CN1303654C - Polishing method and device - Google Patents
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- CN1303654C CN1303654C CNB031491049A CN03149104A CN1303654C CN 1303654 C CN1303654 C CN 1303654C CN B031491049 A CNB031491049 A CN B031491049A CN 03149104 A CN03149104 A CN 03149104A CN 1303654 C CN1303654 C CN 1303654C
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Abstract
The present invention relates to a polishing method and polishing equipment suitable for the polishing method. In the method, the millstone comprising grinding material granules and abrasive resin pasting the grinding material granules. The millstone with required elastic modulus can be obtained by utilizing the abrasive resin pasting the grinding material granules, and can be used for flattening the surface of a substrate with concave and convex parts, and the dimension of the concave and convex parts is not considered. In addition, the surface of the substrate is firstly polished by a polishing tool with low elastic modulus, and then is polished by a polishing tool with high elastic modulus so as to obtain a polished surface with reduced damage. The method of the present invention can effectively plane various substrates with concave and convex parts.
Description
The application is that the name that proposes September 13 nineteen ninety-five is called the dividing an application of No. 95197955.8 patent application of " finishing method and equipment ".
Affiliated field
The present invention relates to a kind of technology, particularly a kind of finishing method that is used to make the technology of semiconductor integrated circuit, and the polissoir that is used for this finishing method by surface polishing substrate surface figure.
Background technology
Semiconductor fabrication process comprises multistage processes.At first a kind of Wiring technique is described below, a craft embodiment in being applied to as the present invention with reference to Fig. 1 (a)-1 (f).
Fig. 1 (a) is the profile that has the wafer of first wiring layer formed thereon.On the surface of the wafer substrates 1 that has transistor part formed thereon, form dielectric film 2, for example form wiring layers 3 such as aluminium lamination on the dielectric film 2 again.For connecting this transistor, in dielectric film 2, form contact hole, so the position corresponding to contact hole of wiring layer is recessed a bit, herein by 3 ' expression.In the second layer Wiring technique shown in Fig. 1 (b), on ground floor, form dielectric film 4 and metal aluminium lamination 5, and on aluminium lamination, apply photoresist film 6, be used for exposure, make aluminium lamination form wiring figure.Then, shown in Fig. 1 (c), utilize 6 exposures of 7 pairs of photoresist films of stepper to transmit the wired circuit figure of the second layer thus.In this case, if the surface irregularity of photoresist film 6, the lip-deep jog by 8 expressions of photoresist film can not focus on simultaneously, so cause resolution unsatisfactory, this is a very serious problem.
For fear of the problems referred to above, studied following planarization technology to substrate surface.After step shown in Fig. 1 (a), shown in Fig. 1 (d), after forming insulating barrier 4, utilize after this method of explanation is polished, smooth so that layer 4 flattens, reach the level shown in the same figure center line 9.In this way, obtain state shown in Fig. 1 (e).After this, form metal aluminium lamination 5 and photoresist layer 6, utilize the stepper 7 shown in Fig. 1 (f) to expose then.In this case, the not satisfied the problems referred to above of resolution can not take place.
Fig. 2 has showed the chemical mechanical polishing method that generally is used for the above-mentioned dielectric film figure of complanation before this.Polishing pad 11 is fixed on the platform 12, and can rotate.About polishing pad 11, for example can be with by the foam urethane resin be cut into slices, and be molded into the polishing pad that thin slice obtains.According to the type of workpiece and the surface roughness that will reach, from various materials and fine surface structure, select suitable material and fine surface structure.On the other hand, wafer 1 to be processed is fixed on the wafer holder 14 by springform platen 13.In wafer holder 14 rotations, wafer is forced on the surface of polishing pad 11, and adds polishing suspension-turbid liquid 15 to polishing pad, and the projection of jettisoning wafer surface upper nonconductive Film 4 obtains flat surfaces thus.
Under the situation of polishing, use colloidal silica usually as the polishing suspension-turbid liquid as dielectric films such as silicon dioxide films.Colloidal silica is that the thin silica granule of about 30nm for example is suspended in the alkaline aqueous solution such as potassium hydroxide solution with diameter.Because the additional chemical effect of alkali uses the characteristics of this colloidal silica to be, compare with the mechanical polishing that utilizes abrasive material separately, can obtain high treatment effeciency and smooth surface, and process-induced damage reduces.Known this in processing procedure, between polishing pad and workpiece, provide the polishing suspension-turbid liquid method be free abrasive polishing technology.
Taking it by and large, utilize the conventional wafer plane technology of this free abrasive polishing method that two difficult problems that will solve are arranged.A difficult problem is the dimension of picture relevant issues, under certain type figure or highly different certain situation, can not reach gratifying complanation degree.Another difficult problem is that the cost of the required particle consumption of glossing is too high.To elaborate below the problem to these.
Generally speaking, on semiconductor wafer, form figure with different size and differing heights.For example, in semiconductor storage unit, shown in Fig. 3 (a), a chip is divided into four substantially, every intermediate rule and form meticulous memory cell thick and fast, and cell mesh is called as memory block part 16.Form peripheral circuit 17 along four memory block segment boundaries, be used to visit said memory cells.Under typical dynamic memory situation, a chip is of a size of about 7mm * 20mm, and the wide of peripheral circuit 17 is about 1mm.The cross section that A-A ' along the line gets chip, shown in Fig. 3 (b), the average height of memory block part 16H is about 0.5-1 μ m, is higher than the height of peripheral circuit part 17L.If form the thick dielectric film 4 of about 1-2 μ m on this step-like figure, then the section shape 31 of surface portion reflects the step shape of bottom figure basically.
With the planarization technology that the present invention was devoted to, the dielectric film 4 on the wafer surface will become shown in the chain-dotted line 32 smooth like that.Yet, when the purpose of utilizing the common soft polishing pad that forms by polyurethane foam to be used to imagine, because the relation of polishing velocity and figure can't realize the above-mentioned complanation of wanting.More specifically, as shown in Figure 4, if use soft polishing pad 11L, then pad interface can resemble among the figure shown in the solid line 30 be out of shape because of the polishing load.Because be point-load, can throw the fine pattern of flat micron dimension size at short notice, but under the big dimension of picture situation of millimeter magnitude, because be that the distributed load polishing velocity is very low.So polishing back section shape becomes the appearance shown in the dotted line 34 among the figure, still residual have a difference in height d.
Make polishing pad can improve flatness more firmly, but in this case, can bring the new problem that the processing inhomogeneities increases in the wafer plane scope, and as later on the process-induced damage problem that illustrates.About this PROCESS FOR TREATMENT inhomogeneities cause of increased that occurs when utilizing hard polishing pad, also not fully aware of.But infer it to be that the lip-deep fine structure of the polished pad of abrasive material that is added to pad interface is partly captured, enter polishing pad and the probability that will handle between the substrate changes, and this change meeting impacts processing.This uniformity that requires in the semiconductor wires technology is below ± 5%.At present, polishing pad hardness on be limited to Young's modulus for about 10kg/mm
2Therefore, in comprising the semiconductor device that little figure and big figure and the magnitude various figures from the millimeter to the micron etc. mix, in memory device, can not wish to have gratifying complanation effect.For this reason, can be limited to the semiconductor product that does not contain very big figure to the product of this polishing pad, for example logic LSI.
As for the polishing pad with the characteristic between hard and soft polishing pad, Japan's special permission discloses and discloses a kind of polishing pad that comprises soft polishing pad and be embedded in the hard polished silicon wafer in the part soft polishing pad among the flat 6-208980.Yet the polishing characteristic that is acquired is almost identical with the polishing pad that middle hardness is arranged.
Second purpose that will realize based on the semiconductor wafer planarization technique of the free abrasive polishing method of above-mentioned routine is to reduce very high production cost.The reason that production cost is high is that the utilance of the used polishing suspension-turbid liquid of free abrasive polishing method is very low.More specifically, for the super smooth polishing that does not cause scar, must for example carry polishing suspension-turbid liquids such as colloidal silica with the speed of per minute hundreds of cc at least.Yet the major part of suspension-turbid liquid is wasted, and actual treatment is not made contributions.And the cost of the high-purity suspension-turbid liquid of semiconductor is quite high, and the cost overwhelming majority of complanation glossing depends on this polishing suspension-turbid liquid.So, be badly in need of in this making moderate progress.
As for the existing method except that the said method of being mentioned, 80-85 page or leaf (Seoul at first international ABTEC proceedings, in November, 1993) a kind of bonding material facture has been described, wherein by abrasive material and metal powder or resin-bonding being manufactured the grinding stone of high speed rotating.Yet known this method exists the shortcoming that causes scuffing through regular meeting on treatment surface.In addition, for solving this scuffing problem, Japan's special permission discloses and discloses the planarization technique that a kind of utilization has the fines grinding stone of the minimum particle diameter of making by electrophoresis among the flat 6-302568.Yet, according to this technology, because grinding stone self is very hard, so still exist by in the used polishing fluid or handle the scuffing problem that dust contained in the atmosphere etc. causes.
In utilizing the conventional semiconductor wafer planarization technique of free abrasive polishing method, as mentioned above, not allowing the minimum dimension of complanation simultaneously is the fine pattern of micron dimension and the big figure of millimeter magnitude.So this routine techniques is applied to comprise that the semiconductor integrated circuit of all big figures and little figure is as still very difficult in the manufacturing of storing LSI.And the required cost of glossing is quite high, the fatal shortcoming that causes it to be applied to produce in batches.
The objective of the invention is to overcome above-mentioned defective of the prior art, provide a kind of big figure and fine pattern plane are changed into same plane and do not produce any processing Treatment injury method, and the equipment that is used for described processing method.
Another purpose of the present invention provides a kind of processing method cheaply and is used for the equipment of described processing method.
Summary of the invention
Adopt the fixed-abrasive processing method of utilizing polishing tool (as grinding stone), replace utilizing the conventional free abrasive polishing technology of polishing pad and polishing suspension-turbid liquid, can realize above-mentioned purpose of the present invention with controlled elasticity modulus.
And, need not resemble and utilize all figures of single treatment complanation the prior art, but by utilizing at first those fine patterns of easily being damaged of a complanation of soft polishing tool, utilize hard polishing tool such as hard grinding stone or polishing pad then, with the bigger big figure of strength highly-efficient treatment rate ground levelization, can solve the processing damage problem of incident hyperfine figure when utilizing hard polishing tool.
Because the treatment conditions that fixed-abrasive facture of the present invention is used certain grinding stone and most suitably selected according to the physical property of workpiece, so, promptly use hard polishing tool, also can make the correlation of planarization process and figure very little, and make the inhomogeneities of the processing speed on the substrate plane very little, do not cause the inhomogeneous of processing.In addition, because do not need expensive polishing suspension-turbid liquid, so cost can be very low.And the cleaning after the processing becomes and is easier to.
In addition, if earlier with soft polishing pad polishing, cutting and the rounding of soft easily be subject to processing damage hyperfine figure corner part and be easy to the corner part of the large scale figure of jettisoning, establish the strong hard polishing pad complanation of function with shape then, then can obtain satisfied treatment surface, and reducing, and non-processor damage with the correlation of graphic width.
Although illustrated below that the present invention uses to as if semiconductor wafer, the present invention also can be applied to the complanation of thin-film display part and glass and ceramic substrate.
Brief description
Fig. 1 (a)-1 (f) is the exemplary plot of the technology of complanation wafer surface;
Fig. 2 is a diagrammatic sketch of explaining cmp method;
Fig. 3 (a) is the plane graph of semiconductor storage unit, and Fig. 3 (b) is its profile;
Fig. 4 is the diagrammatic sketch of explaining with the problem in the finishing method of soft polishing pad;
Fig. 5 explains the diagrammatic sketch that is used for grinding stone configuration of the present invention;
Fig. 6 is the diagrammatic sketch of explaining with the problem in the finishing method of hard polishing pad;
Fig. 7 (a) is a diagrammatic sketch of explaining the polishing condition of prior art, and Fig. 7 (b) is a diagrammatic sketch of explaining polishing condition of the present invention;
Fig. 8 (a)-8 (e) is a diagrammatic sketch of explaining the embodiment of the invention;
Fig. 9 shows the diagrammatic sketch that is applicable to the structure example of implementing treatment facility of the present invention;
Figure 10 (a)-10 (e) is a kind of profile of semiconductor device, shows production process of semiconductor device; And
Figure 11 is the plane graph of device shown in Figure 10 (e).
Most preferred embodiment
Describe embodiments of the invention below in detail.The invention is characterized in, replace conventional polishing pad in the equipment shown in Figure 2 with the specific grinding stone of hardness with control best.As above explanation to prior art, the known technology on rubbing stone planarized semiconductor wafer surface of utilizing has several.But all these technology all exist in the shortcoming that causes tiny scuffing on the treatment surface.So still can not drop into practical application.
Up to the present, think that the reason that causes this scuffing mainly is that particle size is too big.Yet the inventor discovers, this problem should be too big owing to the modulus of elasticity of used grinding stone, rather than the problem of particle size.
The invention is characterized in, utilize as shown in Figure 5 particle 21 looselys and the bonding dead-soft grinding stone of barras 22, replace above-mentioned densification and hard grinding stone.Say that more specifically the modulus of elasticity of grinding stone is 5-500kg/mm
2, so its hardness is that 1/10th of conventional grinding stone arrives one of percentage.On the contrary, hard five to 50 times of the rigid polyurethane foam etc. that for example has been used for the field that the present invention uses than hard polishing pad.
Hereinafter with reference to example the method for making this soft grinding stone is described.The preferred embodiment of particle 21 is silicon dioxide, cerium oxide and alumina particle.Particle diameter is that the particle of 0.01-1 μ m can be realized high handling rate and can not cause scuffing.As for the resin 22 that bonding particle is used, preferred among the present invention as high-purity organic resins such as phenolic resins.After kneading with binder resin, particle is solidified, then, if necessary carry out as processing such as hot curings by applying suitable pressure.Use this manufacture method,, can control the hardness of gained grinding stone by type and the institute's plus-pressure of suitably selecting binder resin.Among the present invention, the Hardness Control of used grinding stone is 5-500kg/mm at modulus of elasticity
2
The example that the grinding stone that utilizes the said method manufacturing is handled below will be described.Using by the cerium oxide of bonding particle diameter 1 μ m and the modulus of elasticity of phenolic resins acquisition is 100kg/mm
2Grinding stone when handling the silicon dioxide film of a micron thickness, can obtain gratifying treatment surface, the gained surface roughness is 2nmRa, and is the fabulous graphic width correlation of 0.3+0.01 μ m/min with respect to all types graphics process speed in the 10mm-0.5 mu m range.Do not observe inhomogeneous that any wafer surface that betides when using hard polishing pad handles.Can infer that this is because the cause of the bonding material different with the conventional treatment of using no abrasive material has been used in processing of the present invention.
Although only provide pure water to make polishing fluid in the above-mentioned processing example, much less, can provide the alkalescence or the acid liquid that resemble in the conventional polishing technology according to the type of workpiece.When workpiece is silicon dioxide or silicon, preferably use alkalies, and workpiece is during as metals such as aluminium or tungsten, preferably uses acid liquid.
When needing the surface roughness of higher level, obviously can satisfy this demand by utilizing above-mentioned grinding stone polishing back with soft polishing pad finishing workpiece surface.
If the modulus of elasticity of used grinding stone exceeds above-mentioned scope, then can't handle satisfactorily.More particularly, if the modulus of elasticity of grinding stone less than 5kg/mm
2, then can only the little figure of fast polishing width, that is, the correlation apparition of graphic width, the result can't the complanation memory device.On the contrary, if the modulus of elasticity of used grinding stone greater than 500kg/mm
2, then no matter how little the particle diameter of grinding stone is, still can have scuffing problem to be solved.In other words, the 5-200kg/mm that has only the modulus of elasticity of grinding stone to be advised here
2In the scope, can be applicable to semi-conductive processing.More preferably scope is 50-150kg/mm
2
Even under above-mentioned use grinding stone condition,, on the figure that will polish, add excessive polish pressure if consider from improving the treatment effeciency aspect, and also can be different from the processing damage problem of above-mentioned scuffing problem, this depends on the shape that will polish figure.To be illustrated handling damage problem below.
As shown in Figure 6, when utilizing hard grinding stone or polishing pad 11H to polish, in the polishing process, the surface of polishing tool can only contact with the bossing of step figure.At this moment, if add excessive polish pressure on this figure, then the end 35 of figure is subjected to the moment introduced because of frictional force, and can resemble shown in the dotted line 36 peel off or cave in, or at the base portion of figure tiny be full of cracks 37 takes place.Although different and different according to treatment conditions, 37 the degree of depth of chapping is usually greater than the level of required complanation, to having caused harmful effect as polishing reliability of products such as semiconductor device.Because the damage problem of this fine pattern need utilize hard polishing tool slowly to carry out complanation work with low-pressure, need the quite long processing time for this reason.
Utilize following method to address the above problem with explanation.Cause the reason and the basic thought of the present invention that prevents this damage of above-mentioned figure damage below with reference to Fig. 7 explanation.Among the same figure, top two width of cloth figure have showed that the protruding figure on the wafer substrates is pressed onto hard polishing pad 11H and goes up situation, and bottom two width of cloth figure have showed the stress distribution that acts on the figure.Just after the polishing beginning, the figure end still is angled, so stress concentrates on each end of wide figure 101, shown in 102, its maximum has reached more than ten times of mean stress.In addition, act on stress 104 on the narrow figure 103 also near described maximum.In this case, if between polishing pad and wafer substrates relative motion takes place, the frictional force that then is proportional to above-mentioned stress will affact on the different piece of figure.If these frictional force are greater than the mechanical strength of graphic material, then the end of figure can be peeled off or fine pattern can cave in.The reason that Here it is causes figure to damage.
The figure damage problem of concentrating owing to the above-mentioned stress of handling the starting stage can cause the figure corner part that stress is concentrated and remove fine pattern and solved by removing in advance.More specifically say, shown in Fig. 7 (b), can pass through the corner part 105 of the wide figure of rounding, or, shown in 106, solve described problem by reducing height and its corner part of rounding of fine pattern.The stress distribution of this figure can not concentrated, shown in the latter half among the same figure, so even utilizing the polishing tool harder than prior art polishing tool can apply bigger polish pressure yet.As a result, can realize the processing of graphic width correlation minimum at short notice.
Above-mentioned basic thought can be achieved by two polishing steps.In this, describe instantiation in detail with reference to Fig. 8 (a)-8 (e) below.The first step (Fig. 8 (a) and 8 (b)) is utilized soft polishing pad 11L (punctulate pad is gone up on pad surface, SUPREMERN for example, the product of RODEL NITTA company) and is polished the suspension-turbid liquid (not shown), and polishing will be handled wafer surface about 31 1 minutes.The polishing suspension-turbid liquid can be with any as in colloidal silica, cerium oxide and the aluminium oxide etc. extremely commonly used.Shown in Fig. 8 (c), handle the preceding submicron order fine pattern part that exists by having polished away, and the corner part of the big figure of rounding.
Then, second step, utilize the strong hard polishing tool 11H of planarization application, for example the polishing of the grinding stone of configuration shown in Figure 5 is about 3 minutes.Because the above-mentioned first step has been removed easily vulnerable fine pattern, so promptly use the polishing tool hard than the first step, the fine pattern base portion can not chap yet, and can carry out the not damaged planarization technology, shown in Fig. 8 (c).
The polishing tool of second step polishing usefulness has no particular limits, as long as it can plane earth high speed polishing wafer surface.Not only can be with the grinding stone of polishing usefulness, and can use very common the combining of the conventional hard polishing pad that forms by polyurethane foam and colloidal silica.Yet, utilize modulus of elasticity at 5-500kg/mm
2Grinding stone in the scope can obtain smooth at short notice and not have the polished surface of be full of cracks.
Like this,, carry out planarization technology with the strong hard instrument of high rigidity of shape establishment effect then, can obtain undamaged basically burnishing surface by at first removing visuals easy to crack with soft instrument.This effect is to find first by the concrete experiment that the inventor carries out.It is well-known before this to utilize a plurality of polishing steps to obtain the technology of final treatment surface, as the technology of the clear 1-42823 peace of the open Nos of Japan's special permission 2-267950 so openly.In all these known methods, generally manage efficient aloft but after easily causing the polishing step of damage, be intended to remove the level and smooth step of the damage that produces in the polishing step.For this reason, the polishing pad that the hardness of used polishing pad is used in going on foot greater than second in the first step.The present invention is intended at first remove the factor that causes this processing damage in contrast, and therefore technological thought of the present invention and known method are far from each other.
Figure 10 (a)-(e) has showed the example of the manufacturing process of the present invention of the memory cell that comprises a transistor and an electric capacity.Figure 10 is the profile of being got along A-A ' line among Figure 11.Among these figure, numeral 110 expression source regions, numeral 120 expression drain regions, numeral 111 and 121 is represented the coupling part of bonding pad 110 and 120 respectively, numeral 210 expression capacitor lower electrodes, numeral 230 expression electric capacity top electrodes, numeral 106 expression bit lines, numeral 141 expression gate electrodes.
Figure 10 (a) is the profile of P type silicon substrate 101, by the selective oxidation method, formed the silica element-isolating film 102 of thick 800nm on this substrate, the electricity that is used between memory cell is isolated, and has also formed the silicon oxide film of the gate insulating film that is used for switch mos transistor.After this, inject boron-doping by ion, with the threshold voltage of control MOS transistor, and by chemical vapor deposition method (after this abbreviating the CVD method as), the polysilicon film of the thick 300nm of deposit is as gate electrode 141.Then, shown in Figure 10 (b), utilize known photoetch technology, form transistorized gate electrode 141 of MoS and gate insulating film 130.Mix phosphorus in the polysilicon film, make it conduction.Subsequently, mix arsenic, form the source region 110 and the drain region 120 of MOS transistor by the ion injection.
Then, shown in Figure 10 (c), with PSG (phosphorus glass) film 103 of CVD method thick 500nm of deposit on substrate surface,, carry out the polishing of complanation then, to about 200nm as interlayer dielectric.The modulus of elasticity of polishing psg film 103 used grinding stones is 50kg/mm
2
Then, on psg film, form coupling part 111, and form bit line 106 (Figure 11).
Then, shown in Figure 10 (d),,, carry out the polishing of complanation then, and, form coupling part 121 by the photoetch windowing as interlayer dielectric with the psg film 104 of the thick 500nm of CVD method deposit.The modulus of elasticity of polishing psg film 104 used grinding stones is 50kg/mm
2If, be 50kg/mm with modulus of elasticity by polishing same film with conventional soft polishing pad
2Grinding stone carry out the polishing of psg film, then can reduce the damage in the polishing.
Subsequently, form the polysilicon film that is used as capacitor lower electrode 210 with the CVD method, and be processed into required form.In addition, in this polysilicon film, mix phosphorus, make this film conduction.Then, on polysilicon film, form capacitor insulating film 220 and capacitance electrode 230 (Figure 10 (e)).
Utilize said method, can make memory cell surface ratio prior art more smooth, and can obtain fine structure and semiconductor device with high reliability.
Be applicable to the formation of implementing treatment facility of the present invention below with reference to Fig. 9 explanation.This equipment is actually two and presses the polissoir of mill, two header structures, but it is characterized in that pressing polishing tool and their method of operation on the mill.The grinding stone that has the above-mentioned low elastic modulus grinding stone that is bonded in its upper surface presses mill 51 and the polishing that has the polishing pad that is bonded in its upper surface to press mill 52 all to rotate with the constant speed about 20rpm.Conveying robot 54 will be handled wafer 55 and take out from magazine 53, and be positioned on the load ring 57 of carrying on the direct acting carrier 56, then, directly effect carrier 57 is moved to the left in the drawings, arrive charging/discharge position, polishing arm A58 rotation on it, wafer 55 is sandwiched in the downside that (clamping) device 59 is fixed in the wafer polishing that is arranged at the polishing arm end by vacuum.Then, polishing arm A58 rotation makes fixture 59 be positioned polishing pad and presses on the mill 52.To shift onto downwards on the polishing pad 52 attached to the wafer 55 of fixture downside in the time of fixture 59 rotations, so that providing under the condition of polishing the suspension-turbid liquid (not shown) about 1 minute of wafer polishing.By this polishing operation, remove the fine pattern part of submicron order on the wafer surface, this part is easy as before described to be subject to processing damage, and the corner part of rounding large scale figure.
After having finished above-mentioned first polishing step, polishing arm A58 rotation is pressed on the mill 51 so that wafer polishing fixture 59 is positioned grinding stone.Then, the wafer 55 that will be clamped in the fixture downside in the time of fixture 59 rotation is shifted grinding stone downwards onto and is pressed on the mill 51, and polishing suspension-turbid liquid (not shown) is provided in the same manner as described above, grinding wafers 55 about two minutes.After second polishing step finished, polishing arm A58 rotated again, so that wafer polishing fixture 59 navigates to the position that mill 52 is pressed in polishing, and polished wafer 55 about a minute in the same manner as described above.This polishing operation behind the grinding technics is used for removing slight scuffing that grinding technics causes etc.Certainly, the glossing of being discussed can omit, and this depends on grinding situation or required surface roughness rank.
Finished glossing by above-mentioned three steps polishing, then, by the cleaning clean wafers.Polishing arm A58 rotation, so that wafer polishing fixture 59 places on the cleaning positions, the cleaning positions place is provided with rotating brush 60.During rotation, utilize the rinsing brush, rotating brush 60 cleans the treated side of the wafer 55 that is sandwiched in fixture 59 downsides.After cleaning end, directly act on carrier 56 and be moved upwards up to again on the above-mentioned cleaning positions, receive the wafer that discharges from the vacuum cup of fixture 59.
Can replace the above rotation of using to scrub with the ablution that utilizes the water spout under the ultrasonic wave effect.
Then, when directly acting on carrier 56 and getting back to charging/discharge position again, carrying wafers manipulator 54 is clamped the wafer of handling, and it is loaded on unloads in the magazine 61.These are operational cycle of polishing arm A58.In these operations simultaneously, polishing arm B62 also works in an identical manner.Certainly, this will share mode with the time and effectively utilizes two polished land.The operating sequence of polishing arm B62 is identical with polishing arm A58, but its phase lag half period.That is, polishing arm B62 and above-mentioned second polishing step are started working synchronously.
The suitable polishing arm of the structure of the foregoing description is two a situation.In this structure, if the position that exists the rotate path of two polishing arms to intersect or contact with each other, if reach the stop position that this position provides a pair of cleaning brush and directly acts on charging/discharging carrier, then two polishing arms can be realized its relevant function.
Although the foregoing description adopts two polishing arms, need not, for simplified structure can be only with a polishing arm.On the contrary, be to improve the output of equipment, can be with three above polishing arms, or fix a plurality of wafer polishing fixtures on the single polishing arm, and, although use two rotation platforms that independently are used to fill up with grinding stone in the foregoing description, can be only with a rotation platform.In this case, annular grinding stone is arranged at the periphery of rotation platform, and polishing pad places the centre of platform, also can adopt the design of rotating platform inclination with the intersection point (convex area of installation) of minimizing equipment.
The present invention not only can be applied to semiconductor device, can also be applied to liquid crystal display device, microfabrication, magnetic disk substrate, compact disc substrate, Fresnel Lenses, and other have the optical element of fine surface structure.
Claims (6)
1. method, semi-conductor device manufacturing method is used for utilizing at least one first polishing tool and one second polishing tool to come complanation one to be formed on the semi-conductive substrate surface and having the film of convex-concave pattern by substep, comprises the following steps:
To have on the surface that this Semiconductor substrate that is formed on its lip-deep this convex-concave pattern alternately presses against the surface of this first polishing tool and this second polishing tool; And
Make between the surface of this semiconductor substrate surface and this first polishing tool and this second polishing tool and produce relative motion;
The modulus of elasticity of first polishing tool that wherein, is at first used is less than the modulus of elasticity of second polishing tool that is used subsequently.
2. method, semi-conductor device manufacturing method according to claim 1 is characterized in that first polishing tool that is used is one to comprise the polishing pad of resin.
3. method, semi-conductor device manufacturing method according to claim 1 is characterized in that this second polishing tool comprises abrasive grain and a kind ofly is used for bonding and fixes the material of this abrasive grain.
4. method, semi-conductor device manufacturing method according to claim 3, the modulus of elasticity that it is characterized in that this second polishing tool is 5-500kg/mm
2
5. method, semi-conductor device manufacturing method as claimed in claim 3 is characterized in that abrasive grain as a kind of component of this second polishing tool is the particle of the mixture of any one or they in silicon dioxide, cerium oxide and the aluminium oxide.
6. method, semi-conductor device manufacturing method as claimed in claim 3 is characterized in that particle diameter as the abrasive grain of a kind of component of this second polishing tool is not less than 0.01 micron and be not more than 1 micron.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95197955A CN1197542A (en) | 1995-09-13 | 1995-09-13 | Grinding method of grinding device |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95197955A Division CN1197542A (en) | 1995-09-13 | 1995-09-13 | Grinding method of grinding device |
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| CN1516247A CN1516247A (en) | 2004-07-28 |
| CN1303654C true CN1303654C (en) | 2007-03-07 |
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| CNB031491049A Expired - Lifetime CN1303654C (en) | 1995-09-13 | 1995-09-13 | Polishing method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2008290233A (en) * | 2007-05-21 | 2008-12-04 | Applied Materials Inc | Method and device for high-performance low-cost polishing tape for polishing slope and edge of substrate in semiconductor manufacture |
| CN216781428U (en) * | 2021-09-07 | 2022-06-21 | 杭州众硅电子科技有限公司 | Wafer polishing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4459779A (en) * | 1982-09-16 | 1984-07-17 | International Business Machines Corporation | Fixed abrasive grinding media |
| US4654051A (en) * | 1984-10-26 | 1987-03-31 | Tohoku Chemical Industries, Ltd. | Grinding wheel |
| US4750915A (en) * | 1985-02-22 | 1988-06-14 | Kanebo, Ltd. | Composite whetstone for polishing soft metals |
| EP0272531A1 (en) * | 1986-12-08 | 1988-06-29 | Sumitomo Electric Industries Limited | Surface grinding machine |
-
1995
- 1995-09-13 CN CNB031491049A patent/CN1303654C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4459779A (en) * | 1982-09-16 | 1984-07-17 | International Business Machines Corporation | Fixed abrasive grinding media |
| US4654051A (en) * | 1984-10-26 | 1987-03-31 | Tohoku Chemical Industries, Ltd. | Grinding wheel |
| US4750915A (en) * | 1985-02-22 | 1988-06-14 | Kanebo, Ltd. | Composite whetstone for polishing soft metals |
| EP0272531A1 (en) * | 1986-12-08 | 1988-06-29 | Sumitomo Electric Industries Limited | Surface grinding machine |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1516247A (en) | 2004-07-28 |
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