EP1458102B1 - Hochauflösender Digital Analog Wandler mit geringem Leistungsverbrauch - Google Patents

Hochauflösender Digital Analog Wandler mit geringem Leistungsverbrauch Download PDF

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Publication number
EP1458102B1
EP1458102B1 EP03425160A EP03425160A EP1458102B1 EP 1458102 B1 EP1458102 B1 EP 1458102B1 EP 03425160 A EP03425160 A EP 03425160A EP 03425160 A EP03425160 A EP 03425160A EP 1458102 B1 EP1458102 B1 EP 1458102B1
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Prior art keywords
group
voltage
digital
current
digital code
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EP03425160A
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English (en)
French (fr)
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EP1458102A1 (de
Inventor
Pierangelo Confalonieri
Germano Nicollini
Ricardo Martignone
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STMicroelectronics SRL
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STMicroelectronics SRL
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Priority to EP03425160A priority Critical patent/EP1458102B1/de
Priority to DE60307039T priority patent/DE60307039T2/de
Priority to EP06116241A priority patent/EP1710917A1/de
Priority to US10/791,663 priority patent/US7098831B2/en
Publication of EP1458102A1 publication Critical patent/EP1458102A1/de
Priority to US11/272,937 priority patent/US7348912B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/687—Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators
    • H03M1/745—Simultaneous conversion using current sources as quantisation value generators with weighted currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/76—Simultaneous conversion using switching tree
    • H03M1/765—Simultaneous conversion using switching tree using a single level of switches which are controlled by unary decoded digital signals

Definitions

  • the present invention relates to a digital-analog converter as defined in the preamble of Claim 1 and as disclosed for example, in the closest prior art document US-B1-6 486 818.
  • a schematic representation of a D/A converter commonly used for this purpose is shown in Figure 1.
  • the gate terminal of the transistor M1 is connected to the output of an operational amplifier OPA1, which has an inverting input connected to a reference voltage source Vref and a non-inverting input connected to the connection node N1 between the resistive divider and the drain terminal of the transistor M1.
  • SWO-SW4095 electronic switch
  • the current I that passes the resistive divider is regulated in such a way as to maintain the node N1 at a voltage equal to the reference voltage Vref.
  • the voltage Vin is amplified by the operational amplifier OPA2 with a gain determined by the resistors R1 and R2.
  • the D/A converter described above is characterized by an intrinsic monotonicity, because the divider voltage that from time to time is applied to the input of the amplifier OPA2 increases / diminishes as the digital code to be converted increases / diminishes and is therefore suitable for being employed in the systems cited at the beginning.
  • the gain of the converter can be regulated at will by means of resistors (R1 and R2) that are not in any way related with the resistors of the resistive divider, so that they can be chosen to have a relatively high value and thus reduce the electricity consumption to a minimum.
  • resistors R1 and R2
  • resistors moreover, cannot be realized as normal polysilicon resistors when the divider is made up of a large number of resistors. Indeed, the maximum number of resistors is limited by an overall resistance of the divider that makes the current crossing the divider become so small as to make it comparable with the leakage current of the diffused regions of the transistors that perform the function of electronic switches. In this case, moreover, even the conversion time becomes unacceptably long.
  • the resistors are formed by means of a technique that utilizes a special low-resistivity silicon; however, the resistors produced by the use of this technique are often of far from uniform value, so that the production yield of the integrated circuit is low.
  • FIG. 2 Another known converter is shown in Figure 2. It is made up of two sections, a first section for the conversion of the digital code with the more significant bits (MSB) and a second section for the conversion of the part of the digital code with the less significant bits (LSB).
  • DEC-9BIT 9-bit decoding logic
  • the second section is made up of as many current generators (MD0, MD1, MD2) as there are bits considered to be less significant in the code that is to be converted, in this example three bits (D0, D1, D2).
  • the three generators MD0, MD1, MD2 consist of N-channel MOS transistors that can be selectively connected by means of three electronic selectors SD0, SD1 and SD2 controlled by a 3-bit transcoding logic (TRANSCOD-3BIT) between the terminals (Vdd and ground) of the supply source or between the inverting input of an operational amplifier OPA2 (equal to the one of the converter of Figure 1) and ground.
  • the three transistors MD0-MD2 are connected in current mirror fashion to a diode-connected N-channel MOS transistor M3.
  • the transistor M3 is connected in series to a P-channel MOS transistor M2 between the terminals of the supply source (Vdd, ground).
  • the gate terminal of the transistor M2 is connected to the gate terminal of the transistor M1, which stabilizes the voltage applied to the resistive divider, so that the current I of the divider is mirrored in the circuit branch containing M2 and M3.
  • the sizes of the transistors M1, M2, M3, MD0-MD2 are chosen in such a way that the generators formed by the transistors MD0-MD2 are codified in binary form, that is to say, the currents that pass through them are equal to, respectively 2 0 *I/4, 2 1 *I/4 and 2 2 *I/4, and they therefore contribute to the formation of the converter output voltage Vout in the right proportion to represent the three less significant bits of the code to be converted.
  • R1' and R2' are the resistances of the resistors indicated by the same symbol in the figure
  • IL is the current that the generators MD0-MD2 inject into the connection node N2 between the resistors R1' and R2', i.e., into the inverting input terminal of the operational amplifier OPA2.
  • the current IL will amount to 7/4 of the current I that passes through the divider and the contribution to the output voltage will therefore amount to 7/4*I*R, i.e. 7/8 of the contribution of a resistor R of the divider.
  • the converter of Figure 2 has the advantage that, given parity of resolution, it can be integrated into a much smaller area than the converter of Figure 1, this thanks to the fact that it has only one eighth the number of resistors of the divider of Figure 1 and only a few extra transistors; it is, however, associated with some drawbacks that render its use rather problematical.
  • the divider can be realized with equal resistors R having typical values comprised between 20 and 200 Ohm and that the operational amplifier OPA2 may have a gain typically comprised between 1.5 and 2.5, the resistors that determine the gain cannot be chosen with a high resistance, as is possible in the case of the converter of Figure 1, because the feedback resistor R1' must have a value equal to that of a resistor of the divider and R2' cannot have a value much greater than R', so that the consumption of the converter is unacceptably great.
  • the consumption can be reduced by utilizing a feedback resistor R1' of a larger value and using correspondingly smaller current generators MD0-MD2, so that the contribution of the LSB section to the voltage output of the converter remains unchanged.
  • the output voltage Vout may be very close to ground potential, so that when the drain terminals of the transistors MD0-MD2 are connected to the node N2, their voltages may be so low as to cause them to operate in the non-linear zone.
  • One aim of the present invention is to propose a D/A converter that can be integrated into a small area and has only a limited consumption.
  • Another aim of the invention is to propose a D/A converter of great linearity and precision even at the maximum excursion of the output voltage.
  • the converter in accordance with the invention differs from the one of Figure 2 by virtue of the fact that the feedback resistance of the operational amplifier OPA2 consists of two resistors R3 and R4 arranged in series and such that R4 has the same resistance R as a resistor of the divider of the MSB section and R3 has a resistance equal to R2"-R, where R2" is the resistance of the resistor indicated by the same symbol and connected between the inverting input terminal and ground.
  • the current of the generators of the LSB section is injected into the node N3 between the two resistors in series.
  • the resistance R2" can be chosen as large as desired, without there being any constraint deriving from the elementary resistance R of the divider, and this makes it possible to have a converter that not only occupies a small area thanks to the reduction (1/8) of the number of resistors of the divider, but also has a small consumption.
  • Figure 4 shows a second embodiment of the invention that likewise solves the problem of the poor precision in the case of extensive excursions of the output voltage.
  • the LSB section has been modified as compared with Figure 3: more particularly, two groups of generators are now used in place of the single group of generators made up of N-channel transistors: one of these still consists of three N-channel transistors, indicated by MD0N, MD1N and MD2N, while the other consists of four P-channel transistors, respectively indicated by MD0P, MD1P, MD2P and MOP.
  • the three transistors MD0P-MD2P have the function of generators codified in binary form and the transistor MOP has the function of a complementary generator, as will be made clear by the explanation about to be given, and has the same weight as the generator of least weight among the three generators codified in binary form.
  • the two groups of generators can be activated alternatively.
  • the current I passing through the MSB section is mirrored both in the branch constituted by the transistors M2 and M3, as in Figures 2 and 3, and also in a supplementary branch consisting of one N-channel transistor M5.
  • the gate electrode of the transistor M4 is connected to the gate terminals of the four P-channel transistors MD2P, MD1P MD0P and M0P, which can be selectively connected, by means of four electronic selectors SD2P, SD1P, SD0P and SOP controlled by a 3-bit transcoding logic (TRANSCOD-3BIT'), between the supply source terminals (Vdd and ground) or between the node N3 of the feedback resistance of the operational amplifier OPA2 and the terminal Vdd.
  • the sizes of the transistors MD2P, MD1P, MD0P and MOP are such that their currents contribute to the formation of the output voltage Vout of the converter in the right proportion for representing the three less significant bits of the code to be converted.
  • MD2P is of the same size as M4, MD1P is 1/2 the size of M4, and MD0P and M0P are both 1/4 of the size of M4.
  • the shown MSB section is identical to that of the converter of Figure 2, but in practice it differs therefrom by virtue of the fact that the electronic switch SW0 always remains open (and can therefore be omitted), that the resistor R connected to the resistor RL can form a single resistor with this latter and that the central switch SW256 is closed by two successive codes 100000000 and 011111111. The reason for these variants will become clear from the explanation of how the converter functions.
  • the three less significant figures of the digital code to be converted are transcoded by the three-bit transcoder (TRANSCOD-3BIT'), the output of which controls the opening and closing of the electronic selectors of the group of N-channel transistors and the group of P-channel transistors.
  • the criterion for the selection of one or the other of the two groups can be different from the one described (based on the value of the most significant bit): in fact, one could take as selector a code other than the central one, always provided that it is comprised in the field of variability of the code to be converted.
  • the minimum value of the output voltage of the section i.e. the input voltage Vin of the operational amplifier OPA2, is given by the voltage drop across RL+R.
  • DEC-9BIT' 9-bit decoding logic
  • the central switch SW256 is activated by two different codes (011111111 and 100000000).
  • the control signals for operating the electronic switches SD0N, SD1N, SD2N associated with the N-channel transistors of the LSB section and the electronic switches SD0P, SD1P, SD2P associated with the P-channel transistors of the LSB section are generated by the 3-bit transcoding logic (TRANSCOD-3BIT') and applied to either one or the other of the two groups of transistors according to the value of the most significant bit (D11) of the code to be converted.
  • the current IL flowing to the node N3 is a function of the code D ⁇ 2:0> and, becoming summed with the voltage due to the MSB section, contributes to forming the output voltage of the operational amplifier OPA2.
  • the gain of the operational amplifier OPA2 is equal to two.
  • the gain may be chosen differently from two by appropriately modifying the resistance of the resistor R4 and/or the size of the N-channel and P-channel transistors that determine the current IL injected into the node N3.
  • the resistance of R4 must not be equal to the resistance of a resistive module R of the divider, but will have to amount to 0.75*R, so that the current may develop a voltage equal to 0.75 times the voltage obtained in the example described above.
  • the minimum current IL causes an output variation equal to 1/8 of the output voltage determined by a resistive module R of the divider.
  • the converter in accordance with the embodiment of the invention shown in Figure 4 makes it possible to attain all the aims of the invention. In particular, it can be integrated into a small area, and has a low consumption and a high precision. Naturally, whenever consumption is not a problem, the converter can be realized by making do without the feedback divider, i.e. using a resistor R3 of zero resistance in accordance with the scheme of Figure 2.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Claims (9)

  1. Ein Digital-zu-Analog-Wandler, um einen digitalen Code, der aus einem ersten Teil von höherwertigen Bits und einem zweiten Teil von niederwertigen Bits besteht, in eine analoge Größe umzuwandeln, der folgende Merkmale aufweist:
    einen Wandlerausgang,
    einen ersten Abschnitt (MSB), um den ersten Teil des digitalen Codes in eine erste Spannung (Vin) umzuwandeln, wobei die erste Spannung aus diskreten Spannungen ist, die ganzzahlige Vielfache eines vorbestimmten ersten Spannungsschrittes (ΔV1) sind,
    einen zweiten Abschnitt (LSB), um den zweiten Teil des digitalen Codes in einen Strom (IL) umzuwandeln,
    eine Einrichtung zum Transformieren des Stroms in eine zweite Spannung, wobei die zweite Spannung aus diskreten Spannungen ist, die ganzzahlige Vielfache eines zweiten Spannungsschrittes (ΔV2) sind, der gleich 1/2L des Produktes des ersten Spannungsschritts (ΔV1) multipliziert mit einem vorbestimmten Koeffizienten ist, wobei L die Anzahl der niederwertigen Bits des digitalen Codes ist, der umgewandelt werden soll,
    eine Steuereinrichtung (DEC-9BIT; TRANSCOD-3BIT) des ersten und des zweiten Abschnitts, und
    eine Summationseinrichtung (OPA2) zum Erhalten der zuvor erwähnten analogen Größe (Vout) als die Summe der zweiten Spannung und des Produktes der ersten Spannung multipliziert mit dem vorbestimmten Koeffizienten, die eine Summationsschaltung mit einer Widerstandsrückkopplungseinrichtung (R3, R4) aufweist, wobei die Summationsschaltung einen Operationsverstärker (OPA2) aufweist, der einen ersten Eingang (-), einen zweiten Eingang (+) und einen Ausgang aufweist, der mit dem Wandlerausgang verbunden ist, wobei die Widerstandsrückkopplungseinrichtung einen Spannungsteiler (R3, R4) aufweist und die Einrichtung zum Transformieren des Stroms in eine zweite Spannung einen Umwandlungswiderstand (R4) aufweist, der einen Teil des Spannungsteilers bildet,
    dadurch gekennzeichnet, dass der Spannungsteiler zwischen dem ersten Eingang (-) und dem Ausgang des Operationsverstärkers (OPA2) definiert und zwischen dieselben geschaltet ist.
  2. Ein Digital-zu-Analog-Wandler gemäß Anspruch 1, bei dem:
    - der vorbestimmte Koeffizient die Verstärkung des Operationsverstärkers (OPA2) ist,
    - der erste Abschnitt (MSB) ein Widerstandsnetzwerk aufweist, das 2M Abgriffe, wobei M die Anzahl der höherwertigen Bits des digitalen Codes ist, der umgewandelt werden soll, und im Wesentlichen gleiche Widerstandswerte (R) zwischen benachbarten Abgriffen und 2M elektronische Schalter (SW0-SW511) aufweist, die jeweils zwischen einen jeweiligen Abgriff und einen gemeinsamen Knoten (N4) eingefügt sind, der mit dem zweiten Eingang (+) des Operationsverstärkers (OPA2) verbunden ist,
    - der zweite Abschnitt (LSB) eine erste Gruppe von L Stromgeneratoren, die in binärer Form kodifiziert sind (MD0-MD2), eine Auswahleinrichtung (SD0-SD2) zum Auswählen von Stromgeneratoren der ersten Gruppe und eine Einrichtung zum Fördern des Stroms der Stromgeneratoren, die durch die Auswahleinrichtung ausgewählt sind, auf einen gemeinsamen Knoten (N3) aufweist, der mit dem Umwandlungswiderstand (R4) verbunden ist, und
    - die Steuereinrichtung eine Einrichtung (DEC-9BIT) zum selektiven Betreiben der elektronischen Schalter (SW0-SW511) in einer derartigen Weise, um jeden der 2M-Abgriffe mit dem zweiten Eingang (+) des Operationsverstärkers gemäß dem ersten Teil (D<11:3>) des digitalen Codes zu verbinden, und eine Einrichtung (TRANSCOD-3BIT) zum selektiven Betreiben der Auswahleinrichtung gemäß dem zweiten Teil (D<2:0>) des digitalen Codes aufweist.
  3. Ein Digital-zu-Analog-Wandler gemäß Anspruch 2, bei dem der zweite Abschnitt (LSB) eine zweite Gruppe von L Stromgeneratoren (MD0P-MD2P), die in binärer Form kodifiziert sind, und eine zweite Auswahleinrichtung (SD0P-SD2P) zum Auswählen der Stromgeneratoren der zweiten Gruppe aufweist und bei dem die Steuereinrichtung eine Auswahllogik aufweist, die alternativ entweder die erste oder die zweite Gruppe demgemäß auswählt, ob der digitale Code, der umgewandelt werden soll, einen vorbestimmten Wert jeweils überschreitet oder nicht.
  4. Ein Digital-zu-Analog-Wandler gemäß Anspruch 1, bei dem:
    - der vorbestimmte Koeffizient die Verstärkung des Operationsverstärkers (OPA2) ist,
    - der erste Abschnitt (MSB) ein Widerstandsnetzwerk (R, RL) aufweist, das 2M-1 Abgriffe, wobei M die Anzahl der höherwertigen Bits des digitalen Codes ist, der umgewandelt werden soll, und im Wesentlichen gleiche Widerstandswerte (R) zwischen benachbarten Abgriffen und 2M-1 elektronische Schalter (SW1-SW511) aufweist, die jeweils zwischen einen jeweiligen Abgriff und einen gemeinsamen Knoten (N4) eingefügt sind, der mit dem zweiten Eingang (+) des Operationsverstärkers verbunden ist,
    - der zweite Abschnitt (LSB) eine erste Gruppe von L Stromgeneratoren (MD0N-MD2N), die in binärer Form kodifiziert sind, eine erste Auswahleinrichtung (SD0N-SD2N) zum Auswählen der Stromgeneratoren der ersten Gruppe, eine zweite Gruppe von Stromgeneratoren, von denen L (MD0P-MD2P) in binärer Form kodifiziert sind,und ein komplementärer Stromgenerator (MOP) die gleiche Gewichtung wie der Generator der geringsten Gewichtung der Stromgeneratoren der ersten Gruppe aufweist, eine zweite Auswahleinrichtung (SD0P-SD2P, S0P) zum Auswählen von Stromgeneratoren der zweiten Gruppe und eine Einrichtung zum Fördern des Stroms (IL) der Stromgeneratoren, die durch die erste oder die zweite Auswahleinrichtung ausgewählt sind, auf einen gemeinsamen Knoten (N3), der mit dem Umwandlungswiderstand (R4) verbunden ist, aufweist;
    - die Steuereinrichtung eine Einrichtung (DEC-9BIT) zum selektiven Betreiben der elektronischen Schalter (SW1-SW511) in einer derartigen Weise, um einzeln jeden der 2M-1 Abgriffe mit dem zweiten Eingang (+) des Operationsverstärkers gemäß dem ersten Teil (D<11:3>) des digitalen Codes zu verbinden, eine Einrichtung (TRANSCOD-3BIT') zum selektiven Betreiben der ersten und der zweiten Auswahleinrichtung (SD0N-SD2N, SDP0-SD2P, S0P) gemäß dem zweiten Teil (D<2:0>) des digitalen Codes und eine Auswahllogik aufweist, die alternativ die erste oder die zweite Gruppe von Stromgeneratoren demgemäß auswählt, ob der digitale Code, der umgewandelt werden soll, einen vorbestimmten Wert jeweils überschreitet oder nicht.
  5. Ein Digital-zu-Analog-Wandler gemäß Anspruch 4, bei dem die elektronischen Schalter des ersten Abschnitts (MSB) eine erste und eine zweite Gruppe von elektronischen Schaltern bilden, die einen elektronischen Schalter gemeinsam haben, und bei dem die Auswahllogik den Betrieb der elektronischen Schalter der ersten oder der zweiten Gruppe von elektronischen Schaltern demgemäß bestimmt, ob der digitale Code, der umgewandelt werden soll, einen vorbestimmten Wert jeweils überschreitet oder nicht, und die permanente Auswahl des komplementären Generators (M0P) der zweiten Gruppe von Stromgeneratoren bestimmt, wenn der digitale Code, der umgewandelt werden soll, den vorbestimmten Wert (D11=0) nicht überschreitet.
  6. Ein Digital-zu-Analog-Wandler gemäß einem der Ansprüche 3 bis 5, bei dem der vorbestimmte Wert durch den digitalen Code ausgedrückt ist, dessen höchstwertiges Bit gleich 0 ist und dessen verbleibende Bits gleich 1 sind.
  7. Ein Digital-zu-Analog-Wandler gemäß einem der Ansprüche 2 bis 5, bei dem die Stromgeneratoren der ersten Gruppe N-Kanal-MOS-Transistoren aufweisen.
  8. Ein Digital-zu-Analog-Wandler gemäß Anspruch 3 oder Anspruch 5, bei dem die Stromgeneratoren der zweiten Gruppe P-Kanal-MOS-Transistoren aufweisen.
  9. Ein Digital-zu-Analog-Wandler gemäß Anspruch 6, bei dem die Stromgeneratoren der ersten Gruppe N-Kanal-MOS-Transistoren aufweisen und die Stromgeneratoren der zweiten Gruppe P-Kanal-MOS-Transistoren aufweisen.
EP03425160A 2003-03-14 2003-03-14 Hochauflösender Digital Analog Wandler mit geringem Leistungsverbrauch Expired - Fee Related EP1458102B1 (de)

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Application Number Priority Date Filing Date Title
EP03425160A EP1458102B1 (de) 2003-03-14 2003-03-14 Hochauflösender Digital Analog Wandler mit geringem Leistungsverbrauch
DE60307039T DE60307039T2 (de) 2003-03-14 2003-03-14 Hochauflösender Digital Analog Wandler mit geringem Leistungsverbrauch
EP06116241A EP1710917A1 (de) 2003-03-14 2003-03-14 Hochauflösender Digital Analog Wandler mit geringem Leistungsverbrauch
US10/791,663 US7098831B2 (en) 2003-03-14 2004-03-02 High resolution and low consumption digital-analog converter
US11/272,937 US7348912B2 (en) 2003-03-14 2005-11-14 High resolution and low consumption digital-to-analog converter

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EP03425160A EP1458102B1 (de) 2003-03-14 2003-03-14 Hochauflösender Digital Analog Wandler mit geringem Leistungsverbrauch

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US8941522B2 (en) 2012-05-04 2015-01-27 Analog Devices Technology Segmented digital-to-analog converter having weighted current sources
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US20040233089A1 (en) 2004-11-25
EP1458102A1 (de) 2004-09-15
US20060066463A1 (en) 2006-03-30
US7098831B2 (en) 2006-08-29
EP1710917A1 (de) 2006-10-11
DE60307039D1 (de) 2006-09-07
DE60307039T2 (de) 2007-01-18
US7348912B2 (en) 2008-03-25

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