EP1396801A1 - Méthode pour développer un composant électronique - Google Patents

Méthode pour développer un composant électronique Download PDF

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Publication number
EP1396801A1
EP1396801A1 EP02019999A EP02019999A EP1396801A1 EP 1396801 A1 EP1396801 A1 EP 1396801A1 EP 02019999 A EP02019999 A EP 02019999A EP 02019999 A EP02019999 A EP 02019999A EP 1396801 A1 EP1396801 A1 EP 1396801A1
Authority
EP
European Patent Office
Prior art keywords
timing
file
layout
information
violation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02019999A
Other languages
German (de)
English (en)
Inventor
Majid Ghameshlu
Karlheinz Krause
Herbert Taucher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to EP02019999A priority Critical patent/EP1396801A1/fr
Priority to US10/654,604 priority patent/US20040139410A1/en
Publication of EP1396801A1 publication Critical patent/EP1396801A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Definitions

  • the invention relates to electronic components, in particular to a process for developing or creating a design of an electronic component in which a Layout for a block and a file with Timing information is generated.
  • ASICs Application Specific Integrated Circuits
  • Called ASICs an arrangement of logic gates, as well as memory circuits and their connections, on a single silicon wafer.
  • ASICs are a collection of circuits with simple functions such as flip flops, inverters, and NANDs NORs as well as of more complex structures, such as memory arrangements, Adders, counters and phase locked loops.
  • the different Circuits are combined in an ASIC to perform a specific application or application.
  • ASICs are used in a variety of products, e.g. Consumer products, such as video games, digital cameras, in vehicles and PCs, as well as in high-end technology products such as Workstations and routers used.
  • timing closure In this final phase, which is known in the field as "timing closure" with the ASIC layout, usually some corrections due to timing violations required.
  • the number of modifications increases with the complexity, the operating frequency and the deep submicron effects.
  • the changes due to Timing violations are required from the timing reports derived from a static timing analysis (STA).
  • STA static timing analysis
  • a time critical current ASIC design can e.g. several thousand Corrections.
  • FIG. 1 An example of a conventional timing closure process is shown in Figure 1.
  • Step 10 After going through the first three ASIC design phases in the previous phases generated net lists, i.e. Lists with Components and their connections on a chip surface placed and wired. Here the previously defined Layout constraints or restrictions are observed.
  • a timing analysis is made in step 11, specifically performed a static timing analysis and timing reports generated, which is then in a subsequent verification step 12 examined for timing violations become. If no timing violations are found, can according to the net lists generated in the last layout production of the ASIC is started.
  • Have been however in step 12 timing violations are found in the Step 14 instead generates so-called patch lists that Type and scope of the necessary timing corrections based on the timing violations previously detected.
  • step 15 is also known as an engineering change order (ECO).
  • ECO step 15 those shown in the patch lists are shown physical corrective actions due to timing violations implemented in the layout. Because the corrective action however, this can have undesirable side effects Go back to step 11, and another static Timing analysis is done. The procedure is repeated now until all timing violations have been resolved.
  • the present invention is therefore based on the problem a process for the development of an electronic component to create an excessive netlist change for the layout is avoided, thereby reducing the overall To be able to shorten the ASIC design process.
  • step d) of modifying the file interventions in this file are now made that are equivalent to those caused by the injury information in the patch list defined physical measures and compliant to a The file format of this file are.
  • the File a file in standard delay format (SDF). hereby the procedure is based on an existing database, namely the SDF file, and enables a new timing analysis without a new layout.
  • SDF standard delay format
  • step a) is a static timing analysis (STA).
  • STA static timing analysis
  • a new patch list is generated, in which violation information is stored to easy rejection or modification of individual modification steps to enable if after the preliminary analysis should point out that a modification is not allowed has led to the desired success.
  • step c) starts of the process when step c) is carried out for the first time set up a patch list and each time it is run again of step c) further injury information obtained attached to the existing patch list. This will all necessary modifications are saved and managed centrally.
  • both the patch lists automatically generate as well the changes to the SDF file perform automatically. This saves time and money for the timing closure significantly reduced since all Steps can be carried out computer-aided.
  • step 16 the preferred method of constructing an electronic Building block described.
  • the process begins in step 16 with the implementation of the final layout or the final one Layouts.
  • a file with timing information is also created generated to the real time behavior of the Control circuit.
  • the file is a so-called SDF file (Standard delay format).
  • the SDF file contains under among other things, the entire timing for all paths in the ASIC. in this connection is the real time behavior of the circuit due to many Factors such as the output driver strengths of each Components, the number of each connected Inputs of other component and the length of the respective connection calculated from the geometric data of the layout and saved in the SDF file.
  • Content and specification of a SDF files are well known in the art and e.g. in the document "Standard Delay Format Specification", Version 3.0, May 1995, published by Open Verilog, described.
  • the timing analysis is a static timing analysis (STA).
  • STA static timing analysis
  • the basis for the timing analysis is the one before generated SDF file that contains all timing values and all paths, which are necessary to carry out the timing analysis, contains.
  • the STA brings all the paths that are relevant to you path to be fully considered are interconnected.
  • the STA continues to sort and combine the paths for a timing analysis and gives so-called timing reports out.
  • Timing violations are generally called hold and Setup violations divided.
  • the setup time is the time period before the rising edge of the synchronization clock. With the hold time, the time period becomes after denotes the rising edge of the synchronization clock. If the setup and hold time criteria e.g. with a flip-flop are not met, this leads to a timing violation and the flip-flop output is not secure guaranteed.
  • timing closure phase can be determined of the ASIC design, and which from the last layout generated corresponding net lists used for ASIC production (step 19).
  • step 20 so-called Patch lists created in which the positions in the ASIC are listed where to intervene to avoid the timing violations to correct.
  • the patch lists contain the preferred Embodiment also information about physical Actions to be taken to ensure that Eliminate timing violations. On these measures discussed in more detail below.
  • the SDF file adjusted for the corrections is now in the Step 22 used for a new static timing analysis.
  • This preliminary STA shows whether the measures taken eliminate the timing violations previously detected, whether the measures cover all injuries (completeness) and whether the corrections have undesirable side effects.
  • step 23 those supplied by the STA 22 are again Timing reports checked for injuries. provides out in step 23 that there is still timing violations the method returns to step 20 and subsequently steps 20, 21, 22 and 23 are repeated as often as until there are no more timing violations.
  • step 24 a so-called layout merge or Engineering Change Order (ECO) carried out.
  • ECO 24 the netlists will be according to the current patchlists modified.
  • step 17 for input timing analysis step 17 back The rest of the process the process is then carried out again as described above. This means that at least steps 17, 18, possibly also Steps 20, 21, 22, 23, 24 are repeated.
  • equivalent SDF file modifications are provided within the scope of the present invention and, if necessary, are provided in step 21: Physical measure
  • Equivalent intervention in SDF file Hold violation insert delay element (s) Pitch or correct hold / setup of target FF Setup violation: Delayed clock, delay element at TI input Patch interconnect from target FF / CP, hold / setup from target FF / TI patch Setup violation: Early clock, delay element at the TI input of the successor flip-flop (FF) Patch interconnect of target FF / CP, hold / setup of successor FF / TI patch Inserting or removing delay elements, buffers, .. Patch IOPATH
  • the required SDF file modifications can also be automated.
  • scripts and tools can be used, both the patch lists as well as make changes to the SDF file automatically.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
EP02019999A 2002-09-05 2002-09-05 Méthode pour développer un composant électronique Withdrawn EP1396801A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02019999A EP1396801A1 (fr) 2002-09-05 2002-09-05 Méthode pour développer un composant électronique
US10/654,604 US20040139410A1 (en) 2002-09-05 2003-09-04 Method for developing an electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02019999A EP1396801A1 (fr) 2002-09-05 2002-09-05 Méthode pour développer un composant électronique

Publications (1)

Publication Number Publication Date
EP1396801A1 true EP1396801A1 (fr) 2004-03-10

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EP02019999A Withdrawn EP1396801A1 (fr) 2002-09-05 2002-09-05 Méthode pour développer un composant électronique

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US (1) US20040139410A1 (fr)
EP (1) EP1396801A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7219317B2 (en) * 2004-04-19 2007-05-15 Lsi Logic Corporation Method and computer program for verifying an incremental change to an integrated circuit design
US7278126B2 (en) * 2004-05-28 2007-10-02 Qualcomm Incorporated Method and apparatus for fixing hold time violations in a circuit design
US7331028B2 (en) * 2004-07-30 2008-02-12 Lsi Logic Corporation Engineering change order scenario manager
US7590957B2 (en) * 2006-08-24 2009-09-15 Lsi Corporation Method and apparatus for fixing best case hold time violations in an integrated circuit design
US7620925B1 (en) * 2006-09-13 2009-11-17 Altera Corporation Method and apparatus for performing post-placement routability optimization
US8234560B1 (en) * 2009-04-17 2012-07-31 Google Inc. Technique for generating a set of inter-related documents
CN106407489B (zh) * 2015-07-31 2019-11-22 展讯通信（上海）有限公司 一种时序约束检查方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953236A (en) * 1995-10-31 1999-09-14 Vlsi Technology, Inc. Method and apparatus for implementing engineering change orders in integrated circuit designs
US6099584A (en) * 1996-12-06 2000-08-08 Vsli Technology, Inc. System to fix post-layout timing and design rules violations
EP1179790A1 (fr) * 2000-08-08 2002-02-13 Stratus Research and Development Limited Conception de circuits electroniques
US20020120910A1 (en) * 2000-12-28 2002-08-29 Olivier Giaume Method for optimization of temporal performances with rapid convergence

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095454A (en) * 1989-05-25 1992-03-10 Gateway Design Automation Corporation Method and apparatus for verifying timing during simulation of digital circuits
US5754826A (en) * 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
US5886900A (en) * 1996-09-25 1999-03-23 Lsi Logic Gorporation Protection of proprietary circuit designs during gate level static timing analysis
US6189131B1 (en) * 1998-01-14 2001-02-13 Lsi Logic Corporation Method of selecting and synthesizing metal interconnect wires in integrated circuits
GB2338573B (en) * 1998-06-15 2002-11-06 Advanced Risc Mach Ltd Modeling integrated circuits
US6668359B1 (en) * 2001-10-31 2003-12-23 Lsi Logic Corporation Verilog to vital translator
US6658628B1 (en) * 2001-12-19 2003-12-02 Lsi Logic Corporation Developement of hardmac technology files (CLF, tech and synlib) for RTL and full gate level netlists
US6934921B1 (en) * 2002-01-04 2005-08-23 Cisco Technology, Inc. Resolving LBIST timing violations
US6938229B2 (en) * 2002-12-04 2005-08-30 Broadcom Corporation Method and apparatus for analyzing post-layout timing violations
US7299433B2 (en) * 2003-06-09 2007-11-20 Intel Corporation Timing analysis apparatus, systems, and methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953236A (en) * 1995-10-31 1999-09-14 Vlsi Technology, Inc. Method and apparatus for implementing engineering change orders in integrated circuit designs
US6099584A (en) * 1996-12-06 2000-08-08 Vsli Technology, Inc. System to fix post-layout timing and design rules violations
EP1179790A1 (fr) * 2000-08-08 2002-02-13 Stratus Research and Development Limited Conception de circuits electroniques
US20020120910A1 (en) * 2000-12-28 2002-08-29 Olivier Giaume Method for optimization of temporal performances with rapid convergence

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