EP1393087A1 - Procede de mesure de la resistance des fusibles dans une matrice de fusibles - Google Patents

Procede de mesure de la resistance des fusibles dans une matrice de fusibles

Info

Publication number
EP1393087A1
EP1393087A1 EP02769186A EP02769186A EP1393087A1 EP 1393087 A1 EP1393087 A1 EP 1393087A1 EP 02769186 A EP02769186 A EP 02769186A EP 02769186 A EP02769186 A EP 02769186A EP 1393087 A1 EP1393087 A1 EP 1393087A1
Authority
EP
European Patent Office
Prior art keywords
fuse
resistance
array
current source
measuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02769186A
Other languages
German (de)
English (en)
Inventor
Elie G. Internationaal Octrooibureau B.V. KHOURY
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP1393087A1 publication Critical patent/EP1393087A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/74—Testing of fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance

Definitions

  • This invention relates to a method for measuring fuse resistance in a fuse array; and particular the salicide poly fuse resistance in a fuse array, without a destructive de- layering process.
  • microprobing wafers or dies to measure a salicide poly fuse requires a de-layering process. This is a destructive process and slow at best. Once the top metal layer is removed and the fuses exposed, they can be measured by microprobes. This is a very tedious and slow process. At best, the resistance of only a few fuses can be measured in an hour. The de-layering and microprobing process is a very expensive procedure requiring a lot of engineering time and can be done only once per die, since it is destructive.
  • a simple electronics method for measuring the pre and post programming fuse resistance in a fuse array is incorporated into the design of the array.
  • Non-destructive measuring the full resistance can be repeated many times, allowing fuse characterization under differing conditions. The process is extremely fast and is performed on the tester. All fuses in an array can be measured, and characterized. Statistical information can be extracted, and process, temperature and other conditions can be attributed.
  • Measuring the fuse resistance in a fuse array is the same process as blowing a fuse, but with a much lower current, for example 100 ⁇ A instead of 20 mA.
  • the measured value or aggregate fuse resistance is the resistance of the wires, and the resistance of the devices used to switch the current.
  • the present invention comprises the step of positioning a fuse array, arranged in rows and columns, in a tester, the tester having an internal write source, means for controlling the write source, and a low current test source.
  • the procedure includes disabling the internal write source, addressing the fuse array to select a fuse, applying the low current source to the fuse and measuring the voltage of this low current source. The resistance of the fuse is thus obtained.
  • a suitable value for the low current source is between 100 ⁇ A and of 500 ⁇ A.
  • Spice simulation data a higher level of accuracy in resistance values is optionally obtained.
  • one fuse can be shorted to provide a datum value for wires and other non-fuse items.
  • Fig. 1 is a diagrammatic illustration of a known write circuit for blowing fuses in an array
  • Fig. 2 is a diagrammatic illustration of a write circuit in accordance with the present invention.
  • Fig. 1 illustrates a circuit for blowing fuses, fuse array on a chip indicated generally at 26.
  • Write current is applied at 10 in a tester, and an address selects one row, 12, and one column, 14.
  • At the intersection of a row and a column is a fuse 16 and an N-MOS switch device 18.
  • the column address 20 selects all the N-MOS switch devices 18 in that column, while the row address 22 selects the P-MOS switch device 24 for a particular row.
  • An electrical path is formed allowing current to flow from the source of the P- MOS switch 22 into the row, into the fuse 16, and then into the drain of the N-MOS switchl ⁇ , to ground.
  • This current, in write mode is large, of the order of 20 mA, and is generated by an internal current source, and is sufficient to blow the fuse, subject to any faults in the fuse.
  • the procedure is optionally repeated for different fuses by selecting different rows and columns. Once tested, then the fuse is blown and thus this testing is typically only a form of quality control, in that it is a destructive process and can therefore only provide an indication of what the fuse resistances are in a production process.
  • Fig. 2 shows a modified circuit, in accordance with the present invention, which allows one fuse to be measured at a time using the write procedure.
  • the P-MOS switch device 22 of Figure 1 is replaced by a pass-gate device 30 - comprising an N-MOS in parallel with a P-MOS device - that has close to zero voltage drop - for example a few millivolts - across its terminals, when the current flowing is small (100 ⁇ A - 500 ⁇ A).
  • An intermediate node FCMV (force current measure voltage), 32, between the internal write current source 10 and the terminal of the pass gate is tapped and routed to an analogue pad 34.
  • FCMV force current measure voltage
  • the write current source Power Down (PDN) signal is gated with a specific signal "Measure-R", at 36, which powers down the write current source only.
  • the chip 24 has a FCMV pin connecting to the FCMV node 32.
  • the tester supplies a low current source at pad 34.
  • write current at 10 is reduced to a small value by the R-measure.
  • a typical measuring procedure is as follows:
  • Raggregate V(fcmv) / I(fcmv) This procedure is optionally repeated for each fuse in the array. In addition to providing an actual resistance value for each fuse 16, the procedure is useful for providing indications of process variations and other possible variables.
  • This procedure provides a non-destructive method of checking fuse arrays.
  • the fuses were blown, only an indication of the quality of the manufacturing process could be obtained.
  • the present invention the actual values of fuses being used can be obtained.
  • the aggregate resistance is the resistance of the wires, Pass-gate switch andN- MOS switch.
  • the voltage drop across the wires, pass-gates and N-MOS switches is very small - a few millivolts.
  • the error introduced by this voltage drop to the fuse resistance measured for a blown fuse is very small (error ⁇ 1%), while it is in the order of 10%, or less, for an unblown fuse measurement.
  • SPICE Using a simulation application, known and referred to as SPICE, can provide a simulated result for a given PNT (process, voltage and temperature) variation, a minimum, typical and maximum voltage drop across the switches.
  • PNT process, voltage and temperature
  • SPICE figures improves the fuse measurement.
  • the final fuse resistance in this case is given by:
  • the present invention enables the actual checking, and measuring, the resistance of a fuse, without destroying it, such fuses afterwards being usable. It is a possibility that the whole process can be automated, being part of a production line, for checking of fuses as a continuous procedure.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé permettant de mesurer la résistance des fusibles dans une matrice de fusibles. Selon le mode de réalisation décrit dans cette invention, les commutateurs P-MOS utilisés pour l'adresse des lignes sont remplacés par un dispositif à grilles passantes qui comprend un N-MOS placé en parallèle avec un P-MOS, avec une chute de tension admissible proche de zéro. Ce mode de réalisation permet d'appliquer un courant source de puissance réduite à travers le fusible. La chute de tension admissible est mesurée et la résistance est obtenue. Ce mode de réalisation permet d'effectuer des essais non-destructeurs par rapport aux essais destructeurs effectuer dans le mode de réalisation de l'état de la technique.
EP02769186A 2001-05-10 2002-05-02 Procede de mesure de la resistance des fusibles dans une matrice de fusibles Withdrawn EP1393087A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US851964 2001-05-10
US09/851,964 US6541983B2 (en) 2001-05-10 2001-05-10 Method for measuring fuse resistance in a fuse array
PCT/IB2002/001526 WO2002091006A1 (fr) 2001-05-10 2002-05-02 Procede de mesure de la resistance des fusibles dans une matrice de fusibles

Publications (1)

Publication Number Publication Date
EP1393087A1 true EP1393087A1 (fr) 2004-03-03

Family

ID=25312157

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02769186A Withdrawn EP1393087A1 (fr) 2001-05-10 2002-05-02 Procede de mesure de la resistance des fusibles dans une matrice de fusibles

Country Status (4)

Country Link
US (1) US6541983B2 (fr)
EP (1) EP1393087A1 (fr)
JP (1) JP2004526164A (fr)
WO (1) WO2002091006A1 (fr)

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JP4545416B2 (ja) * 2003-11-04 2010-09-15 パナソニック株式会社 Ｐｒｏｍ回路
US20050254189A1 (en) * 2004-05-07 2005-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection circuit with low parasitic capacitance
US20090161470A1 (en) * 2007-12-20 2009-06-25 Micron Technology, Inc. Circuit for dynamic readout of fused data in image sensors
JP5636794B2 (ja) * 2010-07-30 2014-12-10 ソニー株式会社 半導体装置及びその駆動方法
KR102133356B1 (ko) * 2014-02-24 2020-07-13 에스케이하이닉스 주식회사 반도체 장치 및 그 동작방법
CN105762137B (zh) 2014-12-15 2020-09-08 联华电子股份有限公司 熔丝结构以及其监控方式
US10598703B2 (en) 2015-07-20 2020-03-24 Eaton Intelligent Power Limited Electric fuse current sensing systems and monitoring methods
US9666305B1 (en) 2015-12-09 2017-05-30 International Business Machines Corporation System for testing charge trap memory cells
CN106997782B (zh) * 2017-03-27 2021-01-29 上海华力微电子有限公司 一种efuse烧写方法及烧写电路
US11289298B2 (en) 2018-05-31 2022-03-29 Eaton Intelligent Power Limited Monitoring systems and methods for estimating thermal-mechanical fatigue in an electrical fuse
US11143718B2 (en) 2018-05-31 2021-10-12 Eaton Intelligent Power Limited Monitoring systems and methods for estimating thermal-mechanical fatigue in an electrical fuse
CN111880009B (zh) * 2020-07-10 2023-05-30 广东电网有限责任公司广州供电局 一种中压熔断器熔体电阻精确测量电路及其测量方法
US11906560B2 (en) * 2021-12-08 2024-02-20 Nanya Technology Corporation System and method of measuring fuse resistance and non-transitory computer readable medium

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US4698589A (en) * 1986-03-21 1987-10-06 Harris Corporation Test circuitry for testing fuse link programmable memory devices
US5210699A (en) * 1989-12-18 1993-05-11 Siemens Components, Inc. Process for extracting logic from transistor and resistor data representations of circuits
US5453696A (en) * 1994-02-01 1995-09-26 Crosspoint Solutions, Inc. Embedded fuse resistance measuring circuit
US5635854A (en) * 1994-05-24 1997-06-03 Philips Electronics North America Corporation Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, validly open or invalid
US5469396A (en) * 1994-06-07 1995-11-21 Actel Corporation Apparatus and method determining the resistance of antifuses in an array
US5731733A (en) * 1995-09-29 1998-03-24 Intel Corporation Static, low current sensing circuit for sensing the state of a fuse device
US5952833A (en) * 1997-03-07 1999-09-14 Micron Technology, Inc. Programmable voltage divider and method for testing the impedance of a programmable element
US6185705B1 (en) * 1997-03-07 2001-02-06 Micron Technology, Inc. Method and apparatus for checking the resistance of programmable elements
US5991220A (en) * 1998-03-09 1999-11-23 Lucent Technologies, Inc. Software programmable write-once fuse memory
JP3307349B2 (ja) * 1998-12-15 2002-07-24 日本電気株式会社 プログラム回路および冗長アドレスデコーダ

Non-Patent Citations (1)

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Title
See references of WO02091006A1 *

Also Published As

Publication number Publication date
US6541983B2 (en) 2003-04-01
WO2002091006A1 (fr) 2002-11-14
US20020167323A1 (en) 2002-11-14
JP2004526164A (ja) 2004-08-26

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