EP1352419A2 - Structure de bosse de contact pour l'etablissement d'une structure de liaison entre des surfaces de connexion d'un substrat - Google Patents

Structure de bosse de contact pour l'etablissement d'une structure de liaison entre des surfaces de connexion d'un substrat

Info

Publication number
EP1352419A2
EP1352419A2 EP01985323A EP01985323A EP1352419A2 EP 1352419 A2 EP1352419 A2 EP 1352419A2 EP 01985323 A EP01985323 A EP 01985323A EP 01985323 A EP01985323 A EP 01985323A EP 1352419 A2 EP1352419 A2 EP 1352419A2
Authority
EP
European Patent Office
Prior art keywords
connection
metallization
spacer
contact
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP01985323A
Other languages
German (de)
English (en)
Inventor
Elke Zakel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pac Tech Packaging Technologies GmbH
Original Assignee
Pac Tech Packaging Technologies GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pac Tech Packaging Technologies GmbH filed Critical Pac Tech Packaging Technologies GmbH
Publication of EP1352419A2 publication Critical patent/EP1352419A2/fr
Ceased legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Definitions

  • Bump structure for establishing a connection structure between substrate connection areas
  • the invention relates to a contact bump structure for forming raised contact points on connection areas of a substrate, in particular chip connection areas, in accordance with the preamble of claims 1 and 10, and a connection structure between connection areas of substrates contacted with one another using the contact bump structure in accordance with claims 4 and 18.
  • a direct contacting method has become established in which increased contact metallizations , which are referred to in technical terms as "bumps", are used to connect mutually opposite connection surfaces to be contacted substrates.
  • the connection surface density increases, there are increased requirements for tolerance compensation, which on the one hand deviates from the position of the connection surfaces assigned to one another of the substrates and, on the other hand, height differences of the bumps forming contact bumps, in order to largely prevent incorrect contacting or mechanical stresses in the components which impair the operational safety of the electronic components.
  • the present invention is therefore based on the object of proposing a contact bump structure which enables tolerance compensation in the case of height differences of the bumps or positional deviations of the contact surfaces to be contacted.
  • the contact bump structure according to the invention has a spacing metallization provided on the connection surfaces of the substrate in order to achieve a defined height of the contact bump structure, which at least partially consists of annealed copper.
  • a contact bump structure which has a metallic structure made of copper, the copper structure having a so-called recrystallization structure with a relatively coarse structure due to the tempering, that is to say a heat treatment, which overall gives the contact bump structure to be flexible enabled under pressure. It is therefore possible that even a large number of bumps, which are arranged distributed on a contact side of a substrate and have different heights in the original state within the scope of a height tolerance that cannot be avoided in terms of production technology, due to the contact pressure when contacting another substrate uniform dimensions are compressed. This can largely rule out the possibility of incorrect contact points due to differing contact heights of individual bumps or component tension due to contact can occur.
  • an intermediate metallization can be provided for the indirect connection of the spacer metallization to the connection surface. This proves to be particularly advantageous if, in contrast to the spacer metallization, the intermediate metallization does not consist of copper, but instead of aluminum, for example.
  • the use of a Ni-Au layer layer structure on the pad metallization or the arrangement of a Ni / Au alloy on the pad metallization has proven to be advantageous for the intermediate metallization.
  • a coating which acts as an oxidation barrier.
  • a coating can be, for example, a Ni / Au, Sn or an Sn / Pb alloy.
  • connection structure between connection areas of substrates that have been contacted with one another using the contact bump structure according to the invention has a spacing metallization which is arranged on a connection area of a first substrate and which at least partially consists of annealed copper.
  • Known thermocompression processes or adhesive techniques with, in particular, non-conductive adhesive can be used to produce the connection structure; techniques that do not necessarily require the use of an additional connecting compound.
  • the connecting compound which is used to produce a cohesive, electrically conductive connection between the spacing metallization arranged on the connection surface of the first substrate and the assigned connection surface of the second substrate, consists of an anisotropic adhesive material.
  • the combination of the anisotropic adhesive material as the bonding compound with the spacer metallization made of annealed copper enables - particularly because of the relatively good plastic deformability of the tempered copper - the particular advantage of contacting the two substrates without significant exposure to temperature and thus without influencing the structural structure of the spacer metallization.
  • the desired equalization of the heights of the spacer metallizations occurs in a plurality of bumps arranged in a common contact plane simultaneously with the pressurization of the adhesive material necessary for producing a conductive contact.
  • connection structure according to the invention also enables the use of a solder material as a connecting compound.
  • connection structure when an oxidation barrier is arranged on the spacer metallization and / or an intermediate metallization is arranged for indirect use Connection of the spacer metallization with the connection area has corresponding advantages.
  • a recrystallization of the deposited copper by application of heat is carried out in a process step following the deposition process a temperature above the temperature during the deposition process.
  • the copper With the subsequent heat treatment of the copper which has previously been electrolessly deposited at a temperature of approximately 60 ° C., the copper is preferably transformed at a temperature> 100 ° C.
  • This structural transformation from a structure that is rather amorphous as a result of the deposition process to a comparatively roughly structured, crystalline structure leads to a reduction in hardness of the copper structure, with the result that the plastic deformability of the copper is increased.
  • a bump structure for forming raised contact points on connection surfaces of a substrate which has a spacer made of a dielectric, the at least partially electrically conductive surface of which is connected via an electrical conductor to the associated connection surface of the substrate is connected, wherein the conductor is at least partially designed as a surface conductor arranged on the surface of the spacer.
  • the inventive combination of non-conductive spacer and surface conductor for electrically conductive contacting the surface of the spacer with the connection surface of the substrate enables a redistribution and / or enlargement of the connection areas in the simplest way without the previously usual multi-layer structure on the contact side of a substrate.
  • the spacer body is arranged in a covering position with the associated connection surface, it is possible to form an electrically conductive contact surface of the spacer body with an electrically conductive connection to the connection surface of the substrate by partially forming the conductor as a via, which extends through a through hole in the spacer body.
  • the spacer body can also be arranged with the intermediate layer of the conductor on the connection surface, and the conductor can extend around at least a partial circumference of the spacer body up to the upper side of the spacer body.
  • the conductor extending from a second partial surface of the connection surface onto the surface of the spacer body is a reconnection, ie a redistribution the effective connection surfaces, particularly easy to implement.
  • connection area In order to achieve a permanently electrically reliable connection between the connection area and the electrically conductive upper side of the non-conductive spacer, it proves to be advantageous if the conductor at least in the areas outside the connection area has an adhesion promoter layer as a carrier for a contact metallization of the conductor.
  • Such an adhesion promoter layer can be formed, for example, by germinating with palladium on the corresponding surface areas of the electrically non-conductive surface, that is to say, for example, the passivation of a chip, so that on the one hand, due to the low selectivity of palladium, deposition on non-metallic surfaces is possible, and on the other hand deposited palladium particles can serve as seeds for a subsequent metal deposition of, for example, copper or a Cu / Ni alloy.
  • connection surface can be provided with a contact metallization containing Ni and Au.
  • a connection structure produced using the contact bump structure according to the invention between connection surfaces of substrates contacted with one another has, according to the invention, a spacer body arranged on a connection surface of a first substrate for achieving a defined height of the connection structure and a connection mass arranged between the spacer body and an assigned connection surface of a second substrate, wherein the spacer consists of a dielectric, the at least partially electrically conductive surface of which is connected to the connection surface of the first substrate via an electrical conductor.
  • connection structure according to the invention not only enables compensation of pitch errors in a connection between two substrates, but also a relative enlargement of the connection areas and / or a redistribution of the connection areas.
  • the enlargement of the connection surfaces made possible enables a preferred use of an anisotropic adhesive material as a connecting compound.
  • FIG. 1 shows a bump structure in a first embodiment with intermediate metallization.
  • FIG. 3 shows a connection structure between two substrates using the contact bump structure shown in FIG. 2;
  • connection setup 4 shows an enlarged individual illustration of a connection setup
  • FIG. 6 shows the pad area shown in FIG. 4 with a dielectric layer
  • FIG. 7 shows the pad area shown in FIG. 5 with a spacer formed from a dielectric
  • FIG. 8 shows the pad area shown in FIG. 6 with a further embodiment of a bump structure; 9 shows a further embodiment of a contact bump structure with a spacer;
  • FIG. 10 shows a connection structure between two substrates produced using a further embodiment of a contact bump structure with a spacer body
  • FIG. 11 shows a corner region of a substrate provided with a plurality of bump structures corresponding to FIG. 8;
  • FIG. 12 shows a corner area of a substrate provided with a plurality of contact bump structures corresponding to FIG. 9.
  • FIG. 1 shows a pad area 20 of a substrate 21 with a pad 22 formed in the present case from aluminum, which is provided with a two-layer intermediate metallization 23 made of a nickel layer 24 and a gold layer 25.
  • the substrate 21, for example a chip is provided with a so-called passivation 26.
  • the intermediate metallization 23 is provided with a spacer metallization 28 made of copper in order to form a bump structure 27 on the connection area 22.
  • the spacer metallization 28 is provided with a coating 29 to prevent surface oxidation, which can be formed, for example, from gold, a nickel / gold alloy, tin or a tin / lead alloy.
  • the coating 29 can in particular be used to compensate for micro-roughness on the surface of the spacer metallization 28.
  • the spacer metallization 28 made of copper has a relatively coarse, crystalline structure, which is the result of a the arrangement of the spacer metallization 28 on the intermediate metallization 23 subsequent heat treatment.
  • electroless deposition of nickel and gold is subsequently deposited on the connection surface 22 to form the intermediate metallization 23, and electroless copper is deposited on the intermediate metallization 23.
  • Nickel and gold are deposited, for example, until layer thicknesses of 5 to 20 micrometers and 0.1 to 0.5 micrometers are achieved.
  • the chemical deposition process of the copper takes place at a temperature below 100 ° C, for example at about 60 ° C.
  • the result of the currentless deposition process is a copper layer with an almost amorphous structure.
  • Subsequent heat treatment at a temperature> 100 ° C induces recrystallization of the copper structure with a comparatively coarse, crystalline structure which has a marked reduction in hardness compared to the starting structure.
  • connection bump structure 33 formed on a connection area 31 of a substrate 32, in which the spacer metallization 28 is applied directly, that is to say without an intermediate metallization 23, to the connection area 31 made of copper by electroless deposition.
  • FIG. 3 shows a connection structure 34 between two substrates 32 and 35 using bump structures 33, as shown in FIG. 2.
  • the substrate 35 provided with connection areas 36 is first provided, and the connection areas 36 are provided with a connecting compound made of anisotropic adhesive 37.
  • the contacting of the substrate 32 provided with contact bump assemblies 33 takes place in so-called “flip-chip technology”, in which the substrate 32 is brought into contact with the contact bump assemblies 33 directed against the connection surfaces 36 of the substrate 35 and pressed under a defined connection pressure becomes.
  • the spacer metallizations 28 of the bump structures 33 are plastically deformed such that the bump structures 33 having different heights hi to h in the unloaded initial state (dashed lines) are deformed until a uniform height H of the bump structures 33 is formed.
  • the plastic deformation of the spacer metallizations 28 during the flip-chip contacting also enables the surface contour of the spacer metallizations 28 to be adapted to the surface contour of the connection surfaces 36, as shown by way of example in FIG. 4.
  • the large-area surface contact made possible in this way proves to be particularly advantageous in connection with connection technologies in which no connecting compound is used between the contact partners, which compensates for deviations in the surface contours of the contact partners, such as in the thermocompression process or a connection with non-conductive adhesive, in which the adhesive essentially is arranged in the periphery of the connection setup.
  • connection area region 39 shows the connection area region 39 with a connection area 41 and, with the exception of the connection area 41, a surface of the substrate 40 covered by a passivation 42.
  • the connection area 41 consists of aluminum and, with an intermediate metallization 23, comprises a nickel layer 24 and a gold layer 25 provided.
  • the entire pad area 39 is with a Surface conductive layer 43 is covered as a surface conductor, which in the present case has a copper / nickel alloy as contact metallization on a layer support preferably containing palladium. If desired, the desired adhesion between the contact metallization of the surface conductive layer 43 and a non-metallic substrate, that is to say the passivation 42, can be achieved by means of the layer support.
  • FIG. 6 shows the arrangement of an electrically non-conductive thick film 44 made of a dielectric on the pad area 39 and a photomask 45 arranged on the thick film 44, which enables structuring of a spacer 46 from the thick film 44 in the etching process or the like.
  • an etching method for structuring the spacer 46 can be used at the same time for removing the surface conductive layer 43 in the area surrounding the spacer 46.
  • connection surfaces are made of aluminum, so that an intermediate metallization of the type described above is expedient for further contacting of the connection surfaces. If the connection surfaces are made of copper, contacting without intermediate metallization is of course also possible.
  • FIG. 9 shows in a further embodiment a bump structure 48 with a spacer body 49, which is arranged in a cover position with a connection surface 50 of a substrate 51 and with a Through hole 52 is provided.
  • the spacer body 49 is provided both on its underside 53 and on its upper side 54 with a surface conductive layer 43, which enables an electrically conductive connection from the upper side 54 via a perforated wall 55 of the through hole 52 to the underside 53 and via the intermediate metallization 23 to the connecting surface 50 ,
  • connection structure 56 between two substrates 57 and 58 using a further embodiment of a contact bump structure 59.
  • the contact bump structure 59 comprises a spacer body 60, which is in contact with a left partial region 61 in a covering position with a partial surface 79 a connection surface 62 of the substrate 57 is located.
  • the connection surface 62 consists of aluminum and is provided with an intermediate metallization 23 comprising a nickel layer 24 and a gold layer 25.
  • An anisotropic adhesive 67 is provided as the connecting compound for contacting the upper side 63 of the spacer body 60 provided with the surface conductive layer 65 and a connection surface 66. It is clear from the illustration of the connection structure 56 between the substrates 57 and 58 that by means of the contact bump structure 59 comprising the spacer body 60, a redistribution or rewiring of the contact surface structure of the substrate 57 to adapt to the contact surface structure or contact surface distribution of the substrate 58 is possible.
  • the contact bump assemblies 73, 74, 75 can be designed, for example, in the manner of the contact bump assembly 38 shown in FIG. 8.
  • contact tops 76, 77, 78 of different surface shapes with a matching surface size.
  • Such enlarged contact areas not only make it possible to reconnect or adapt to a contact area distribution of a counter substrate, not shown in FIG. 10, but also to compensate for tolerance-related deviations in the contact area distribution between substrate and counter substrate due to the enlarged contact areas.
  • the enlarged contact areas of the contact upper sides 76, 77, 78 form a particularly secure basis for connection structures between substrates which are in contact with the adhesive.
  • FIG. 12 shows a top view of a corner region of a substrate 81, the connection surfaces 82 of which, in contrast to the substrate 68 shown in FIG. 11, are provided with bump assemblies 83, 84 in the manner of the bump assembly 48 shown in FIG. 9.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

L'invention concerne une structure de bosse de contact (27) et un procédé de production d'une structure de bosse de contact pour la formation de points de contact surélevés sur des surfaces de connexion (22) d'un substrat (21), en particulier des surfaces de connexion d'une puce. Cette structure de bosse de contact renferme une métallisation d'écartement (28) permettant d'atteindre une hauteur de structure de bosse de contact définie, ladite métallisation d'écartement (28) contenant au moins une proportion de cuivre trempé.
EP01985323A 2000-12-20 2001-12-19 Structure de bosse de contact pour l'etablissement d'une structure de liaison entre des surfaces de connexion d'un substrat Ceased EP1352419A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10063914A DE10063914A1 (de) 2000-12-20 2000-12-20 Kontakthöckeraufbau zur Herstellung eines Verbindungsaufbaus zwischen Substratanschlussflächen
DE10063914 2000-12-20
PCT/DE2001/004774 WO2002050889A2 (fr) 2000-12-20 2001-12-19 Structure de bosse de contact pour l'etablissement d'une structure de liaison entre des surfaces de connexion d'un substrat

Publications (1)

Publication Number Publication Date
EP1352419A2 true EP1352419A2 (fr) 2003-10-15

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EP01985323A Ceased EP1352419A2 (fr) 2000-12-20 2001-12-19 Structure de bosse de contact pour l'etablissement d'une structure de liaison entre des surfaces de connexion d'un substrat

Country Status (5)

Country Link
US (1) US7007834B2 (fr)
EP (1) EP1352419A2 (fr)
AU (1) AU2002234489A1 (fr)
DE (1) DE10063914A1 (fr)
WO (1) WO2002050889A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10063914A1 (de) 2000-12-20 2002-07-25 Pac Tech Gmbh Kontakthöckeraufbau zur Herstellung eines Verbindungsaufbaus zwischen Substratanschlussflächen
JP2005216606A (ja) * 2004-01-28 2005-08-11 Hitachi Ltd 平面型表示装置
JP4219951B2 (ja) * 2006-10-25 2009-02-04 新光電気工業株式会社 はんだボール搭載方法及びはんだボール搭載基板の製造方法
US7713860B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump on I/O pad
DE102009016594A1 (de) * 2009-04-08 2010-10-14 Pac Tech-Packaging Technologies Gmbh Kontaktanordnung zur Substratkontaktierung
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0180101A2 (fr) * 1984-11-01 1986-05-07 International Business Machines Corporation Dépôt d'une configuration en utilisant l'ablation par laser
EP0295914A2 (fr) * 1987-06-19 1988-12-21 Hewlett-Packard Company Structure d'interconnexion pour plaques à circuits imprimés et circuits intégrés
EP0827190A2 (fr) * 1994-06-24 1998-03-04 Industrial Technology Research Institute Structure de plot de contact et méthodes pour sa fabrication

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4188438A (en) * 1975-06-02 1980-02-12 National Semiconductor Corporation Antioxidant coating of copper parts for thermal compression gang bonding of semiconductive devices
JPS6112047A (ja) 1984-06-28 1986-01-20 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4740700A (en) * 1986-09-02 1988-04-26 Hughes Aircraft Company Thermally insulative and electrically conductive interconnect and process for making same
JPS647542A (en) * 1987-06-30 1989-01-11 Toshiba Corp Formation of bump
EP0308971B1 (fr) * 1987-09-24 1993-11-24 Kabushiki Kaisha Toshiba Soudure et procédé pour sa réalisation
JP2833326B2 (ja) * 1992-03-03 1998-12-09 松下電器産業株式会社 電子部品実装接続体およびその製造方法
JPH05251455A (ja) * 1992-03-04 1993-09-28 Toshiba Corp 半導体装置
JP3141364B2 (ja) * 1992-05-06 2001-03-05 住友電気工業株式会社 半導体チップ
JP3152834B2 (ja) * 1993-06-24 2001-04-03 株式会社東芝 電子回路装置
US6132887A (en) * 1995-06-16 2000-10-17 Gould Electronics Inc. High fatigue ductility electrodeposited copper foil
US5578527A (en) * 1995-06-23 1996-11-26 Industrial Technology Research Institute Connection construction and method of manufacturing the same
US6007349A (en) * 1996-01-04 1999-12-28 Tessera, Inc. Flexible contact post and post socket and associated methods therefor
US5868304A (en) * 1996-07-02 1999-02-09 International Business Machines Corporation Socketable bump grid array shaped-solder on copper spheres
JPH10125725A (ja) * 1996-10-18 1998-05-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6070321A (en) * 1997-07-09 2000-06-06 International Business Machines Corporation Solder disc connection
US6028011A (en) * 1997-10-13 2000-02-22 Matsushita Electric Industrial Co., Ltd. Method of forming electric pad of semiconductor device and method of forming solder bump
US6248429B1 (en) * 1998-07-06 2001-06-19 Micron Technology, Inc. Metallized recess in a substrate
US6268660B1 (en) * 1999-03-05 2001-07-31 International Business Machines Corporation Silicon packaging with through wafer interconnects
JP2003152023A (ja) * 1999-03-23 2003-05-23 Citizen Watch Co Ltd 半導体装置の接続構造とその製造方法
JPH11330165A (ja) * 1999-03-29 1999-11-30 Seiko Epson Corp 電気素子の接続構造及び液晶パネル
US6103624A (en) * 1999-04-15 2000-08-15 Advanced Micro Devices, Inc. Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish
WO2000079589A1 (fr) * 1999-06-17 2000-12-28 Infineon Technologies Ag Composant electronique a structures de contact souples et procede de fabrication d'un tel composant
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
DE10063914A1 (de) 2000-12-20 2002-07-25 Pac Tech Gmbh Kontakthöckeraufbau zur Herstellung eines Verbindungsaufbaus zwischen Substratanschlussflächen
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0180101A2 (fr) * 1984-11-01 1986-05-07 International Business Machines Corporation Dépôt d'une configuration en utilisant l'ablation par laser
EP0295914A2 (fr) * 1987-06-19 1988-12-21 Hewlett-Packard Company Structure d'interconnexion pour plaques à circuits imprimés et circuits intégrés
EP0827190A2 (fr) * 1994-06-24 1998-03-04 Industrial Technology Research Institute Structure de plot de contact et méthodes pour sa fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0250889A2 *

Also Published As

Publication number Publication date
AU2002234489A1 (en) 2002-07-01
DE10063914A1 (de) 2002-07-25
WO2002050889A3 (fr) 2003-04-24
WO2002050889A2 (fr) 2002-06-27
US7007834B2 (en) 2006-03-07
US20040051116A1 (en) 2004-03-18

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