Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current
  • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current
  • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

• the present invention relates to the field of voltage regulators and in particular that of regulators with low waste voltage.
• a low drop out regulator in the form of an integrated circuit can be used to supply a predetermined potential with low noise to a set of electronic circuits from a supply potential supplied by a rechargeable battery. .
• a supply potential decreases over time and is likely to include noise caused by the action of neighboring electromagnetic radiation on the battery / regulator links.
• the regulator is said to have a low waste voltage because it provides a potential close to the supply potential.
• Figure 1 shows schematically an example of a conventional low-voltage waste regulator.
• the regulator has an output terminal S intended to be connected to a load R.
• the essentially resistive load R represents the sum of the input impedances of the circuits supplied by the regulator. For simplicity, it is subsequently considered that the load R is a resistance.
• the regulator comprises an operational amplifier 4 of which a non-inverting input IN + is connected to a positive reference potential Vref and of which an inverting input IN ⁇ is connected to the terminal S by a feedback loop.
• the potential Vref is produced in a known manner by a constant voltage source (not shown) with high output impedance.
• the operational amplifier 4 is supplied between a positive supply potential Vbat supplied by the battery and a ground potential GND.
• An inverter stage 6, supplied between the potentials Vbat and GND, receives the output of the operational amplifier 4 and its output is connected to the gate of a power MOS transistor T1, with P channel, the drain of which is connected to the output terminal S and whose source is connected to the potential Vbat.
• the transistor T1 is of the MOS type rather than bipolar in particular to minimize the difference between the output potential Vout of the terminal S and the supply potential Vbat.
• a charge capacitor C is disposed between the output terminal S and the potential GND.
• FIG. 2 schematically represents an exemplary embodiment of the operational amplifier 4 of FIG. 1.
• Two MOS transistors T2, T3, with P channel, have their • sources connected to each other and their gates respectively connected to the inputs IN ⁇ and IN +.
• a bias current source CS1 is arranged between the potential Vbat and the sources of the transistors T2 and T3.
• the transistors T2 and T3 form a differential pair.
• Two N-channel MOS transistors T4 and T5 have their sources connected to the GND potential and their gates connected to each other.
• the drains of the transistors T4 and T5 are respectively connected to the drains of the transistors T2 and T3.
• the drain of transistor T3 is connected to the gates of transistors T4 and T5.
• the transistors T4 and T5 form an active charge of the differential pair formed by the transistors T2 and T3.
• the drain of transistor T2 constitutes the output of amplifier 4.
• the voltage regulator of FIG. 1 maintains the potential Vout of the output terminal S at a value equal to the reference potential Vref. Any variation in the potential Vbat results in a variation in the potential Vout, which is transmitted by the feedback loop on the input IN " . When the regulator functions correctly, the variation of the potential of the input IN " causes the potential Vout to return to the potential Vref.
• the regulator circuit which forms a looped system between the input IN " and the terminal S must be a stable system. For the system to be stable when it is looped, its gain in open loop must not be greater to 1 when the phase shift is less than -180 ° (when there is phase opposition between the input and the output of the system).
• Figure 3 illustrates, according to the frequency f, the variation of the gain G and the phase shift ⁇ of the open loop regulator taken between input IN " and terminal S.
• the gain G is equal to the static gain Gs of the regulator in open loop.
• the elements that make up the regulator each have a gain which varies according to the frequency.
• the cut-off frequency of an element whose gain decreases when the frequency increases constitutes a "pole" of the transfer function of the regulator in open loop.
• Each pole of the transfer function of the open loop regulator introduces a fall of 20 dB per decade of gain G.
• each pole of the transfer function of the open loop regulator introduces a phase shift ⁇ of 90 °.
• the transfer function of the open loop regulator comprises only a main pole PO and a secondary pole PI.
• the frequency at which the main pole PO is located depends in particular on the inverse of the product of the values of the load resistance R and the capacitor C.
• the frequency at which the secondary pole PI is located depends in particular on the impedance of the grid of the transistor T1.
• the inverting stage 6 is an ideal stage which does not introduce any pole.
• the characteristics of the elements that make up the regulator are chosen so that, when the phase shift ⁇ becomes equal to -180 °, the gain G is less than the unit gain (0 dB).
• the PO pole is located at a low frequency and the PI pole is located at a frequency higher than the frequency of the PO pole.
• the gain is equal to the static gain Gs of the open loop regulator. Between the PO and PI poles, the gain drops by 20 decibels per decade. Beyond the PI pole, the gain drops by 40 decibels per decade. The phase shift drops from 0 to -90 ° at the PO pole and from -90 ° to - 180 ° at the PI pole.
• the static gain Gs of the regulator is equal to Gs4.Gs6.Gsl, where Gs4 is the static gain of the operational amplifier 4, Gs6 is the static gain of the inverter stage 6, and Gsl is the static gain of the transistor Tl.
• the static gain of the operational amplifier 4 is of the form:
• GS4 Grr-2.
• (R2.R4) / (R2 + R4) ( ⁇ 2. Zout where .3 ⁇ 2 is the transconductance of the transistor T2, and R2, R4 are the conduction resistors, called “Early" resistors, of the transistors T2 and T4
• the ratio (R2.R4) / (R2 + R4) constitutes the output impedance Zout of the operational amplifier.
• the "Early" resistances of the transistors T2 and T4 are high, and the output impedance Zout as well as the static gain Gs4 of the amplifier 4 have a high value.
• a strong Gs4 gain makes the static Gs gain high, which shifts the gain curve upwards and makes the stability of the regulator difficult to obtain.
• FIG. 3 illustrates a gain curve G 'of an open loop regulator having the two poles PO, PI above and having a static gain Gs' greater than the previous static gain Gs.
• the gain G ' is greater than 1 (0 dB) when the phase shift ⁇ reaches the value of -180 °, which makes the regulator unstable.
• a conventional way of solving this problem is to increase the capacitance of the capacitor C, which reduces the frequency at which the main pole PO is located.
• the use of a large capacitor C is not desirable.
• An object of the present invention is to provide a stable voltage regulator with a large passband while using a low value output capacitor. To achieve this object, the present invention provides for reducing the apparent output resistance of the operational amplifier of a regulator.
• the present invention provides a voltage regulator having an output terminal suitable for being connected to a load, comprising an operational amplifier whose non-inverting input is connected to a first reference potential, and whose inverting input is connected at the output terminal, an inverter stage the input of which is connected to the output of the operational amplifier, a power switch controlled by the output of the inverter stage, disposed between the output terminal and a supply potential , and a charge capacitor disposed between the output terminal and a supply reference potential, comprising means for reducing the effective output impedance of the operational amplifier.
• the means of reduction of -pumpedance comprises a first resistor, a first terminal of which is connected to the output of the operational amplifier, a MOS transistor connected as a diode, the drain of which is connected to a second terminal of the first resistor and whose source is connected to the second reference potential, and means for biasing the transistor connected as a diode in the on state.
• the first resistance has a value much lower than the output impedance of the operational amplifier.
• the operational amplifier comprises first and second MOS transistors, of a first type, the sources of which are connected to each other, and the gates of which are respectively connected to the inputs inverting and non-inverting, a current source disposed between the supply potential and the sources of the first and second transistors, of the third and fourth MOS transistors, of a second type, the sources of which are connected to the first reference potential, of which the gates are connected to each other, and the drains of which are respectively connected to the drains of the first and second transistors, the drain of the first transistor being connected to the output of the operational amplifier and the drain and the gate of the fourth transistor being connected to each other.
• the inverter stage comprises a fifth MOS transistor, of the type of the third and fourth transistors, the gate and the drain of which are respectively connected to the input and to the output of the inverter stage , and the source of which is connected to the first reference potential, an impedance arranged between the output of the inverter stage and the supply potential, and a capacitor and a second resistor arranged in series between the input and the output of 1 'reverse stage.
• the power switch is a sixth MOS transistor of the type of the first and second transistors.
• the first, second and sixth transistors are P-channel MOS
• the third, fourth and fifth transistors are N-channel MOS
• FIG. 4 schematically represents an embodiment of a regulator according to the present invention
• FIG. 5 schematically represents an embodiment of an inverter usable according to the present invention. Only the elements allowing the understanding of the present invention have been represented in the various figures. The same references represent the same elements in the different figures.
• FIG. 4 schematically represents an embodiment of a regulator.
• the regulator comprises the elements already described of a conventional regulator and a circuit 7 for reducing the output impedance connected to the output of the operational amplifier 4.
• a resistor RI has a first terminal connected to the output of the operational amplifier 4.
• An MOS transistor 8 with N channel, has its drain connected to a second terminal of the resistor RI and its source connected to the potential GND. The drain and the gate of transistor 8 are connected to each other so that transistor 8 is connected as a diode.
• a current source CS2 for biasing the transistor 8 connected as a diode is connected between the potential Vbat and the drain of the transistor 8.
• the current source CS2 is chosen so that the transistor 8 connected as a diode conducts permanently.
• the transistor 8 is chosen so that the voltage drop between its drain and its source is equal to the voltage existing between the input of the inverter stage 6 and the ground potential GND. It follows that the voltage drop across the resistor RI is substantially zero, and that the operation of the operational amplifier 4 is not unbalanced by a current flowing through the resistor RI.
• the impedance Z of the transistor 8 connected in diode and of the resistance RI connected in series is equal to: where G m 8 is the transconductance of the transistor 8.
• the resistance RI and the transistor 8 are chosen so that the impedance Z is much less than the output impedance Zout of the operational amplifier.
• the static gain Gs4 of the operational amplifier 4 whose output OUT is connected in parallel on the impedance Z is equal to Gs4 ***** G ⁇ . (Zout .Z) / (Zout + Z), i.e. substantially G ⁇ . .
• the present invention makes it possible to reduce the static gain introduced by the operational amplifier 4, and thereby the static gain of the open loop voltage regulator.
• the reduction in the apparent output impedance of the operational amplifier 4 corresponds to a reduction in the gain of this amplifier.
• the present invention has been described in relation to an ideal inverter stage 6 which does not introduce any pole in the transfer function of the open loop voltage regulator.
• the inverter stage 6 is not an ideal amplifier stage, but is, for example, a so-called "Miller" amplifier stage.
• the function of such an amplifier stage is notably to increase the frequency at which the secondary pole PI is located in order to increase the bandwidth of the open loop voltage regulator.
• a Miller stage notably introduces a pole P2 and a zero Zl into the transfer function of the open loop voltage regulator.
• FIG. 5 schematically represents an embodiment of a voltage regulator according to the present invention, in which the inverter stage 6 of the amplification circuit 2 'is a Miller stage.
• the inverter stage 6 comprises a transistor T7, with an N channel, the gate and the drain of which are respectively connected to the input and to the output of the stage 6.
• the source of the transistor T7 is connected to the potential GND.
• An impedance 10 is disposed between the output of stage 6 and the potential Vbat.
• a capacitor C1 and a resistor R2 are arranged in series between the input and the output of the amplifier stage. The value of the capacitor Cl, of the resistor R2, and the gain of the transistor T7 make it possible in particular to adjust the frequencies at which the poles PI, P2 are located.
• the voltage drop across the terminals of the transistor 8 connected as a diode is in this case chosen to be equal to the gate / source voltage of the transistor T7.
• the reduction in the output impedance connected at the input of the inverter stage 6 also has the effect of increasing the frequency at which the pole P2 introduced by stage 6 is situated, which represents an additional advantage of the present invention. .
• the present invention is susceptible of various variants and modifications which will appear to one skilled in the art.
• the present invention has been described in relation to a particular operational amplifier, but a person skilled in the art will easily adapt the present invention to a voltage regulator using other types of operational amplifiers.
• the present invention has been described in relation to a voltage regulator using a power transistor T1, but a person skilled in the art will easily adapt the present invention to a voltage regulator using another type of voltage-controlled power switch.
• the present invention has been described in relation to positive Vbat and Vref potentials, but those skilled in the art will easily adapt the present invention to negative Vbat and Vref potentials, by reversing the types of transistors. tors MOS described and the connection of the transistor 8 connected in diode.
• the present invention has for reasons of simplicity been described in relation to a voltage regulator using a non-resistive feedback loop and supplying a voltage equal to a reference voltage Vref received.
• a person skilled in the art will easily adapt the present invention to a voltage regulator, the feedback loop of which comprises a resistive bridge, and which supplies an output voltage different from the voltage Vref received.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• General Physics & Mathematics (AREA)
• Radar, Positioning & Navigation (AREA)
• Automation & Control Theory (AREA)
• Continuous-Control Power Sources That Use Transistors (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=8858157

Family Applications (1)

Country Status (4)

Families Citing this family (8)

Family Cites Families (8)

• 2000
  • 2000-12-22 FR FR0016978A patent/FR2818762B1/fr not_active Expired - Fee Related
• 2001
  • 2001-12-21 EP EP01995774A patent/EP1352302A1/de not_active Withdrawn
  • 2001-12-21 US US10/451,593 patent/US6933708B2/en not_active Expired - Lifetime
  • 2001-12-21 WO PCT/FR2001/004174 patent/WO2002052364A1/fr active Application Filing

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events