EP1349313B1 - Appareil et procédé de réception de données sur un canal de commande en mode paquet dans un système de communication mobile - Google Patents

Appareil et procédé de réception de données sur un canal de commande en mode paquet dans un système de communication mobile Download PDF

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Publication number
EP1349313B1
EP1349313B1 EP03006823A EP03006823A EP1349313B1 EP 1349313 B1 EP1349313 B1 EP 1349313B1 EP 03006823 A EP03006823 A EP 03006823A EP 03006823 A EP03006823 A EP 03006823A EP 1349313 B1 EP1349313 B1 EP 1349313B1
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EP
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Prior art keywords
symbols
slots
slot
decoder
decoding
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Expired - Fee Related
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EP03006823A
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German (de)
English (en)
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EP1349313A1 (fr
Inventor
Se-Hyoung c/o Samsung Electronics Co. Ltd. Kim
Woo-Sang c/o Samsung Electronics Co. Ltd. Hong
Ji-Won c/o Samsung Electronics Co. Ltd. Ha
Sang-Min c/o Samsung Electronics Co. Ltd. Bae
Jin-Woo c/o Samsung Electronics Co. Ltd. Heo
Soo-Bok c/o Samsung Electronics Co. Ltd. Yeo
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0046—Code rate detection or code type detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]

Definitions

  • the present invention relates to an apparatus and method for a mobile communication system supporting a multimedia service including voice and packet data services, and in particular, to an apparatus and method for effectively receiving a control channel that transmits control information related to transmission of packet data.
  • a conventional mobile communication system for example, an Interim Standard-2000 (IS-2000), Code Division Multiple Access (CDMA) mobile communication system, chiefly supports a voice service and a low-speed circuit and packet data service.
  • IS-2000 Interim Standard-2000
  • CDMA Code Division Multiple Access
  • a mobile communication system supporting a high-speed packet data service With the development of a communication technology and at the request of users, research has been conducted on a mobile communication system supporting a high-speed packet data service.
  • an IS-2000 Evolution in Data and Voice (1xEVDV) mobile communication system has recently attracted public attention, supports not only a voice service but also a high-speed packet data service.
  • a receiver capable of handling high-speed packet data is required.
  • a transmitter transmits various control information for the packet data channel over a packet data control channel (PDCCH) for the same time period.
  • the control information includes destination address, data rate, modulation scheme and code rate of transmission data, and is used for reception of a packet data channel.
  • a packet data channel and a packet data control channel both support a plurality of data rates.
  • the data rates are related to a period, or the number of time slots, required for transmitting data having a predetermined length. For example, a length of control information transmitted over a packet data control channel is fixed to 13 bits, and the control information is transmitted over 1, 2 or 4 time slots each having a predetermined length.
  • a data rate of a packet data channel can be determined by a data rate of a packet data control channel
  • a transmitter does not separately inform a receiver of a data rate of the packet data control channel. The receiver detects a data rate of received data from the received data, and acquires control information according to the detected data rate.
  • Document WO 99/14885 discloses transmitting time slots and repetition of the time slots from the base station to the mobile station; selectively receiving the time slots, detecting soft information from each of the time slots, and providing combination of the soft information to a channel decoder.
  • the document uses soft information led from the received whole slot or partial 2-time slot and stored soft information. It discloses selectively using the soft information depending on whether the reception of 1-time slot is in error or not. It is disclosed that the repeated slot may not be received or processed, if the CRC check of a first-transmitted slot is passed, indicating no error.
  • the document teaches respectively decoding slots case by case.
  • an object of the present invention to provide an apparatus according to claim 1 and a method according to claim 14 for effectively receiving a control channel in a mobile communication system that simultaneously transmits a channel for transmitting packet data and the control channel for transmitting control information of the packet data.
  • CRC cyclic redundancy code
  • an apparatus for receiving control information transmitted from a transmitter using one of a plurality of slot lengths in a high-speed packet transmission mobile communication system comprises a decoder adapted to receive symbols by the slot, and generate at least one bit stream by decoding as many symbols of at least one possible slot length among a plurality of slot lengths according to a previous decoding result; an error checker adapted to perform error checking on the bit stream from the decoder; and a controller adapted to provide symbols of one more consecutive slot to the decoder, if the error checking failed, and acquire control information from the error checking-passed bit stream, if the error check passed,.
  • a method for receiving control information transmitted from a transmitter using one of a plurality of slot lengths in a high-speed packet transmission mobile communication system comprises the steps of generating at least one bit stream by decoding as many symbols of at least one possible slot length among the slot lengths according to a previous decoding result by a decoder that receives symbols by the slot; performing error checking on the bit stream; acquiring control information from the error checking-passed bit stream, if the error checking passed; and providing symbols of one more consecutive slot to the decoder if the error checking failed and repeating the above steps until the error checking passes.
  • a method for receiving control information transmitted from a transmitter over code-division-multiplexed first and second control channels using one of a plurality of slot lengths in a high-speed packet transmission mobile communication system comprise the steps of generating at least one first bit stream by decoding as many symbols of at least one possible slot length among a plurality of slot lengths according to a previous decoding result by a first decoder that receives symbols by the slot over the first control channel; performing error checking on the first bit stream; providing symbols of one more consecutive slot to the first decoder until the error checking is passes, if the error checking on the first bit stream failed, and repeating the above steps to detect a slot length used for the first slot channel; acquiring first control information with a first user identifier from the first bit stream corresponding to the detected slot length; decoding as many symbols as the detected slot length to generate a second bit stream by a second decoder that receives symbols by the slot over the second control channel if the first user identifie
  • an apparatus for receiving control information transmitted from a transmitter using one of a plurality of slot lengths in a high-speed packet transmission mobile communication system.
  • the apparatus comprises a decoder adapted to receive symbols by the slot, and generate a plurality of bit streams and frame quality metrics for the bit streams by decoding as many symbols as each of the slot lengths an error checker for performing error checking on the bit streams; and a controller adapted to compare frame quality metrics for the error checking-passed bit streams with each other if error checking on at least 2 bit streams passed, select one bit stream having the maximum frame quality metric, and acquire control information from the selected bit stream.
  • a method for receiving control information transmitted from a transmitter using one of a plurality of slot lengths in a high-speed packet transmission mobile communication system comprises the steps of generating a plurality of bit streams and frame quality metrics for the bit streams by decoding as many symbols as each of the slot lengths by a decoder that receives symbols by the slot; performing error checking on the bit streams; and comparing frame quality metrics for the error checking-passed bit streams with each other, if error checking on at least 2 bit streams passed, selecting one bit stream having the maximum frame quality metric, and acquiring control information from the selected bit stream.
  • the present invention provides herein a receiver structure for efficiently demodulating a packet data control channel (PDCCH) that transmits various control information necessary for the demodulation of a packet data channel (PDCH) in a mobile communication system which is capable of supporting a multimedia service including a voice service and a low-speed circuit and high-speed packet data service, using a 1x bandwidth.
  • the present invention provides a receiver structure for efficiently receiving a plurality of packet data control channels which are multiplexed by code division multiplexing (CDM).
  • CDM code division multiplexing
  • forward link refers to a link transmitted from a base station of a known cellular communication system to a mobile station
  • reverse link refers to a link transmitted from a mobile station to a base station
  • Channels for a forward link packet data service are divided into a common channel, a control channel and a traffic channel.
  • the common channel typically represents a pilot channel (PICH), and is used to provide a reference amplitude and a phase variation necessary for synchronous demodulation at a mobile station.
  • the traffic channel includes a packet data channel (PDCH) that actually carries forward packet data
  • the control channel includes two separated channels that transmit control information related to the packet data channel.
  • a first control channel transmits, to a mobile station, subpacket length information indicating the number of slots constituting forward packet data.
  • a second control channel transmits, to a mobile station, (i) a medium access control identifier (MAC_ID) as a user identifier indicating a destination mobile station of a forward transmission packet, (ii) a subpacket identifier (SP_ID) indicating whether a transmission packet is a new packet or a retransmitted packet, (iii) an automatic repeat request (ARQ) channel identifier (ARQ_ID) indicating an ARQ channel corresponding to a transmission packet among a plurality of ARQ channels when parallel transmission is used, (iv) an encoder packet (EP) size indicating a size of a transmission packet, and (v) a Walsh space indicator indicating Walsh codes used for a packet data channel.
  • the secondary packet data control channel transmits, to a mobile station, (i) a medium access control identifier (MAC_ID) as a user
  • F-PDCH forward packet data channel
  • each mobile station Since a forward packet data channel (F-PDCH) is simultaneously received at all mobile stations, each mobile station must distinguish a packet uniquely assigned to its user for accurate packet reception. Since user information and control information for a packet transmitted over F-PDCH are separately transmitted over two control channels, packet data transmitted over F-PDCH cannot be restored until demodulation on the two control channels is completed. Actually, however, demodulation on the F-PDCH can be performed after demodulation on the F-SPDCCH out of the two control channels is completed. This is a result of the length information of a packet transmitted over F-PPDCCH can be spontaneously determined by demodulating F-SPDCCH. In an embodiment of the present invention, data received on F-PDCH is temporarily stored until demodulation on F-SPDCCH is completed.
  • a mobile station cannot determine (i) whether data received on F-PDCH is data assigned thereto, (ii) a size of a received packet, (iii) a modulation scheme, (iv) whether a received packet is a retransmitted packet, and (v) Walsh code numbers in use, until demodulation on the F-SPDCCH is completed.
  • CDM when CDM is used, there may simultaneously exist a plurality of F-SPDCCHs. Actually, even though CDM is used, the maximum number of available SPDCCHs is limited to 2 due to limitations on performance.
  • a base station since a base station transmits control information for F-PDCH of each user over as many independent F-SPDCCHs as the number of users, a mobile station must detect only a particular F-SPDCCH including control information indicating transmission of packet data thereto from the F-SPDCCHs, and then demodulate the F-SPDCCH.
  • the present invention provides a receiver and reception method for effectively demodulating a forward packet data control channel (F-PDCCH) that transmits control information necessary for demodulation of a packet data channel (PDCH), in a system that uses CDM in order to simultaneously support a packet data service to a plurality of users in addition to time division multiplexing (TDM) fundamentally used in F-PDCH for packet data transmission.
  • F-PDCCH forward packet data control channel
  • PDCH packet data channel
  • CDM time division multiplexing
  • FIG. 1 is a block diagram illustrating an example of a structure of a packet data channel (PDCH) transmitter according to an embodiment of the present invention.
  • a cyclic redundancy code (CRC) generator 2 generates a CRC for input packet data having a predetermined number of bits, and attaches the generated CRC to the input packet data.
  • the CRC has 8 bits.
  • a tail bit generator 4 attaches tail bits e.g., 8 zero-bits for convergence during decoding, to the CRC-attached packet data from the CRC generator 2.
  • An encoder 6 encodes a bit stream from the tail bit generator 4 and generates code symbols or coded symbols.
  • the encoder 6 represents a turbo encoder that turbo-encodes an input bit stream and generates a predetermined number of code symbols according to a code rate R. For example, if a code rate of 1/5 is used, the encoder 6 generates 5 code symbols X, Y0, Y0', Y1 and Y1' for 1 input bit.
  • a channel interleaver 8 interleaves the code symbols from the encoder 6.
  • a symbol selector 10 selects (or repeatedly selects) a predetermined number of symbols among the interleaved symbols from the channel interleaver 8.
  • the symbols generated from the symbol selector 10 become a quasi complementary turbo code (QCTC).
  • QCTC quasi complementary turbo code
  • a scrambling code generator 12 generates a scrambling sequence for scrambling symbols transmitted over a forward packet data channel.
  • An exclusive OR (XOR) operator 13 performs a logical XOR operation on the symbols from the symbol selector 10 and the scrambling sequence from the scrambling code generator 12, and generates scrambled symbols.
  • a modulator 14 modulates the scrambled symbols from the XOR operator 13, and generates complex modulation symbols or modulated symbols for an in-phase (I) channel and a quadrature-phase (Q) channel.
  • a symbol demultiplexer (DEMUX) 16 demultiplexes the modulation symbols from the modulator 14 into preferably as many modulation symbols as the number of Walsh codes currently available for a packet data channel (PDCH), and then outputs the demultiplexed modulation symbols over a plurality of I channels and Q channels.
  • a plurality of Walsh coverers 18 and 20 each receive symbols on a corresponding I channel and Q channel from the symbol demultiplexer 16, and spread the received symbols with a corresponding Walsh code among the Walsh codes available for PDCH.
  • a Walsh chip level summer 22 chip-level-sums outputs of the Walsh coverers 18 and 20 according to I and Q channels, and generates its outputs over an I channel and a Q channel.
  • the I channel and the Q channel of the Walsh chip level summer 22 are applied to terminals A and B of FIG. 3 , respectively.
  • the I channel and the Q channel are converted into a radio frequency (RF) band through pseudo-random noise (PN) spreading and baseband filtering, and then transmitted through an antenna.
  • RF radio frequency
  • PN pseudo-random noise
  • FIG. 2 is a block diagram illustrating an example of a structure of a secondary packet data control channel (SPDCCH) transmitter according to an embodiment of the present invention.
  • a CRC generator 24 generates a CRC for an input sequence representing control information necessary for demodulation of a packet data channel, and attaches the generated CRC to the input sequence.
  • the CRC has 8 bits.
  • a tail bit generator 26 attaches 8 tail bits e.g., 8 zero-bits for convergence during decoding, to the CRC-attached input sequence from the CRC generator 24, and outputs a 29-bit stream.
  • a convolutional encoder 28 convolutional-encodes the tail-attached bit stream from the tail bit generator 26, and generates code symbols.
  • a constraint length K of the convolutional encoder 28 is preferably 9.
  • a symbol puncturer 32 punctures a predetermined number of symbols from the repeated symbols provided from the symbol repeater 30.
  • An interleaver 34 interleaves the punctured symbols from the symbol puncturer 32.
  • a block interleaver is used herein as the interleaver 34. As a result, the block interleaver 34 outputs 48N symbols every N slots.
  • a modulator 36 Quadrature Phase Shift Keying (QPSK) modulates the interleaved symbols provided from the interleaver 34, and generates modulation symbols of I and Q channels.
  • Multipliers 38 and 40 each spread the modulation symbols from the modulator 36 with a Walsh code of length 64, assigned to F-SPDCCH. Outputs of the multipliers 38 and 40 are applied to the terminals A and B of FIG. 3 , respectively. In FIG. 3 , the outputs of the multipliers 38 and 40 are converted into an RF band through PN spreading and baseband filtering, and then transmitted through an antenna.
  • QPSK Quadrature Phase Shift Keying
  • a channel signal generated from the secondary packet data control channel (F-SPDCCH) transmitter of FIG. 2 is CDM-multiplexed with other channel signals such as a primary packet data control channel (F-PPDCCH) signal, a packet data channel (F-PDCH) signal and a pilot channel (PICH) signal before being transmitted.
  • F-PPDCCH primary packet data control channel
  • F-PDCH packet data channel
  • PICH pilot channel
  • control information transmitted over a secondary packet data control channel comprises(i) 6-bit MAC_ID indicating a user scheduled to receive packet data, (ii) 2-bit SP_ID indicating whether a transmission packet is a retransmitted packet, (iii) 2-bit ARQ_ID indicating an ARQ channel of packet data, and (iv) 3-bit EP_SIZE indicating a size of an encoder packet (EP).
  • the control information further includes corresponding additional information such as Walsh space indicator and CDM channel indicator.
  • a mobile station acquires the above-stated information based on the control information received over the secondary packet data control channel (F-SPDCCH), and uses the acquired information for demodulation of a packet data channel.
  • FIG. 3 is a block diagram illustrating an example of a structure for transmitting channel signals generated by the transmitters of FIGs. 1 and 2 in a base station according to an embodiment of the present invention.
  • a gain controller 42 multiplies I channel and Q channel signals from, for example, PDCH, PPDCCH and SPDCCH transmitters by a corresponding gain.
  • a chip level summer 44 chip-level-sums the gain-controlled complex channel signals according to I and Q channels, and generates an output through an I channel and a Q channel.
  • a PN spreader 46 multiplies the I channel and Q channel signals from the chip level summer 44 by PN codes PN_I and PN_Q for the complex channels.
  • Baseband filters 48 and 50 each baseband-filters the PN-spread signals received from the PN spreader 46.
  • Multipliers 52 and 54 each convert their corresponding baseband-filtered signals into corresponding carrier bands fc.
  • An adder 56 generates a forward modulated waveform by adding outputs of the multipliers 52 and 54, and then transmits the generated forward modulated waveform to an antenna (not shown).
  • FIG. 4 is a block diagram illustrating an example of a structure of a secondary packet data control channel (F-SPDCCH) receiver according to an embodiment of the present invention.
  • the receiver of FIG. 4 corresponds to the transmitter of FIG. 2 .
  • multipliers 51 and 52 despread received signals preferably with a Walsh code W i 64 assigned to the secondary packet data control channel.
  • a QPSK demodulator 53 QPSK-demodulates outputs of the multipliers 51 and 52, and generates demodulation symbols or demodulated symbols.
  • a deinterleaver 54 deinterleaves the demodulation symbols from the QPSK demodulator 53 according to a predetermined deinterleaving rule.
  • a symbol inserter 55 inserts zero-symbols into the deinterleaved symbols from the deinterleaver 54 according to a predetermined insertion rule.
  • a symbol combiner 56 combines the symbols provided from the symbol inserter 55 according to a predetermined combining rule.
  • a decoder 57 under the control of a controller 59, decodes the symbols of consecutive slots provided from the symbol combiner 56 and generates a bit stream representing control information MAC_ID, SP_ID, ARQ_ID, EP_SIZE, and so on of the secondary packet data control channel.
  • the bit stream is divided into information bits and CRC bits.
  • a CRC checker 58 performs a CRC check on the information bits generated from the decoder 57, and provides the CRC check result to the controller 59.
  • the controller 59 controls a decoding period of the decoder 57, and determines whether a secondary packet data control channel is acquired or not, based on the CRC check result of the CRC checker 58. If the CRC check passed for example, CRC OK, the controller 59 provides a packet data channel (PDCH) receiver with information bits except the CRC bits so that the PDCH receiver can use the information bits for the demodulation of packet data.
  • PDCH packet data channel
  • a secondary packet data control channel supports a plurality of data rates. Therefore, the controller 59 must detect a data rate and a slot length, used during transmission of control information, from the data decoded by the decoder 57.
  • a decision method of detecting a data rate from received data is classified into a pre-decision method and a post-decision method.
  • the pre-decision method detects a data rate before decoding of a frame, and then performs decoding according to the detected data rate
  • the post-decision method detects a data rate after decoding of a frame, and then acquires a decoding result data corresponding to the detected data rate.
  • the post-decision method generally performs decoding on all possible data rates, and then determines a data rate based on the decoding results.
  • an error check result based on CRC bits included in received data serves as a criterion for determining a data rate.
  • the post-decision method preferably performs, in principle, decoding on possible slot lengths of the SPDCCH each time symbols of every slot are received. Performing decoding on all possible slot lengths every slot even though possible slot lengths of the SPDCCH are predetermined is very inefficient and causes an increase in delay before reception of a packet data channel.
  • the present invention can detect an accurate slot length by performing decoding as many times as an actually needed number according to decoding results at a previous slot, instead of performing decoding on all possible slot lengths of SPDCCH every slot in order to demodulate SPDCCH.
  • an operation of detecting a data rate, or a slot length, of SPDCCH according to the present invention will be described in detail with reference to the accompanying drawings, and for the sake of convenience, an operation of the decoder 57 will first be described. In addition, a description will be separately made of one case where one SPDCCH is used and another case where a plurality of CDM-multiplexed SPDCCHs are used.
  • FIG. 5 is a flow chart illustrating an example of steps for receiving a secondary packet data control channel (SPDCCH) in a mobile station according to an embodiment of the present invention, wherein one SPDCCH is used. This procedure is assumed to be performed by the controller 59 of FIG. 4 .
  • SPDCCH secondary packet data control channel
  • the 1-slot flag, 2-slot flag and 4-slot flag are provided to detect when SPDCCH uses 1, 2 and 4 slots, respectively.
  • the 8-slot flag is provided to detect when SPDCCH uses 4 slots and PDCH uses 8 slots.
  • the controller 59 receives symbols of one slot over SPDCCH in step 104, and increases the slot number by '1' in step 106.
  • the above-stated symbols represent the symbols that were previously received and stored in a buffer arranged in a previous stage of the decoder after being subject to Walsh despreading and symbol combining.
  • the controller 59 stores a smaller value out of the increased slot number and a slot number '4' as a new slot number in step 108, and then proceeds to step 110 because the SPDCCH does not use more than 4 slots.
  • “success in decoding” means that the CRC check on the decoding result is successful or has passed. If decoding is not successful even after 4 slots are received, the slot number becomes 4 as before, even though symbols of an additional slot are received and decoded. Therefore, in an embodiment of the present invention, decoding is performed on preferably only 4 slots. However, when 5 or more slots are received, decoding is performed on symbols of the last received 4 slots.
  • the controller 59 proceeds to steps 116, 118, 120 and 122, and controls (orders) the decoder 57 to perform decoding on symbols of the last received 4, 4, 2 and 1 slots, respectively.
  • the 4 decoding operations can be performed either sequentially by a common decoder, or in parallel by 4 separate decoders having the same structure.
  • the slot number is '3', it means that symbols of 3 slots have been received after success in decoding, so it is possible to perform decoding on symbols of the last received 1 slot and 2 slots. That is, since SPDCCH does not use 3 slots, decoding is performed in the same way when the slot number is '3' and the slot number is '2'.
  • step 124 the controller 59 performs a CRC check on 8 slots using an information bit stream obtained by performing decoding in step 116. If the CRC check passed for example, CRC OK, the controller 59 sets the 8-slot flag to '1' in step 126, and sets the slot number to '-4' in step 128, and then returns to step 102. However, if the CRC check failed, the controller 59 proceeds to step 142.
  • setting the 8-slot flag to '1' means that a subpacket length (SP_LEN) of a packet data channel is determined as 8 slots, since decoding on 4 slots with an initial state '0' is successful.
  • SP_LEN subpacket length
  • the slot number is set to '-4' in order to disregard 4 F-SPDCCH slots received from now on.
  • the controller 59 performs a CRC check on 4 slots using an information bit stream obtained by performing decoding in step 118. If the CRC check passed, the controller 59 sets the 4-slot flag to '1' in step 132, and then proceeds to step 142. Otherwise, if the CRC check failed, the controller 59 proceeds directly to step 142.
  • step 134 the controller 59 performs a CRC check on 2 slots using an information bit stream obtained by performing decoding in step 120. If the CRC check passed, the controller 59 sets the 2-slot flag is set to '1' in step 136, and then proceeds to step 142. If, however, the CRC check failed, the controller 59 proceeds directly to step 142. Further, in step 138, the controller 59 performs a CRC check on 1 slot using an information bit stream obtained by performing decoding in step 122. If the CRC check passed, the controller 59 sets the 1-slot flag to '1' in step 140, and then proceeds to step 142. If, however, the CRC check failed, the controller 59 proceeds directly to step 142.
  • step 142 the controller 59 determines whether any one of the slot flags is set to '1'. If any one of the slot flags is set to '1', the controller 59 selects in step 144 one accurate decoding result including F-PDCH-related control information from at least one decoding result among the decoding results of the steps 116, 118, 120 and 122.
  • the control information includes MAC_ID, ARQ_ID, EP_SIZE, and SP_ID.
  • a slot length corresponding to the selected decoding result is detected as a slot length, or a data rate, of the SPDCCH, used by a transmitter.
  • the controller 59 selects in step 144 one decoding result corresponding to only one slot flag set to '1' among the slot flags. Actually, however, due to unpredictable distortion or noise of a radio environment, CRC check on two or more slot lengths may pass. In this case, the controller 59 selects one preferable decoding result among the decoding results corresponding to two or more slot flags set to '1', using an auxiliary criterion other than the CRC check result. A more detailed description of the operation performed in step 144 will be made with reference to FIGs. 7 to 10 .
  • step 142 If it is determined in step 142 that there is no flag set to '1', the controller 59 returns to step 102 because symbols of one more consecutive slot must be received, since decoding on symbols of F-SPDCCH, received up to the present, is not successful, i.e., acquiring control information has failed.
  • FIGs. 6A and 6B are flow charts illustrating an example of steps for receiving two or more secondary packet data control channels (SPDCCHs) in a mobile station according to an embodiment of the present invention.
  • FIG. 6A illustrates a procedure for receiving a first secondary packet data control channel (SPDCCH1) out of two secondary packet data control channels SPDCCH1 and SPDCCH2 transmitted by a base station by CDM
  • FIG. 6B illustrates a procedure for receiving a second secondary packet data control channel (SPDCCH2).
  • SPDCCH1 first secondary packet data control channel
  • SPDCCH1 and SPDCCH2 transmitted by a base station by CDM
  • FIG. 6B illustrates a procedure for receiving a second secondary packet data control channel (SPDCCH2).
  • SPDCCH1 first secondary packet data control channel
  • SPDCCH1 and SPDCCH2 transmitted by a base station by CDM
  • FIG. 6B illustrates a procedure for receiving a second secondary packet data control channel (SPDCCH2).
  • SPDCCH2 secondary packet data control channel
  • the controller 59 receives symbols of one slot over F-SPDCCH in step 204, and increases the slot number by '1' in step 206.
  • the controller 59 stores a smaller value out of the increased slot number and a slot number '4' as a new slot number in step 208, and then proceeds to step 210. This is because the SPDCCH does not use more than 4 slots.
  • the above-stated symbols represent the symbols that were previously received and stored in a buffer arranged in a previous stage of a decoder after being subject to Walsh despreading and symbol combining.
  • the 4 decoding operations can be performed either sequentially by a common decoder, or in parallel by 4 separate decoders having the same structure.
  • the controller 59 performs a decoding operation (step 216) where an initial state '0' is used to detect F-PDCH having an 8-slot length and a decoding operation (step 218) where an initial state '1' is used to detect F-PDCH having a 4-slot length.
  • step 224 the controller 59 performs CRC a check on 8 slots using an information bit stream obtained by performing decoding in step 216. If the CRC check passed for example, CRC OK, the controller 59 sets the 8-slot flag to '1' in step 226, and sets the slot number to '-4' in step 228, and then returns to step 202. However, if the CRC check failed, the controller 59 proceeds to step 242 of FIG. 6B .
  • setting the 8-slot flag to '1' means that a subpacket length (SP_LEN) of a packet data channel (PDCH) is determined as 8 slots, since decoding on 4 slots with an initial state '0' is successful.
  • SP_LEN subpacket length
  • PDCH packet data channel
  • the slot number is set to '-4' in order to disregard 4 F-SPDCCH slots received from now on.
  • the controller 59 performs a CRC check on 4 slots using an information bit stream obtained by performing decoding in step 218. If the CRC check passed, the controller 59 sets the 4-slot flag to '1' in step 232, and then proceeds to step 242. Otherwise, if the CRC check failed, the controller 59 directly proceeds to step 242.
  • step 234 the controller 59 performs a CRC check on 2 slots using an information bit stream obtained by performing decoding in step 220. If the CRC check passed, the controller 59 sets the 2-slot flag to '1' in step 236, and then proceeds to step 242. If, however, the CRC check failed, the controller directly proceeds to step 242. Further, in step 238, the controller performs CRC check on 1 slot using an information bit stream obtained by performing decoding in step 222. If the CRC check passed, the controller sets the 1-slot flag to '1' in step 240, and then proceeds to step 242. If, however, the CRC check failed, the controller 59 directly proceeds to step 242.
  • the controller 59 determines in step 242 whether any one of the slot flags is set to '1'. If any one of the slot flags is set to '1', the controller 59 selects in step 244 one accurate decoding result including F-PDCH-related control information from at least one decoding result among the decoding results of the steps 216, 218, 220 and 222.
  • the control information includes MAC_ID1, ARQ_ID1, EP_SIZE1, and SP_ID1.
  • a slot length corresponding to the selected decoding result is detected as a slot length, or a data rate, used by a transmitter for transmission of F-SPDCCH.
  • the controller 59 selects one preferable decoding result, using an auxiliary metric other than the CRC check result, and its detailed description will be made later.
  • the controller 59 compares MAC_ID1, user identification information of F-SPDCCH1, included in control information obtained from the selected decoding result with its own MAC_ID assigned from a base station. If the two MAC_IDs are identical to each other, the controller 59 controls in step 250 an F-PDCH receiver to demodulate a corresponding packet data channel F-PDCH1 using the control information.
  • the F-PDCH1 refers to PDCH indicated by control information of F-SPDCCH1.
  • step 252 the controller 59 controls in step 252 the F-PDCH receiver to suspend processing on F-PDCH1, and then proceeds to step 254.
  • step 254 the controller 59 starts processing on F-SPDCCH2 according to a subpacket length (SP_LEN) of F-PDCH, acquired from the F-SPDCCH1.
  • SP_LEN subpacket length
  • the controller 59 determines a subpacket length SP_LEN2 of PDCH2, indicated by F-SPDCCH2, according to a subpacket length SP_LEN1 of PDCH1, acquired by demodulating F-SPDCCH1. If the subpacket length SP_LEN1 acquired from F-SPDCCH1 is 8 slots, the controller 59 controls in step 256 the decoder to decode symbols of 4 slots of F-SPDCCH2 by setting the initial state to '0', and an input to the decoder becomes symbols of the last 4 slots of F-SPDCCH2 received together with F-SPDCCH1.
  • the controller 59 controls in step 258 the decoder to decode symbols of 4 slots of F-SPDCCH2 by setting the initial state to '1', and likewise, an input to the decoder becomes symbols of the last 4 slots of F-SPDCCH2 received together with F-SPDCCH1.
  • the controller 59 controls in step 260 the decoder to decode symbols of 2 slots of F-SPDCCH2, and an input to the decoder becomes symbols of the last 2 slots of F-SPDCCH2 received together with F-SPDCCH1. Finally, if a subpacket length SP_LEN1 acquired from F-SPDCCH1 is '1', the controller 59 controls in step 262 the decoder to decode symbols of 1 slots of F-SPDCCH2, and an input to the decoder becomes symbols of the last 1 slot of F-SPDCCH2 received together with F-SPDCCH1.
  • step 264 the controller 59 performs CRC check on one of the decoding results obtained in steps 256 to 262. If the CRC check failed, the controller 59 controls in step 268 an F-PDCH receiver to suspend processing on F-PDCH2 corresponding to F-SPDCCH2, and then returns to step 202 in order to continuously perform decoding on F-SPDCCH. Otherwise, if the CRC check passed, the controller 59 extracts, in step 266, control information necessary for demodulating a corresponding packet data channel F-PDCH2, from the decoding result of F-SPDCCH2. The control information includes MAC_ID2, ARQ_ID2, EP_SIZE2, and SP_ID2. Further, a slot length, or data rate, of F-SPDCCH2 is determined to be identical to the data rate of F-SPDCCH1.
  • step 270 the controller 59 compares MAC_ID2 included in the control information with its own MAC_ID assigned from a base station. If the two MAC_IDs are identical to each other, the controller 59 controls in step 272 an F-PDCH receiver to perform processing on F-PDCH2 according to the control information. If, however, the two MAC_IDs are different from each other, the controller 59 controls in step 268 the F-PDCH receiver to suspend processing on F-PDCH2, and then returns to step 202.
  • the F-SPDCCH1, F-SPDCCH2, F-PDCH1 and F-PDCH2 are simultaneously received, and in order to process first and second F-PDCHs according to the decoding results on first and second F-SPDCCHs, it is necessary to buffer the first and second F-PDCHs while processing the first and second F-SPDCCHs.
  • a symbol error rate is typically used as the auxiliary metric.
  • the symbol error rate means a difference in the number of symbols based on the result obtained by re-encoding decoded data of a received frame and then comparing the re-encoded data with an original received frame by the symbol. If CRC check on a plurality of candidate rates passed, a receiver compares symbol error rates of the CRC check-passed data rates to detect a data rate having the least symbol error rate.
  • the Viterbi decoder performs, on convolutionally-encoded symbols, a Viterbi decoding algorithm comprises branch metric calculation, path selection on a trellis, and trace-back.
  • This algorithm outputs a difference between path metric values together with decoded data, each time input symbols are decoded. It can be determined that as the path metric difference becomes larger, decoding is performed more accurately. Therefore, the path metric difference can be used as a decoding reliability criterion.
  • a difference between path metrics input to each state (or node) on a trellis is referred to as "frame quality metric (FQM)", and an accurate slot length of SPDCCH is detected using the FQM.
  • FQM frame quality metric
  • FIG. 7 is a block diagram illustrating an example of a partial structure of an SPDCCH receiver with a Viterbi decoder according to an embodiment of the present invention.
  • a Viterbi decoder 60, a CRC checker 70, and a controller 80 for controlling these elements are selectively illustrated in FIG. 7 , and the other elements of the SPDCCH receiver are illustrated in FIG. 4 .
  • the controller 80 collects information bit streams, frame quality metrics FQMn and CRC check results CRCn, decoded for each of all possible slot lengths, and detects a slot length of an information bit stream having the largest frame quality metric among good-CRC (or CRC check-passed) information bit streams.
  • the Viterbi decoder 60 includes symbol converter 61, a branch metric generator 62, a path metric calculator 63, a path metric memory 64, a path memory 65, and a trace-back unit 66.
  • the Viterbi decoder 60 of FIG. 8 performs decoding in such a way that it searches (detects) a code sequence most similar to an input code sequence from all possible code sequences on a particular code.
  • the symbol converter 61 arranged in front of the branch metric generator 62, converts input symbols in the form of 2's complement into a soft decision value in the form of signed-magnitude, for decoding.
  • the branch metric generator 62 generates branch metric values for all possible branches at a current state for the symbols in the form of the received soft decision value, and the path metric calculator 63 calculates path metric values for a surviving path toward a particular state based on the branch metric values, and stores the calculated path metric values in the path metric memory 64.
  • an optimal surviving path having the minimum path metric value determined by comparing path metric values stored for two or more states is selected by the path metric calculator 63, and the history of the selected surviving path is stored in the path memory 65.
  • the trace-back unit 66 determines a decoded information bit stream by tracing-back the surviving path stored in the path memory 65.
  • the Viterbi decoder selects a path input to a corresponding state by comparing path metric values for received paths, at each state on a trellis expressed by paths extending from a particular state to the next state, and if a difference of path metric values between a selected surviving path and a non-selected competitor path is large, it could be said that path selection reliability is high at the state. Therefore, if a difference of path metric values between paths input to each state on the trellis is defined as a state quality metric of the state, the difference value can be used as a reliability criterion of a path input to the state. That is, it can be determined that as the state quality metric is larger, reliability of a path input to the state is higher in the Viterbi decoding process.
  • a state quality metric of a 0-state can be used as a decoding reliability criterion of the entire frame. In an embodiment of the present invention, this is defined as a frame quality metric, and as the frame quality metric becomes larger, there is a higher probability that decoding on a frame is performed accurately.
  • a path metric difference value exceeds a predetermined threshold value at a particular state, a value of a bit assigned to the state is set to '1', and if the path metric difference value does not exceed the threshold value, the value of the bit assigned to the state is set to '0'.
  • an output bit is '1', it is determined that quality of the decoding result is good, and if the output bit is '0', it is determined that quality of the decoding result is bad.
  • a path metric difference value itself instead of a hard decision value determined by comparing the path metric difference value at the final state with a predetermined threshold value. Therefore, as a result of CRC check by the CRC checker 70 of FIG. 7 , if CRC checks on a plurality of slot lengths are passed, the controller 80 compares path metric difference values, or frame quality metrics, obtained through decoding on each of the CRC check-passed slot lengths, and detects one slot length having the largest frame quality metric. As mentioned before, a slot length is related to a data rate. Therefore, a CRC check-passed slot length will be referred to herein as "candidate rate.”
  • Frame quality metrics for different data rates cannot be directly compared with each other because a code rate and an input frame length have different values according to the data rate. Therefore, the controller 80 multiplies frame quality metrics for the candidate rates by proper normalization factors (NFs), for normalization, and then compares the results with one another. That is, the controller 80 compares the normalized frame quality metrics with one another, and then detects a data rate having the maximum normalized frame quality metric.
  • NFs normalization factors
  • the normalization factors are determined by an input frame length of a decoder according to a code rate.
  • An increase in a code rate causes an increase in a range of a branch metric value accumulated at every state to form a path metric value. Since the path metric value is also accumulated in a calculation process on the trellis, an increase in length of a frame results in an increase in a frame quality metric.
  • the frame length is determined by considering repetition and puncturing during the encoding process.
  • FQM_NFi denotes a normalization factor for a data rate i
  • Ci denotes code rates of the decoder for the data rate i
  • Li denotes an input frame length for the data rate i
  • Ln denotes a maximum frame length.
  • SPDCCH secondary packet data control channel
  • an encoder when 37 bits including tail bits and CRC bits are received, an encoder outputs 48, 96 or 192 bits through repetition and puncturing according to the data rates.
  • Li/Ln 37/37.
  • calculation results of Equation (1) for the data rates are (37/48)*(37/37), (37/96)*(37/37), (37/192)*(37/37), respectively.
  • the normalization factors are determined as 1, 1/2 and 1/4.
  • FIG. 9 is a block diagram illustrating an example of a of the controller 80 for detecting a data rate according to an embodiment of the present invention.
  • the Viterbi decoder 60 decodes the input frame at a code rate corresponding to the data rate n, and provides the decoded data to the CRC checker 70 and a frame quality metric FQMn generated through the decoding to the controller 80.
  • the CRC checker 70 provides CRC check result CRCn to the controller 80 by consulting CRC bits extracted from the decoded data.
  • a candidate rate selector 81 in the controller 80 receives the FQMn and the CRCn and determines whether the CRCn is good. If the CRCn is good, the candidate rate selector 81 provides the frame quality metric FQMn to a multiplier 82.
  • the multiplier 82 multiplies the FQMn by a corresponding normalization factor FQM_NFn, and provides a normalized frame quality metric FQMn*FQM_NFn to a comparator 83.
  • the normalization factor is calculated in the above-stated method.
  • the comparator 83 compares the FQMn*FQM_NFn with a frame quality metric FQM(n-1)*FQM_NF(n-1) normalized for a previous candidate rate, and stores the larger one in its internal register (not shown). If there is no frame quality metric normalized for a previous candidate rate, i.e., if a frame quality metric normalized for a first candidate rate is received, the comparator 83 stores the received frame quality metric in the internal register without performing comparison. After completing the comparison on the normalized frame quality metrics for all candidate rates, the comparator 83 outputs a normalized frame quality metric MaxFQM with a maximum size. A rate detector 84 then detects a data rate corresponding to the MaxFQM.
  • FIG. 10 is a flowchart illustrating an example of steps for detecting a data rate according to an embodiment of the present invention. The algorithm is performed by the controller 80 of FIG. 7 .
  • step 310 the controller 80 initializes, to '0', all internal parameters for performing the data rate detection algorithm, including i for identifying data rates, R indicating an index of a detected data rate, and MaxFQM indicating a frame quality metric currently having the maximum size.
  • the controller 80 increases the current data rate index i by 1 in step 320, and determines in step 330 whether the current data rate index i is identical to the number n of data rates. If the current data rate index i is not identical to the number n of data rates, the controller 80 proceeds to step 340.
  • step 340 the controller 80 determines whether CRC check result CRCi for the current data rate index i is good (CRC OK). If the CRCi is good, the controller 80 proceeds to step 350, and otherwise, returns to step 320.
  • step 350 the controller 80 compares a normalized frame quality metric FQMi*FQM_NFi of a corresponding candidate rate with the MaxFQM. The normalized frame quality metric is generated by multiplying FQM_NFi by a normalization factor corresponding to the FQMi. If the FQMi*FQM_NFi is larger than MaxFQM, the controller 80 proceeds to step 360. Otherwise, the controller 80 returns to step 320 and determines a next data rate.
  • step 360 the controller 80 sets the detected data rate index R to the current data rate index i, and updates the MaxFQM into FQMi*FQM_NFi corresponding to the current data rate index i. After step 360, the controller 80 returns to step 320 and determines the next data rate.
  • step 330 If it is determined in step 330 that the current data rate index i is identical to the number n of data rates, the controller 80 proceeds to step 370, determining that detection for all data rates has been completed.
  • step 370 the controller 80 determines whether the detected data rate index R is equal to '0', to determine whether there exists a detected data rate. If the detected data rate index R is equal to '0', the controller 80 performs a detection fail process in step 390, determining that there is no detected data rate. Otherwise, the controller 80 detects a data rate corresponding to the detected data rate index R in step 380.
  • the present invention can reduce a demodulation time and power consumption of a packet data control channel by providing an efficient demodulation algorithm for the dedicated packet data control channel. Also, when CDM is used to simultaneously support a packet data service to a plurality of users, the present invention can reduce a demodulation time and power consumption of a packet data control channel by providing an algorithm for efficiently demodulating the packet data control channel.
  • the proposed demodulation algorithm for a packet data control channel is used, time delay from a reception time of a packet data channel to a demodulation time of the packet data channel can be reduced, thus contributing to rapid demodulation of the packet data channel.
  • the present invention detects the data rate based on a frame quality metric output from a Viterbi decoder.
  • the rate detection is accomplished along with decoding on a received data frame, preventing a waste of time due to additional calculations and an increase in calculations compared with the existing Viterbi decoder. Therefore, the proposed rate detection method can be effectively applied to a secondary packet data control channel (SPDCCH) defined by IS-2000 1xEVDV standard that requires high-speed processing.
  • SPDCCH secondary packet data control channel

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Claims (27)

  1. Appareil de réception d'informations de commande transmises d'un émetteur en utilisant l'un d'une pluralité de nombres d'intervalles dans un système de communication mobile à transmission par paquets à grande vitesse, l'appareil comprenant :
    un décodeur (57) apte à recevoir des symboles par intervalle et à générer au moins un flux binaire en décodant des symboles d'au moins un nombre possible d'intervalles parmi une pluralité de nombres d'intervalles en fonction de résultats de décodage précédents ;
    un contrôleur d'erreur (58) apte à effectuer un contrôle d'erreur sur l'au moins un flux binaire délivré du décodeur ; et
    un organe de commande (59) apte à fournir des symboles d'au moins un intervalle consécutif au décodeur (57) en cas d'échec du contrôle d'erreur, et à acquérir des informations de commande de l'au moins un flux binaire en cas de réussite du contrôle d'erreur ;
    caractérisé en ce que le décodeur (57) est apte à générer l'au moins un flux binaire en décodant les symboles reçus d'un intervalle, si des symboles d'un intervalle sont reçus ; en décodant des symboles du dernier intervalle reçu et de deux intervalles parmi les symboles reçus de deux intervalles ou de trois intervalles, si des symboles des deux intervalles ou des trois intervalles sont reçus, et en décodant des symboles du dernier intervalle reçu, des symboles des deux derniers intervalles reçus et des symboles de quatre intervalles parmi les symboles reçus de quatre intervalles, si des symboles des quatre intervalles sont reçus.
  2. Appareil selon la revendication 1, dans lequel les symboles sont reçus par le décodeur (57) après la détection réussie d'une information de commande précédente.
  3. Appareil selon l'une quelconque des revendications 1 et 2, dans lequel le décodeur (57) est un décodeur Viterbi (60).
  4. Appareil selon l'une quelconque des revendications 1 à 3, dans lequel l'organe de commande (59) comprend un moyen pour extraire un identifiant d'utilisateur à partir des informations de commande acquises, et pour extraire à partir des informations de commande acquises un identifiant de canal de demande à répétition automatique, ARQ, une taille de paquet de codeur et un identifiant de sous-paquet pour démoduler des données de paquet transmises de l'émetteur, si l'identifiant d'utilisateur extrait est identique à un identifiant d'utilisateur de l'émetteur.
  5. Appareil selon l'une quelconque des revendications 1 à 4, dans lequel le décodeur (57) comprend un moyen pour décoder des symboles d'au moins un nombre possible d'intervalles comprenant le dernier intervalle reçu parmi des intervalles reçus consécutivement.
  6. Appareil selon la revendication 5, dans lequel le nombre possible d'intervalles comprend au moins l'un de 1, 2 et 4.
  7. Appareil selon l'une quelconque des revendications 1 à 6, comprenant un moyen pour démoduler des données de paquet en utilisant les informations de commande acquises.
  8. Appareil selon l'une quelconque des revendications 1 à 7, dans lequel le décodeur comprend un moyen (63) pour délivrer au moins une métrique de qualité de trame pour l'au moins un flux binaire avec l'au moins un flux binaire.
  9. Appareil selon la revendication 8, dans lequel l'organe de commande comprend un moyen (83) pour comparer les métriques de qualité de trame d'au moins deux flux binaires et pour sélectionner un flux binaire ayant la métrique de qualité de trame maximale afin d'acquérir les informations de commande, si le nombre de flux binaires ayant réussi le contrôle d'erreur est supérieur ou égal à 2.
  10. Appareil selon l'une quelconque des revendications 8 et 9, dans lequel le moyen (63) est apte à calculer les métriques de qualité de trame sur la base d'une différence entre des valeurs de métriques de chemin entrées dans un état final sur un treillis selon un algorithme de décodage Viterbi pour les symboles reçus et à délivrer les métriques de qualité de trame.
  11. Appareil selon l'une quelconque des revendications 8 à 10, dans lequel l'organe de commande (59) normalise les métriques de qualité de trame en multipliant les métriques de qualité de trame par des facteurs de normalisation sur la base d'un nombre d'intervalles correspondant aux métriques de qualité de trame pour les deux flux binaires ou plus avant de comparer les métriques de qualité de trame entre elles.
  12. Appareil selon la revendication 11, dans lequel les facteurs de normalisation sont déterminés par : FQM_NFi = Ci * Li / Ln
    Figure imgb0006
    où FQM_NFi correspond à un facteur de normalisation pour un i-ème nombre d'intervalles, Ci correspond à un débit de code du décodeur pour un i-ème nombre d'intervalles, Li correspond à une longueur de symboles d'entrée du décodeur (57) pour un i-ème nombre d'intervalles, et Ln correspond à une longueur maximale de symboles d'entrée pour le décodeur (57).
  13. Appareil selon l'une quelconque des revendications 1 à 12, dans lequel le décodeur (57) est apte à générer une pluralité de flux binaires et des métriques de qualité de trame.
  14. Procédé de réception d'informations de commande transmises d'un émetteur en utilisant l'un d'une pluralité de nombres d'intervalles dans un système de communication mobile à transmission par paquets à grande vitesse, le procédé comprenant les étapes de :
    la réception de symboles par intervalle ;
    la génération d'au moins un flux binaire en décodant des symboles d'au moins un nombre possible d'intervalles parmi la pluralité de nombres d'intervalles en fonction de résultats de décodage précédents ;
    l'exécution d'un contrôle d'erreur sur l'au moins un flux binaire ;
    en cas de réussite du contrôle d'erreur, l'acquisition d'informations de commande de l'au moins un flux binaire ; et
    en cas d'échec du contrôle d'erreur, la fourniture de symboles de l'au moins un intervalle consécutif pour un décodage ;
    caractérisé en ce que l'au moins un flux binaire est généré en décodant les symboles reçus d'un intervalle, si des symboles d'un intervalle sont reçus ; en décodant des symboles du dernier intervalle reçu et de deux intervalles parmi les symboles reçus de deux intervalles ou de trois intervalles, si des symboles des deux intervalles ou des trois intervalles sont reçus, et en décodant des symboles du dernier intervalle reçu, des symboles des deux derniers intervalles reçus et des symboles de quatre intervalles parmi les symboles reçus de quatre intervalles, si des symboles des quatre intervalles sont reçus.
  15. Procédé selon la revendication 14, dans lequel les symboles sont reçus après la détection réussie d'une information de commande précédente.
  16. Procédé selon l'une quelconque des revendications 14 et 15, dans lequel les symboles à décoder comprennent le dernier intervalle consécutif parmi une pluralité de nombres d'intervalles.
  17. Procédé selon l'une quelconque des revendications 14 à 16, dans lequel un décodage Viterbi est effectué.
  18. Procédé selon l'une quelconque des revendications 14 à 17, dans lequel les informations de commande acquises sont fournies pour la démodulation de données de paquet transmises de l'émetteur, et comprennent un identifiant d'utilisateur, un identifiant de canal de demande à répétition automatique, ARQ, une taille de paquet de codeur et un identifiant de sous-paquet.
  19. Procédé selon l'une quelconque des revendications 14 à 18, dans lequel l'étape d'acquisition d'informations de commande comprend l'étape d'extraction d'un identifiant d'utilisateur à partir des informations de commande acquises, et l'extraction à partir des informations de commande acquises d'un identifiant de canal de demande à répétition automatique, ARQ, d'une taille de paquet de codeur et d'un identifiant de sous-paquet pour démoduler des données de paquet transmises de l'émetteur, si l'identifiant d'utilisateur extrait est identique à un identifiant d'utilisateur de l'émetteur.
  20. Procédé selon l'une quelconque des revendications 14 à 19, dans lequel le nombre d'intervalles comprend 1, 2 et 4.
  21. Procédé selon l'une quelconque des revendications 14 à 20, dans lequel le décodeur (57) délivre au moins une métrique de qualité de trame pour l'au moins un flux binaire avec l'au moins un flux binaire.
  22. Procédé selon l'une quelconque des revendications 14 à 21, dans lequel l'étape d'acquisition d'informations de commande comprend l'étape de comparaison, si le nombre de flux binaires ayant réussi le contrôle d'erreur est supérieur ou égal à 2, de métriques de qualité de trame délivrées du décodeur (57) pour les deux flux binaires ou plus et de sélection d'un flux binaire ayant la métrique de qualité de trame maximale afin d'acquérir les informations de commande.
  23. Procédé selon l'une quelconque des revendications 21 et 22, dans lequel la métrique de qualité de trame représente une différence entre des valeurs de métriques de chemin entrées dans un état final sur un treillis selon un algorithme de décodage Viterbi pour les symboles reçus.
  24. Procédé selon l'une quelconque des revendications 21 à 23, dans lequel l'étape d'acquisition d'informations de commande comprend l'étape de normalisation des métriques de qualité de trame en multipliant les métriques de qualité de trame par des facteurs de normalisation sur la base d'un nombre d'intervalles correspondant aux métriques de qualité de trame pour les flux binaires avant la comparaison des métriques de qualité de trame entre elles.
  25. Procédé selon la revendication 24, dans lequel les facteurs de normalisation sont déterminés par : FQM_NFi = Ci * Li / Ln
    Figure imgb0007
    où FQM_NFI correspond à un facteur de normalisation pour un i-ème nombre d'intervalles, Ci correspond à un débit de code du décodeur pour un i-ème nombre d'intervalles, Li correspond à une longueur de symboles d'entrée du décodeur pour un i-ème nombre d'intervalles, et Ln correspond à une longueur maximale de symboles d'entrée pour le décodeur.
  26. Procédé selon l'une quelconque des revendications 14 à 25, dans lequel les informations sont transmises sur des premier et deuxième canaux de commande multiplexés par répartition de code en utilisant l'une d'une pluralité de longueurs d'intervalle, comprenant les étapes de :
    la génération d'au moins un premier flux binaire en décodant des symboles d'au moins un nombre possible d'intervalles parmi une pluralité de nombres d'intervalles en fonction de résultats précédents par un premier décodeur (57) recevant des symboles par intervalle sur le premier canal de commande ;
    l'exécution d'un contrôle d'erreur sur le premier flux binaire ;
    la fourniture de symboles d'au moins un intervalle consécutif au premier décodeur jusqu'à la réussite du contrôle d'erreur, en cas d'échec du contrôle d'erreur sur le premier flux binaire ;
    l'acquisition d'une première information de commande avec un premier identifiant d'utilisateur du premier flux binaire correspondant au nombre détecté d'intervalles ;
    le décodage de symboles avec le nombre détecté d'intervalles pour générer un deuxième flux binaire par un deuxième décodeur recevant des symboles par intervalle sur le deuxième canal de commande, si le premier identifiant d'utilisateur n'est pas identique à son propre identifiant d'utilisateur ;
    l'exécution d'un contrôle d'erreur sur le deuxième flux binaire ; et
    l'acquisition d'une deuxième information de commande avec un deuxième identifiant d'utilisateur du deuxième flux binaire, en cas de réussite du contrôle d'erreur sur le deuxième flux binaire.
  27. Procédé selon la revendication 26, dans lequel si le deuxième identifiant d'utilisateur est identique à un propre identifiant d'utilisateur, alors un identifiant de canal de demande à répétition automatique, ARQ, une taille de paquet de codeur et un identifiant de sous-paquet pour la démodulation de données de paquet transmises de l'émetteur sont extraits de la première information de commande.
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CN1643859A (zh) 2005-07-20
US20030188252A1 (en) 2003-10-02
US7487430B2 (en) 2009-02-03
AU2003214677B2 (en) 2005-12-22
KR20030078033A (ko) 2003-10-04
KR100547822B1 (ko) 2006-01-31
WO2003081854A1 (fr) 2003-10-02
AU2003214677A1 (en) 2003-10-08
EP1349313A1 (fr) 2003-10-01

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