EP1346413A2 - Circuit - Google Patents

Circuit

Info

Publication number
EP1346413A2
EP1346413A2 EP01995582A EP01995582A EP1346413A2 EP 1346413 A2 EP1346413 A2 EP 1346413A2 EP 01995582 A EP01995582 A EP 01995582A EP 01995582 A EP01995582 A EP 01995582A EP 1346413 A2 EP1346413 A2 EP 1346413A2
Authority
EP
European Patent Office
Prior art keywords
substrate
arrangement according
circuit arrangement
circuit
sensor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01995582A
Other languages
German (de)
English (en)
Inventor
Andreas Kux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1346413A2 publication Critical patent/EP1346413A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L29/0657—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the invention relates to a circuit arrangement and a method for checking the authenticity of such a circuit arrangement.
  • Integrated circuits today have a large amount of data. If this data or the integrated circuits are used in security-relevant information systems, there is an increasing need to protect this data. This is the case, for example, in so-called e-commerce.
  • the invention is therefore based on the object of providing protection of an integrated circuit.
  • the second substrate is used to protect against unauthorized reading of data.
  • the second substrate can face both the front and the back of the chip to be protected. It can also be designed in duplicate and surround the chip to be protected like a sandwich.
  • the presence of the second substrate can be checked with high resolution.
  • the capacitive sensor elements are linked by means of a circuit arranged in a connection level, they can at least be easily read out individually.
  • a vertical connection to the integrated circuit If a vertical connection to the integrated circuit is provided, then signals detected by the sensor elements can be evaluated in the integrated circuit itself. In this way, the integrated circuit can check its protection itself.
  • a processing device must be provided within the integrated circuit. It is advantageous if the second surface has unevenness in order to be able to better determine the positional accuracy by means of the capacitive sensor elements. It is possible to level these bumps with an oxide in order to create a better connection.
  • an anisotropically conductive adhesive can be used instead of the unevenness or in combination with it, since this itself results in an individual pattern which, by means of the capacitive sensor elements with a high degree of positional accuracy uninterrupted connection of both substrates can be checked.
  • FIG. 1 a first exemplary embodiment according to the invention
  • FIG. 2 shows a modification of the first exemplary embodiment according to the invention
  • FIG. 3 a second exemplary embodiment according to the invention
  • FIG. 5 shows a block diagram to explain the basic functions according to the invention.
  • first substrate 1 such as a semiconductor chip, on whose first surface 2, opposite a second surface, an integrated circuit 4 is formed.
  • the second surface 2 again has unevenness 5.
  • these bumps 5 are depressions that are generated, for example, at random.
  • the unevenness 5 may have arisen, for example, during the normal manufacture of the substrate 1. However, they can also be created on the surface by irradiation with a laser beam, even in a random distribution.
  • the first surface 2 of the first substrate 1 is connected to a second substrate 9 by means of an adhesive 10.
  • a sensor is formed on the surface of the second substrate 9, which is formed from a plurality of sensor elements 7 in the exemplary embodiment shown.
  • These sensor elements are capacitive elements, that is to say on the surface of the second substrate 9, the capacitive elements are in the form of individual capacitor plates.
  • the second capacitor plate is replaced by the first Surface of the first substrate 1 is formed.
  • the individual sensor elements are charged with a different amount of charge at a predetermined voltage, or have different voltages after a uniformly predetermined charging process.
  • the capacitive sensor elements 7 which lie opposite an unevenness 5 are charged less than the capacitive sensor elements 7 which lie opposite the first surface 2 of the substrate 1 between the unevenness.
  • each arrangement according to FIG. 1 or FIG. 2 will differ from a basically identical arrangement in that the sensor elements 7 have different capacities and are therefore charged differently. Due to these differences, each corresponding arrangement will have an individual charge distribution on the capacitive element 7.
  • the capacitive sensor elements 7 are now connected to one another in a circuit arrangement which is formed in a connection level 8. In this way, the individual capacitive sensor elements 7 can be controlled or read out individually or in groups. This is shown in principle in FIG. 5.
  • the sensor 70 consists of a matrix of sensor elements 7, which are arranged at the intersections of row or row lines and which are addressed via the circuit 14. Access to the circuit 14 enables the individual capacity distribution of the charge distribution of the arrangement to be determined. Once it has been determined, it can be saved as desired and compared again at a later point in time.
  • the circuit 14 can be connected to the integrated circuit 4 via a vertical connection 6. If the integrated circuit 4 has a memory and processing logic, a pattern of the individual properties of the capacitive sensor elements 7, once stored, can be checked for changes at any time. It is thus possible, via the processing device 13, to control the integrated circuit 4 in such a way that it can only be operated as long as the individual distribution of the capacitive sensor elements 7 matches a distribution that was previously stored.
  • the first surface of the first substrate must be planarized.
  • a filler layer 11 is applied, for example, which fills the unevenness 5 and, as shown in FIG. 3, optionally covers the entire surface. This is a uniform level Surface can be manufactured. Otherwise, the arrangement according to this second exemplary embodiment is identical to the arrangements according to FIG. 1 and FIG. 2.
  • a flat first surface 2 of the first substrate 1 is generally assumed.
  • the first and the second substrate are connected to one another with the aid of an anisotropically conductive adhesive 12.
  • the anisotropically conductive adhesive 12 has conductive particles 12 'which are distributed in the adhesive material. In this way too, an individual pattern of the individual capacitive sensor elements 7 is generated, the anisotropically conductive adhesive 12 being used at the same time for connecting the circuit 14 for detecting the individual sensor elements to the vertical connection 6.
  • the sensor elements have a sufficiently fine grid to be able to produce the individuality in the arrangement.
  • the invention is not restricted to this. It is also possible to protect the side carrying an integrated circuit, or to monitor the chip to be protected on both sides with sensor elements like a sandwich. Furthermore, it is already known to stack a plurality of semiconductor chips carrying integrated circuits on top of one another and thus to combine the subcircuits in a cubic manner to form an overall circuit. Which he- The arrangement according to the invention can also be used to check the presence or the integrity of such a chip stack.
  • both the first and the second substrate can be produced in the semiconductor technology common today, such as silicon technology.
  • semiconductor technology common today such as silicon technology.
  • one or both substrates it is also possible for one or both substrates to be produced using the not yet widespread polymer technology.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Pressure Sensors (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

Selon l'invention, il es prévu de former, sur un second substrat, un ensemble capteur qui est placé de façon opposée à une surface d'un premier substrat. Ainsi, il est possible de constater si l'ensemble constitué du premier et du second substrat est ou a été divisé.
EP01995582A 2000-12-29 2001-12-06 Circuit Withdrawn EP1346413A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE2000165747 DE10065747A1 (de) 2000-12-29 2000-12-29 Schaltungsanordnung
DE10065747 2000-12-29
PCT/DE2001/004589 WO2002054492A2 (fr) 2000-12-29 2001-12-06 Circuit

Publications (1)

Publication Number Publication Date
EP1346413A2 true EP1346413A2 (fr) 2003-09-24

Family

ID=7669438

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01995582A Withdrawn EP1346413A2 (fr) 2000-12-29 2001-12-06 Circuit

Country Status (4)

Country Link
EP (1) EP1346413A2 (fr)
DE (1) DE10065747A1 (fr)
TW (1) TW544897B (fr)
WO (1) WO2002054492A2 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10238835A1 (de) * 2002-08-23 2004-03-11 Infineon Technologies Ag Halbleiterchip, Chipanordnung mit zumindest zwei Halbleiterchips und Verfahren zur Überprüfung der Ausrichtung zumindest zweier übereinander liegender Halbleiterchips in einer Chipanordnung
DE10309614A1 (de) * 2003-03-05 2004-09-23 Infineon Technologies Ag Halbleiterstruktur und Verfahren zur Herstellung derselben
US7758911B2 (en) * 2003-05-08 2010-07-20 Honeywell International Inc. Microelectronic security coatings
US7429915B2 (en) 2005-04-20 2008-09-30 Honeywell International Inc. System and method for detecting unauthorized access to electronic equipment or components
US7719419B2 (en) 2005-11-02 2010-05-18 Honeywell International Inc. Intrusion detection using pseudo-random binary sequences
US7388486B2 (en) 2006-01-05 2008-06-17 Honeywell International Inc. Method and system to detect tampering using light detector
US7436316B2 (en) 2006-01-05 2008-10-14 Honeywell International Inc. Method and system to detect tampering using light detector
US7495554B2 (en) 2006-01-11 2009-02-24 Honeywell International Inc. Clamshell protective encasement
US7671324B2 (en) 2006-09-27 2010-03-02 Honeywell International Inc. Anti-tamper enclosure system comprising a photosensitive sensor and optical medium
US7796036B2 (en) 2006-11-30 2010-09-14 Honeywell International Inc. Secure connector with integrated tamper sensors
US8279075B2 (en) 2006-11-30 2012-10-02 Honeywell International Inc. Card slot anti-tamper protection system
US8284387B2 (en) 2007-02-08 2012-10-09 Honeywell International Inc. Methods and systems for recognizing tamper events
EP3156947B1 (fr) 2015-10-12 2020-01-01 Nxp B.V. Dispositif électronique
EP3193281B1 (fr) 2016-01-15 2019-11-13 Nxp B.V. Dispositif électronique

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2727226B1 (fr) * 1994-11-17 1996-12-20 Schlumberger Ind Sa Dispositif de securite actif a memoire electronique
DE19511775C1 (de) * 1995-03-30 1996-10-17 Siemens Ag Trägermodul, insb. zum Einbau in einen kartenförmigen Datenträger, mit Schutz gegen die Untersuchung geheimer Bestandteile
FR2746962B1 (fr) * 1996-04-01 1998-04-30 Schlumberger Ind Sa Dispositif de securite d'une pastille semi-conductrice
TW381057B (en) * 1997-08-07 2000-02-01 Hitachi Ltd Semiconductor device
CA2254695A1 (fr) * 1997-12-19 1999-06-19 John M. Todd Alarme antivol pour appareils portatifs a commande electrique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO02054492A3 *

Also Published As

Publication number Publication date
WO2002054492A2 (fr) 2002-07-11
DE10065747A1 (de) 2002-07-11
TW544897B (en) 2003-08-01
WO2002054492A3 (fr) 2003-02-13

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