Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/861—Diodes
  • H01L29/8611—Planar PN junction diodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/861—Diodes
  • H01L29/8618—Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes

Definitions

• the present invention relates to new diac structures making it possible in particular to facilitate the mounting of these components.
• Oe conventional diac structure is shown in Figure 1.
• the structure is formed from a substrate 1 of a first type of conductivity, here type P.
• On both sides of the substrate are formed heavily doped regions opposite type, here type N, respectively 2 and 3.
• mesa technology is used, which consists in etching grooves at the border between two diacs formed in the same wafer.
• the angle formed by the groove at the point where it intersects the junction between the regions P and N + constitutes an important parameter for determining the breakdown voltage at the periphery of the component.
• Another important parameter is the choice of the passivation product 4 formed in the grooves.
• a diac is a small device, its thickness being less than 0.3 mm and its surface being of the order of 0.5 mm X 0.5 mm. Special boxes are therefore provided for these diacs, for example piston systems arranged on either side of a glass tube in which the chip is enclosed.
• planar type diacs for example such as that shown in FIG. 2, also made from a P type substrate 1.
• a masking layer for example made of silicon oxide, respectively 11 and 12, provided with a central opening through which a diffused region of type N + , respectively 13 and 14 is formed
• These planar structures make it possible to obtain satisfactory breakdown voltages at the junction peripheries but pose mounting problems.
• it becomes difficult to solder the chip on a metal support plate because, in the event that the solder overflows laterally, a short circuit is created between one of the N + regions and the substrate P. It is therefore necessary to provide metallizations, consisting for example of silver beads 15 and 16, located on the regions N + 13 and 14, which complicates the assembly and increases its cost.
• Figure 3 recalls the typical characteristic of a diac. Such a component cannot be compared to two head-to-tail Zener diodes. In fact, the existence, when one of the junctions is in an avalanche, of another direct junction which injects into the substrate produces a reversal-type effect. Thus, the diac breaks down when the voltage across its terminals reaches a VBO value. The voltage then drops to an intermediate voltage Vf as long as the current is within a certain range of values. The voltage across the diac goes up if the current goes out of this range. In the example shown in FIG.
• the value of the voltage VBO is 32 volts
• the value of the voltage Vf is 13 volts
• the current at the time of the reversal is of the order of 0.3 ⁇ A (that is to say that the diac has very low leaks)
• the current corresponding to the voltage Vf is situated in a range of the order of 10 to 100 ⁇ lliamps.
• a diac such as those shown in Figures 1 and 2, has a symmetrical characteristic, as shown in Figure 3.
• the value of the voltage VBO depends essentially on the doping levels at the junctions between the N + regions and the substrate P.
• the value of the direct voltage Vf essentially depends on the doping level and the thickness of the substrate 1, which can be considered as the floating base of a transistor whose emitter and collector correspond to the N + regions. This base must be such that the carriers injected by the direct junction can cross it. It is therefore necessary that the lifetime of the carriers is long in the base if its width is large, that is to say that it is lightly doped. If the size of the base becomes smaller, the life of the carriers in this base must be reduced, for example by metallic diffusion.
• An object of the present invention is to produce such a diac which is easy to manufacture, that is to say which is of the planar type and not of the mesa type, and which it is possible to easily mount on a grid. connection comprising a base on which a face of the component is welded.
• the present invention provides an asymmetric diac comprising a substrate of a first type of conductivity with high doping level, a lightly doped epitaxial layer of the second type of conductivity on the upper surface of the substrate, a heavily doped region of the first conductivity type on the side of the upper face of the epitaxial layer, a region of the second type of conductivity more doped than the epitaxial layer under the region of the first type of conductivity and not overflowing with respect thereto, a ring of channel stop of the second type of conductivity more doped than the epitaxial layer, outside the first region, and a wall of the first type of conductivity outside of said ring, joining the substrate.
• the first type of conductivity is the N type.
• the present invention also provides an assembly constituting a symmetrical diac comprising two asymmetrical diacs as mentioned above, in antiparallel.
• the assembly comprises a first diac welded by its rear face to a first conductive plate, a second diac welded by its rear face to a second conductive plate, the upper face of each of the diacs being welded to the conductive plate carrying the other diac.
• FIG. 2 represents a planar type diac structure according to the prior art
• Figure 3 shows the current / voltage characteristic of a diac
• Figure 4 is a schematic sectional view of a diac structure according to the present invention
• FIG. 5 represents the current / voltage characteristic of a diac according to the present invention
• FIG. 6 illustrates the assembly diagram of a diac according to the present invention
• FIG. 7 represents an assembly of diacs in antiparallel according to the present invention
• FIG. 8 represents a diffusion profile of an exemplary embodiment of a diac according to the invention.
• the present invention provides for forming a diac on a structure comprising a substrate 21 highly doped with a first type of conductivity, which will be considered hereinafter as type N.
• a layer epitaxial 22 of type P is formed in the epitaxial layer 22 in the epitaxial layer 22 .
• a region 23 more heavily doped than region 22 through a first mask.
• an N-type region 24 overflowing on all sides with respect to region 23 and more heavily doped than this region 23.
• a P-type ring 25 which has the function of a stop ring of channel.
• the periphery of the component is occupied by a heavily doped N-type wall 26 which crosses the epitaxial layer 22 and joins the substrate 21.
• the wall 26 is external to and is separated from the ring 25. This wall is formed immediately after the epitaxial layer 22.
• a metallization Ml is formed on the upper face of the region N + 24 and a metallization M2 is formed on the lower face of the substrate N + 21. Thus, a diac is obtained between the metallizations Ml and M2.
• the role of the channel stop region 25 is to prevent leakage currents from flowing in a region situated under the upper surface of the epitaxial layer 22 from the metallization Ml to the metallization M2 via the wall 26 and the substrate 21.
• the role of the wall 26 is to prevent the junction between the substrate 21 and the epitaxial layer 22 from opening onto the outside of the component.
• the first junction of the diac corresponds to the junction between the N + 24 region and the P region 23, and the second junction of the diac corresponds to the junction between the epitaxial layer 22 and the substrate 21.
• the structure of this diac means that the metallization M2 can be welded to a metal base possibly forming part of a connection grid. Indeed, even if weld overflows occur laterally, these, if they go up on the walls of the diac, cannot create short-circuits since the side walls are uniformly of type N + like the layer in contact with metallization M2.
• the diac according to the invention has an asymmetrical characteristic.
• the breakdown voltage of the junction located on the side of the upper face is lower than the breakdown voltage of the junction located on the side of the lower face. This is due to the fact that the region P 23 which fixes with the region N + 24 the positive avalanche voltage (taking as reference the metallization M2) is more doped than the epitaxial layer P 22 which fixes with the region N + 21 negative breakdown voltage (always taking M2 metallization as a reference).
• Such an asymmetric diac can have advantages in certain types of applications.
• FIG. 8 illustrates an example of the doping profile of a diac according to the invention having a characteristic as shown in FIG. 5.
• the abscissa corresponds to vertical distances in micrometers, the value "0" corresponding to the upper face of the N + substrate on which the epitaxial layer of type P is developed.
• the profile of this epitaxial layer corresponds to what is indicated by the reference 41.
• an N + type region of the substrate 21 diffuses along the curve designated by the reference 42.
• the curve 43 corresponds to the P type diffusion formed from the upper face, and the curve 44 corresponds to the N + 24 type diffusion formed from the upper face.
• the N + type layer 24 extends approximately 5 ⁇ m below the upper surface of the epitaxial layer, and the whole of the P type region 23 and of the P type layer 22 extends up to at approximately 12 ⁇ m from the surface of the epitaxial layer.
• the doping level of the P-type layer 22 at the junction with the substrate 21 is approximately 2.10 15 atoms / cm? and the doping level of the P type layer 23 at the interface with the N + type region 24 is of the order of 8.10 17 atoms / cm 3 .
• the doping profile of FIG. 8 is only an example and the various doping levels can be optimized as a function of the desired characteristics of the diac.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Electrodes Of Semiconductors (AREA)
• Thyristors (AREA)

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• 2000
  • 2000-10-13 FR FR0013180A patent/FR2815472B1/fr not_active Expired - Fee Related
• 2001
  • 2001-10-12 EP EP01976431A patent/EP1328980A1/de not_active Withdrawn
  • 2001-10-12 WO PCT/FR2001/003179 patent/WO2002031889A1/fr active Application Filing
  • 2001-10-12 US US10/398,419 patent/US7321138B2/en not_active Expired - Lifetime
  • 2001-10-12 CN CNB018172679A patent/CN1220275C/zh not_active Expired - Fee Related

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