Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
  • H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
  • H03J1/0008—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
  • H04N5/50—Tuning indicators; Automatic tuning control
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
  • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
  • H04N21/41—Structure of client; Structure of client peripherals
  • H04N21/426—Internal components of the client ; Characteristics thereof
  • H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
  • H04N21/4263—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners

Definitions

• the invention generally relates to television receivers and, more particularly, to tuners used in television receivers.
• television receiver herein includes any television signal receiver with or without display.
• Tuners are used in television receivers such as television sets, video cassette recorders, home entertainment systems, and the like.
• the tuners are implemented as either discrete tuner modules or as onboard tuner circuits integrated into a chassis ("tuner- on-board"). Both discrete tuner modules and onboard tuner circuits often include phase lock loop (PLU circuits that facilitate reception of television signals.
• PLU circuits phase lock loop
• FIG. 1 depicts a portion of a prior art television chassis 100 that is conventionally found in a television receiver.
• the television chassis 100 comprises a tuner 104 having a phase lock loop 106 and a microprocessor 108 having an on-chip memory 110.
• the tuner 104 is coupled to the microprocessor 108 via a communications bus 114, e.g., an inter-integrated circuit (I2C) bus.
• the input port 102 for the television chassis 100 is coupled to an antenna, a cable feed or the like.
• the tuner 104 is typically a single conversion tuner, although a double conversion tuner may be used.
• the selection of a channel to receive by the television receiver is performed by the microprocessor 08 instructing the tuner 104 and the phase lock loop 106 to tune to a particular channel for reception.
• the tuner parameters 112 that are used to control the phase lock loop 106 are generally stored within an on-chip memory 110. That is, a tuner's parameters are "hard coded" in the memory that is embedded in the microprocessor. As such, if the tuner 104 is a module that is manufactured separately from the television chassis, the tuner functionality must be well matched from tuner-to- tuner so that the same tuner parameters can be stored in the on-chip memory 110 in a hard coded manner for all tuner modules.
• Electronic tuner control is a process whereby control data
• the tuner parameters for a particular tuner are stored in nonvolatile memory (on-chip memory 110) within the microprocessor 108.
• the microprocessor 108 within the television receiver chassis 100 identifies (looks up) the control data stored in the nonvolatile memory 110 for the desired channel. The control data is then communicated to the television tuner 104.
• Tuner manufacturers use a variety of phase-locked loop (PLU integrated circuits (iCs) in their tuner designs.
• PLL ic is used to adjust the operating frequency of the tuner and thereby cause the television to receive the desired television channel. Since the frequency range to be covered spans over 700 MHz, the PLL achieves broad band tuning by dividing this frequency range into convenient sections - typically three or four. These sections are known as bands, e.g., VHF low, VHF high and VHF.
• the division of the covered frequency range is arbitrary and varies between tuner designs.
• This frequency range information for each band in the tuner forms part of the control data that is stored in nonvolatile memory 110.
• the stored control data also contains instructions that direct the PLL to synthesize the desired frequency and the mode of operation of that particular PLL IC
• the control data controls the PLL for the selected channel, and controls various switch circuits within the tuner, i.e., VHF low, VHF high and UHF band selections. While electronic control eases the design requirements, it narrows compatibility among television receiver components.
• the microprocessor 108 must contain specific routines for selecting and communicating the control data from the on-chip memory 110 to the tuner 104.
• the tuner 104 must be adapted to accept the data and compensate for mismatches.
• the tuner parameters that are to be stored in the on- chip memory varies from tuner-to-tuner.
• the on-chip memory must be specially programmed with different data for each and every tuner type that is supplied from a different manufacturer for the television chassis. Since on-chip memory storage is of a limited size, it is not practical to store tuner parameters for every type of tuner that can be used with a television chassis. As such, a single set of parameters is stored for a particular tuner in the on-chip memory 110. Thus, a faulty tuner can not be replaced without replacing the microprocessor 108.
• the present invention is a television chassis comprising a tuner, a microprocessor, a communications bus and a replaceable nonvolatile memory, e.g., an electrically erasable programmable read only memory (EEPROM).
• the replaceable nonvolatile memory is programmed to contain the tuner control parameters for a tuner at the time of chassis manufacture, allowing for quick adjustment to a change in the tuner type.
• the memory can be programmed for a tuner such that on the manufacturing floor the tuner from each manufacturer is supplied with matching control parameters for the television chassis that the tuner is going to be placed within.
• the tuner parameters are recalled by the microprocessor and used to facilitate electronic control of the tuner and phase lock loop in a conventional manner, while using a separate programmable memory to store the tuner parameters, the invention avoids the problem of having to program an on-chip memory within the microprocessor for each and every type of tuner module that is used in the television chassis.
• FIG. 1 depicts a portion of a block diagram of a prior art television chassis
• FIG. 2 depicts a portion of a block diagram of a television chassis in accordance with the present invention. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
• This disclosure involves a television tuner in which a rewritable memory is used in conjunction with a microprocessor to facilitate tuning of the tuner.
• the rewritable memory stores the tuner control parameters for a phase lock loop within the tuner.
• FIG. 2 depicts a block diagram of one embodiment of a television chassis 200 in accordance with the invention.
• the television chassis 200 comprises an input port 102 for receiving RF signals, e.g., television signals, a tuner 104 having a phase lock loop 106, a microprocessor 108 having on-chip memory 110, and a rewritable memory 202 for storing tuner parameters 112.
• the tuner 104 is coupled through a communications bus 114 to a tuner control system 204 comprising the microprocessor 108 and memory 202.
• the tuner receives television signals through the port 102 that is typically connected to a cable, a digital video disk, a video cassette recorder, or any other source of television signals.
• the tuner module 104 selects an RF signal corresponding to desired television channels selected from a plurality of channel locations in a frequency band provided by the RF source.
• the RF signals associated with television channels may be analog and/or digital television signals.
• the analog television signal may comprise a conventional National Television standard Committee (NTSC) modulated signal within the united states.
• the digital television signal may comprise a vestigial side band (VSB) modulated signal in compliance with the Advanced Television systems Committee (ATSC) standard A/53, for example, a high definition television (HDTV) signal.
• ATSC Advanced Television systems Committee
• HDTV high definition television
• the tuner module 104 selects the desired television channel to be displayed on a display pursuant to a tuning command generated by the microprocessor 108.
• the microprocessor 108 is coupled to the tuner module 104 via the communications bus 114.
• the communications bus 114 may be an inter-integrated circuit (I2C) bus, a three wire bus or any type of communications bus.
• I2C inter-integrated circuit
• the microprocessor recalls the tuner parameters 112 from the memory 202 for use with tuner module 104. These tuner parameters 112 are passed through the communications bus 114 to the phase lock loop 106 within the tuner module 104.
• Memory 202 is rewritable type memory of a nonvolatile nature that may include, but is not limited to, read only memory (ROM) or programmable read only memory (PROM), the latter of which may be subdivided into an electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) and one time PROM (OTPROM).
• ROM read only memory
• PROM programmable read only memory
• the memory 202 is simultaneously programmed with a plurality of other memories using "bulk" programming techniques prior to installing the memory 202 in the chassis 200.
• Electronically programmable memory may be programmed with the correct tuner control information during chassis manufacture.
• the control data 112 comprises digital information necessary to for the tuner PLL 106 to synthesize the correct frequency for receiving selected television signals.
• the tuner module 104 is electronically tuned to provide the correct frequency and best performance for the desired television channel.
• the tuner module 104 contains all necessary data for tuner control after that tuner parameters are passed from the microprocessor to the phase lock loop 106 to facilitate tuner control.
• the tuner module 104 is a discrete component within the television chassis 200 which allows, for example, the replacement of the tuner module 104 in the field without changing the television control system 204, specifically, the microprocessor 102. when using the invention, the tuner module 104 can be changed with a matched memory 202 to facilitate changing the tuner parameters 112 to match the new tuner 104.

Landscapes

• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Circuits Of Receivers In General (AREA)
• Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=22784725

Family Applications (1)

Country Status (7)

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Family Cites Families (5)

• 2001
  • 2001-06-05 KR KR1020027016588A patent/KR20030010665A/ko not_active Application Discontinuation
  • 2001-06-05 CN CNB018108768A patent/CN1208954C/zh not_active Expired - Fee Related
  • 2001-06-05 AU AU2001275245A patent/AU2001275245A1/en not_active Abandoned
  • 2001-06-05 WO PCT/US2001/018143 patent/WO2001097512A2/en active Application Filing
  • 2001-06-05 MX MXPA02012130A patent/MXPA02012130A/es active IP Right Grant
  • 2001-06-05 EP EP01941934A patent/EP1287689A2/de not_active Withdrawn
  • 2001-06-05 JP JP2002511105A patent/JP2004507911A/ja not_active Withdrawn

Non-Patent Citations (1)

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