EP1287689A2 - Apparatus for providing tuner parameters in a television receiver - Google Patents

Apparatus for providing tuner parameters in a television receiver

Info

Publication number
EP1287689A2
EP1287689A2 EP01941934A EP01941934A EP1287689A2 EP 1287689 A2 EP1287689 A2 EP 1287689A2 EP 01941934 A EP01941934 A EP 01941934A EP 01941934 A EP01941934 A EP 01941934A EP 1287689 A2 EP1287689 A2 EP 1287689A2
Authority
EP
European Patent Office
Prior art keywords
tuner
memory
television receiver
television
parameters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01941934A
Other languages
German (de)
French (fr)
Inventor
Feroz Kaiki Alpaiwalla
Edward Allen Hall
Eugene Murphy O'donnell
Edward Charles Maexner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
THOMSON LICENSING
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of EP1287689A2 publication Critical patent/EP1287689A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
    • H03J1/0008—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/50—Tuning indicators; Automatic tuning control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
    • H04N21/4263—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners

Definitions

  • the invention generally relates to television receivers and, more particularly, to tuners used in television receivers.
  • television receiver herein includes any television signal receiver with or without display.
  • Tuners are used in television receivers such as television sets, video cassette recorders, home entertainment systems, and the like.
  • the tuners are implemented as either discrete tuner modules or as onboard tuner circuits integrated into a chassis ("tuner- on-board"). Both discrete tuner modules and onboard tuner circuits often include phase lock loop (PLU circuits that facilitate reception of television signals.
  • PLU circuits phase lock loop
  • FIG. 1 depicts a portion of a prior art television chassis 100 that is conventionally found in a television receiver.
  • the television chassis 100 comprises a tuner 104 having a phase lock loop 106 and a microprocessor 108 having an on-chip memory 110.
  • the tuner 104 is coupled to the microprocessor 108 via a communications bus 114, e.g., an inter-integrated circuit (I2C) bus.
  • the input port 102 for the television chassis 100 is coupled to an antenna, a cable feed or the like.
  • the tuner 104 is typically a single conversion tuner, although a double conversion tuner may be used.
  • the selection of a channel to receive by the television receiver is performed by the microprocessor 08 instructing the tuner 104 and the phase lock loop 106 to tune to a particular channel for reception.
  • the tuner parameters 112 that are used to control the phase lock loop 106 are generally stored within an on-chip memory 110. That is, a tuner's parameters are "hard coded" in the memory that is embedded in the microprocessor. As such, if the tuner 104 is a module that is manufactured separately from the television chassis, the tuner functionality must be well matched from tuner-to- tuner so that the same tuner parameters can be stored in the on-chip memory 110 in a hard coded manner for all tuner modules.
  • Electronic tuner control is a process whereby control data
  • the tuner parameters for a particular tuner are stored in nonvolatile memory (on-chip memory 110) within the microprocessor 108.
  • the microprocessor 108 within the television receiver chassis 100 identifies (looks up) the control data stored in the nonvolatile memory 110 for the desired channel. The control data is then communicated to the television tuner 104.
  • Tuner manufacturers use a variety of phase-locked loop (PLU integrated circuits (iCs) in their tuner designs.
  • PLL ic is used to adjust the operating frequency of the tuner and thereby cause the television to receive the desired television channel. Since the frequency range to be covered spans over 700 MHz, the PLL achieves broad band tuning by dividing this frequency range into convenient sections - typically three or four. These sections are known as bands, e.g., VHF low, VHF high and VHF.
  • the division of the covered frequency range is arbitrary and varies between tuner designs.
  • This frequency range information for each band in the tuner forms part of the control data that is stored in nonvolatile memory 110.
  • the stored control data also contains instructions that direct the PLL to synthesize the desired frequency and the mode of operation of that particular PLL IC
  • the control data controls the PLL for the selected channel, and controls various switch circuits within the tuner, i.e., VHF low, VHF high and UHF band selections. While electronic control eases the design requirements, it narrows compatibility among television receiver components.
  • the microprocessor 108 must contain specific routines for selecting and communicating the control data from the on-chip memory 110 to the tuner 104.
  • the tuner 104 must be adapted to accept the data and compensate for mismatches.
  • the tuner parameters that are to be stored in the on- chip memory varies from tuner-to-tuner.
  • the on-chip memory must be specially programmed with different data for each and every tuner type that is supplied from a different manufacturer for the television chassis. Since on-chip memory storage is of a limited size, it is not practical to store tuner parameters for every type of tuner that can be used with a television chassis. As such, a single set of parameters is stored for a particular tuner in the on-chip memory 110. Thus, a faulty tuner can not be replaced without replacing the microprocessor 108.
  • the present invention is a television chassis comprising a tuner, a microprocessor, a communications bus and a replaceable nonvolatile memory, e.g., an electrically erasable programmable read only memory (EEPROM).
  • the replaceable nonvolatile memory is programmed to contain the tuner control parameters for a tuner at the time of chassis manufacture, allowing for quick adjustment to a change in the tuner type.
  • the memory can be programmed for a tuner such that on the manufacturing floor the tuner from each manufacturer is supplied with matching control parameters for the television chassis that the tuner is going to be placed within.
  • the tuner parameters are recalled by the microprocessor and used to facilitate electronic control of the tuner and phase lock loop in a conventional manner, while using a separate programmable memory to store the tuner parameters, the invention avoids the problem of having to program an on-chip memory within the microprocessor for each and every type of tuner module that is used in the television chassis.
  • FIG. 1 depicts a portion of a block diagram of a prior art television chassis
  • FIG. 2 depicts a portion of a block diagram of a television chassis in accordance with the present invention. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
  • This disclosure involves a television tuner in which a rewritable memory is used in conjunction with a microprocessor to facilitate tuning of the tuner.
  • the rewritable memory stores the tuner control parameters for a phase lock loop within the tuner.
  • FIG. 2 depicts a block diagram of one embodiment of a television chassis 200 in accordance with the invention.
  • the television chassis 200 comprises an input port 102 for receiving RF signals, e.g., television signals, a tuner 104 having a phase lock loop 106, a microprocessor 108 having on-chip memory 110, and a rewritable memory 202 for storing tuner parameters 112.
  • the tuner 104 is coupled through a communications bus 114 to a tuner control system 204 comprising the microprocessor 108 and memory 202.
  • the tuner receives television signals through the port 102 that is typically connected to a cable, a digital video disk, a video cassette recorder, or any other source of television signals.
  • the tuner module 104 selects an RF signal corresponding to desired television channels selected from a plurality of channel locations in a frequency band provided by the RF source.
  • the RF signals associated with television channels may be analog and/or digital television signals.
  • the analog television signal may comprise a conventional National Television standard Committee (NTSC) modulated signal within the united states.
  • the digital television signal may comprise a vestigial side band (VSB) modulated signal in compliance with the Advanced Television systems Committee (ATSC) standard A/53, for example, a high definition television (HDTV) signal.
  • ATSC Advanced Television systems Committee
  • HDTV high definition television
  • the tuner module 104 selects the desired television channel to be displayed on a display pursuant to a tuning command generated by the microprocessor 108.
  • the microprocessor 108 is coupled to the tuner module 104 via the communications bus 114.
  • the communications bus 114 may be an inter-integrated circuit (I2C) bus, a three wire bus or any type of communications bus.
  • I2C inter-integrated circuit
  • the microprocessor recalls the tuner parameters 112 from the memory 202 for use with tuner module 104. These tuner parameters 112 are passed through the communications bus 114 to the phase lock loop 106 within the tuner module 104.
  • Memory 202 is rewritable type memory of a nonvolatile nature that may include, but is not limited to, read only memory (ROM) or programmable read only memory (PROM), the latter of which may be subdivided into an electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) and one time PROM (OTPROM).
  • ROM read only memory
  • PROM programmable read only memory
  • the memory 202 is simultaneously programmed with a plurality of other memories using "bulk" programming techniques prior to installing the memory 202 in the chassis 200.
  • Electronically programmable memory may be programmed with the correct tuner control information during chassis manufacture.
  • the control data 112 comprises digital information necessary to for the tuner PLL 106 to synthesize the correct frequency for receiving selected television signals.
  • the tuner module 104 is electronically tuned to provide the correct frequency and best performance for the desired television channel.
  • the tuner module 104 contains all necessary data for tuner control after that tuner parameters are passed from the microprocessor to the phase lock loop 106 to facilitate tuner control.
  • the tuner module 104 is a discrete component within the television chassis 200 which allows, for example, the replacement of the tuner module 104 in the field without changing the television control system 204, specifically, the microprocessor 102. when using the invention, the tuner module 104 can be changed with a matched memory 202 to facilitate changing the tuner parameters 112 to match the new tuner 104.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Circuits Of Receivers In General (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

A television receiver comprising a tuner (104), a microprocessor (108), a communications bus (114) and a rewritable memory (202), e.g., an electrically erasable programmable read only memory (EEPROM). The memory is programmed to contain the tuner parameters (112) for a tuner. The memory can be programmed to be matched with a tuner such that, on the manufacturing floor, the tuner from each manufacturer is supplied with a matched memory for the television chassis that the tuner and memory are going to be placed within. The tuner parameters are recalled by the microprocessor and used to facilitate tuning of the tuner in a conventional manner.

Description

APPARATUS FOR PROVIDING TUNER PARAMETERS IN A TELEVISION RECEIVER
The invention generally relates to television receivers and, more particularly, to tuners used in television receivers. The term "television receiver" herein includes any television signal receiver with or without display.
Television tuners are used in television receivers such as television sets, video cassette recorders, home entertainment systems, and the like. The tuners are implemented as either discrete tuner modules or as onboard tuner circuits integrated into a chassis ("tuner- on-board"). Both discrete tuner modules and onboard tuner circuits often include phase lock loop (PLU circuits that facilitate reception of television signals.
FIG. 1 depicts a portion of a prior art television chassis 100 that is conventionally found in a television receiver. The television chassis 100 comprises a tuner 104 having a phase lock loop 106 and a microprocessor 108 having an on-chip memory 110. The tuner 104 is coupled to the microprocessor 108 via a communications bus 114, e.g., an inter-integrated circuit (I2C) bus. The input port 102 for the television chassis 100 is coupled to an antenna, a cable feed or the like. The tuner 104 is typically a single conversion tuner, although a double conversion tuner may be used. The selection of a channel to receive by the television receiver is performed by the microprocessor 08 instructing the tuner 104 and the phase lock loop 106 to tune to a particular channel for reception. The tuner parameters 112 that are used to control the phase lock loop 106 are generally stored within an on-chip memory 110. That is, a tuner's parameters are "hard coded" in the memory that is embedded in the microprocessor. As such, if the tuner 104 is a module that is manufactured separately from the television chassis, the tuner functionality must be well matched from tuner-to- tuner so that the same tuner parameters can be stored in the on-chip memory 110 in a hard coded manner for all tuner modules. Electronic tuner control is a process whereby control data
(also referred to herein as the tuner parameters) for a particular tuner are stored in nonvolatile memory (on-chip memory 110) within the microprocessor 108. When a user selects a desired channel, the microprocessor 108 within the television receiver chassis 100 identifies (looks up) the control data stored in the nonvolatile memory 110 for the desired channel. The control data is then communicated to the television tuner 104.
Tuner manufacturers use a variety of phase-locked loop (PLU integrated circuits (iCs) in their tuner designs. The PLL ic is used to adjust the operating frequency of the tuner and thereby cause the television to receive the desired television channel. Since the frequency range to be covered spans over 700 MHz, the PLL achieves broad band tuning by dividing this frequency range into convenient sections - typically three or four. These sections are known as bands, e.g., VHF low, VHF high and VHF.
The division of the covered frequency range is arbitrary and varies between tuner designs. This frequency range information for each band in the tuner forms part of the control data that is stored in nonvolatile memory 110. The stored control data also contains instructions that direct the PLL to synthesize the desired frequency and the mode of operation of that particular PLL IC The control data controls the PLL for the selected channel, and controls various switch circuits within the tuner, i.e., VHF low, VHF high and UHF band selections. While electronic control eases the design requirements, it narrows compatibility among television receiver components. The microprocessor 108 must contain specific routines for selecting and communicating the control data from the on-chip memory 110 to the tuner 104. The tuner 104 must be adapted to accept the data and compensate for mismatches. As such, replacement of malfunctioning television tuners in the field requires finding a new television tuner that is adapted to be controlled by a particular microprocessor and a particular set of tuner parameters. When discrete tuner modules are utilized within the television chassis and those modules are manufactured by various tuner manufacturers, the tuner parameters that are to be stored in the on- chip memory varies from tuner-to-tuner. As such, the on-chip memory must be specially programmed with different data for each and every tuner type that is supplied from a different manufacturer for the television chassis. Since on-chip memory storage is of a limited size, it is not practical to store tuner parameters for every type of tuner that can be used with a television chassis. As such, a single set of parameters is stored for a particular tuner in the on-chip memory 110. Thus, a faulty tuner can not be replaced without replacing the microprocessor 108.
Therefore, the need exists in the art for a method and apparatus for flexibly storing tuner parameters within a television chassis
The present invention is a television chassis comprising a tuner, a microprocessor, a communications bus and a replaceable nonvolatile memory, e.g., an electrically erasable programmable read only memory (EEPROM). The replaceable nonvolatile memory is programmed to contain the tuner control parameters for a tuner at the time of chassis manufacture, allowing for quick adjustment to a change in the tuner type. The memory can be programmed for a tuner such that on the manufacturing floor the tuner from each manufacturer is supplied with matching control parameters for the television chassis that the tuner is going to be placed within. Once the television is assembled, the tuner parameters are recalled by the microprocessor and used to facilitate electronic control of the tuner and phase lock loop in a conventional manner, while using a separate programmable memory to store the tuner parameters, the invention avoids the problem of having to program an on-chip memory within the microprocessor for each and every type of tuner module that is used in the television chassis.
So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. it is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
FIG. 1 depicts a portion of a block diagram of a prior art television chassis; and
FIG. 2 depicts a portion of a block diagram of a television chassis in accordance with the present invention. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
After considering the following description, those skilled in the art will clearly realize that the teachings of this invention can be readily utilized in a television receiver. This disclosure involves a television tuner in which a rewritable memory is used in conjunction with a microprocessor to facilitate tuning of the tuner. The rewritable memory stores the tuner control parameters for a phase lock loop within the tuner.
FIG. 2 depicts a block diagram of one embodiment of a television chassis 200 in accordance with the invention. The television chassis 200 comprises an input port 102 for receiving RF signals, e.g., television signals, a tuner 104 having a phase lock loop 106, a microprocessor 108 having on-chip memory 110, and a rewritable memory 202 for storing tuner parameters 112. The tuner 104 is coupled through a communications bus 114 to a tuner control system 204 comprising the microprocessor 108 and memory 202. The tuner receives television signals through the port 102 that is typically connected to a cable, a digital video disk, a video cassette recorder, or any other source of television signals.
The tuner module 104 selects an RF signal corresponding to desired television channels selected from a plurality of channel locations in a frequency band provided by the RF source. The RF signals associated with television channels may be analog and/or digital television signals. The analog television signal may comprise a conventional National Television standard Committee (NTSC) modulated signal within the united states. The digital television signal may comprise a vestigial side band (VSB) modulated signal in compliance with the Advanced Television systems Committee (ATSC) standard A/53, for example, a high definition television (HDTV) signal. The system described herein could also be configured to function with other formats, such as European, by appropriate changes in the television control system 204. The tuner module 104 selects the desired television channel to be displayed on a display pursuant to a tuning command generated by the microprocessor 108. The microprocessor 108 is coupled to the tuner module 104 via the communications bus 114. in this embodiment, the communications bus 114 may be an inter-integrated circuit (I2C) bus, a three wire bus or any type of communications bus. in addition to a tuning command generated by the microprocessor 108, the microprocessor recalls the tuner parameters 112 from the memory 202 for use with tuner module 104. These tuner parameters 112 are passed through the communications bus 114 to the phase lock loop 106 within the tuner module 104.
Memory 202 is rewritable type memory of a nonvolatile nature that may include, but is not limited to, read only memory (ROM) or programmable read only memory (PROM), the latter of which may be subdivided into an electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) and one time PROM (OTPROM). The memory 202 is simultaneously programmed with a plurality of other memories using "bulk" programming techniques prior to installing the memory 202 in the chassis 200. Electronically programmable memory may be programmed with the correct tuner control information during chassis manufacture. The control data 112 comprises digital information necessary to for the tuner PLL 106 to synthesize the correct frequency for receiving selected television signals. in this manner, the tuner module 104 is electronically tuned to provide the correct frequency and best performance for the desired television channel. The tuner module 104 contains all necessary data for tuner control after that tuner parameters are passed from the microprocessor to the phase lock loop 106 to facilitate tuner control. As such, the tuner module 104 is a discrete component within the television chassis 200 which allows, for example, the replacement of the tuner module 104 in the field without changing the television control system 204, specifically, the microprocessor 102. when using the invention, the tuner module 104 can be changed with a matched memory 202 to facilitate changing the tuner parameters 112 to match the new tuner 104.
Although various embodiments that incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings. For example, the disclosed invention can be used for FM broadcast radio receivers.

Claims

1. A television receiver comprising: a tuner (104); a microprocessor (108); a rewritable memory (202), located external to said microprocessor (108) and coupled to said microprocessor (108), for storing tuner parameters (112); and a communications bus (114) connecting said microprocessor (108) to said tuner (104), where during television channel selection at least one tuner parameter is transferred from said rewritable memory (202) to said tuner (104).
2. The television receiver of claim 1 wherein said rewritable memory (202) includes a programmable read only memory.
3. The television receiver of claim 2 wherein said programmable read only memory (202) includes an electrically erasable programmable read only memory.
4. The television receiver of claim 1 wherein said rewritable memory (202) is removable.
5. The television receiver of claim 1 wherein said tuner parameters (112) are matched to said tuner (104).
6. The television receiver of claim 1 wherein said tuner (104) includes a phase lock loop (106) and said tuner parameters (112) includes phase lock loop control data.
7. The television receiver of claim 6 wherein said control data includes signal band switching information.
8. A television receiver comprising: tuning means (104); control means (108); memory means (202), located external to said control means (108) and coupled to said control means (108), for storing tuning parameters (112); and a communications path (114) connecting said control means (108) to said tuning means (104), where during television channel selection at least one tuning parameter is transferred from said memory means (202) to said tuning means (104).
9. The television receiver of claim 8 wherein said memory means (202) includes a programmable read only memory.
10. The television receiver of claim 3 wherein said programmable read only memory (202) includes an electrically erasable programmable read only memory.
11. The television receiver of claim 8 wherein said memory means (202) is removable.
12. The television receiver of claim 8 wherein said tuning parameters (112) are matched to said tuning means (104).
13. The television receiver of claim 8 wherein said tuning means (104) includes a phase lock loop (106) and said tuning parameters (112) includes phase lock loop control data.
14. The television receiver of claim 13 wherein said control data includes signal band switching information.
EP01941934A 2000-06-09 2001-06-05 Apparatus for providing tuner parameters in a television receiver Withdrawn EP1287689A2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US21089300P 2000-06-09 2000-06-09
US210893P 2000-06-09
PCT/US2001/018143 WO2001097512A2 (en) 2000-06-09 2001-06-05 Apparatus for providing tuner parameters in a television receiver

Publications (1)

Publication Number Publication Date
EP1287689A2 true EP1287689A2 (en) 2003-03-05

Family

ID=22784725

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01941934A Withdrawn EP1287689A2 (en) 2000-06-09 2001-06-05 Apparatus for providing tuner parameters in a television receiver

Country Status (7)

Country Link
EP (1) EP1287689A2 (en)
JP (1) JP2004507911A (en)
KR (1) KR20030010665A (en)
CN (1) CN1208954C (en)
AU (1) AU2001275245A1 (en)
MX (1) MXPA02012130A (en)
WO (1) WO2001097512A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6876400B2 (en) * 2001-12-19 2005-04-05 Thomson Licensing S.A. Apparatus and method for protecting a memory sharing signal control lines with other circuitry
US20060063503A1 (en) * 2002-06-17 2006-03-23 Koninklikle Phillips Electronics Nv Receiver and tuner with electronically tuned filter
ES2206040A1 (en) * 2002-10-07 2004-05-01 Televes, S.A. Tunable filter for use in amplifying television signals, uses application of control voltage to each varicap diode in coupling circuit to vary capacitance of coupling circuit
KR100709413B1 (en) * 2004-12-06 2007-04-18 엘지전자 주식회사 Method for Operating Personal System Setting Information in Television Set having Attachable Memory Unit
JP2006325111A (en) * 2005-05-20 2006-11-30 Alps Electric Co Ltd Method for manufacturing television tuner, and television tuner
JP3128349U (en) 2006-10-23 2007-01-11 船井電機株式会社 Television receiver
JP2008199481A (en) 2007-02-15 2008-08-28 Funai Electric Co Ltd Digital broadcast receiving apparatus
JP2009049813A (en) * 2007-08-21 2009-03-05 Sanyo Electric Co Ltd Semiconductor device for use in radio tuner and method for manufacturing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3138143B2 (en) * 1994-06-17 2001-02-26 三洋電機株式会社 Television receiver
JP3319491B2 (en) * 1995-01-19 2002-09-03 船井電機株式会社 Broadcast wave channel tuning method
US5754253A (en) * 1996-01-11 1998-05-19 Lg Electronics Inc. Apparatus for generating a plurality of quasi-moving PIP/POP screens
GB2336731A (en) * 1998-04-22 1999-10-27 Thomson Multimedia Sa A video tuner in which data representing a PLL division is used to control other circuit parameters
KR20020035144A (en) * 1999-09-22 2002-05-09 추후제출 Pll with memory for electronic alignments

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0197512A2 *

Also Published As

Publication number Publication date
KR20030010665A (en) 2003-02-05
WO2001097512A2 (en) 2001-12-20
CN1208954C (en) 2005-06-29
JP2004507911A (en) 2004-03-11
CN1435049A (en) 2003-08-06
MXPA02012130A (en) 2003-04-25
WO2001097512A3 (en) 2002-04-11
AU2001275245A1 (en) 2001-12-24

Similar Documents

Publication Publication Date Title
US6405372B1 (en) Method for updating electronic program guide information and device thereof in a digital TV receiver
FI76468B (en) AVSTAEMNINGSSYSTEM FOER TELEVISION MED ELEKTRONISK FREKVENSREGLERING.
US4667243A (en) Television receiver for direct broadcast satellite signals
EP0477753B1 (en) A previous channel feature in a television receiver having multiple RF inputs
KR100309099B1 (en) Method and apparatus for selecting channel
US4518993A (en) Television signal receiving system
KR100592905B1 (en) Tuning Apparatus
WO2001097512A2 (en) Apparatus for providing tuner parameters in a television receiver
KR100267446B1 (en) Tv tuner
US20040051815A1 (en) Apparatus for providing tuner parameters in a television receiver
KR20020035144A (en) Pll with memory for electronic alignments
US20060158570A1 (en) Multi-tuner receiver having integrated channel lists
US4598425A (en) All-channel television tuning system
EP0396103B1 (en) Channel selecting apparatus
US8027653B2 (en) Signal receiving apparatus and control method thereof
EP0629045B1 (en) Tuning device for a receiver of radioelectric signals with coils obtained by printing
KR100384464B1 (en) Circuit for selecting band of saw filter
KR100219152B1 (en) Automatic tuning system in voltage synthesize for improving channel memory
KR19980017760A (en) RF Amplifier Common Unit for Television Tuner
WO2000003482A1 (en) Frequency adjustment
MXPA97005816A (en) Circuito de sintonizac
JPS6387091A (en) Channel selector
WO2003103281A1 (en) Digital upgrade module for analogue television set
JP2006100894A (en) Tuner

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20021119

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

RIN1 Information on inventor provided before grant (corrected)

Inventor name: MAEXNER, EDWARD, CHARLES

Inventor name: O'DONNELL, EUGENE, MURPHY

Inventor name: HALL, EDWARD, ALLEN

Inventor name: ALPAIWALLA, FEROZ, KAIKI

RBV Designated contracting states (corrected)

Designated state(s): AT BE CH CY DE FR GB IT LI TR

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: THOMSON LICENSING

17Q First examination report despatched

Effective date: 20080211

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20080624