EP1243025A2 - Encapsulation de semi-conducteurs - Google Patents

Encapsulation de semi-conducteurs

Info

Publication number
EP1243025A2
EP1243025A2 EP00967264A EP00967264A EP1243025A2 EP 1243025 A2 EP1243025 A2 EP 1243025A2 EP 00967264 A EP00967264 A EP 00967264A EP 00967264 A EP00967264 A EP 00967264A EP 1243025 A2 EP1243025 A2 EP 1243025A2
Authority
EP
European Patent Office
Prior art keywords
recess
electronic component
package
terminal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP00967264A
Other languages
German (de)
English (en)
Inventor
Behnam Tabrizi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Skyworks Solutions Inc
Original Assignee
Alpha Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha Industries Inc filed Critical Alpha Industries Inc
Publication of EP1243025A2 publication Critical patent/EP1243025A2/fr
Ceased legal-status Critical Current

Links

Classifications

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/147—Semiconductor insulating substrates
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions

  • the present invention relates to electronic devices and more particularly to packaging for electronic devices.
  • Semiconductor electronic devices often include a package surrounding the device to permit handling and electrical connections while providing protection for the electronic device from external environmental influences.
  • Packages are typically manufactured out of plastic, metal, ceramic or glass.
  • an electronic component and a method for making an electronic component have a silicon package.
  • the silicon package has a recess formed thereon in which a conductive region is placed.
  • a bare die electronic device is disposed in the recess.
  • the device has a top, a bottom, sides and a plurality of terminals, including a non-top terminal.
  • the non-top terminal is electrically coupled to the conductive region.
  • the electronic component is constructed by first creating a recess in a silicon wafer to a depth substantially equal to the first dimension of the bare die electronic device.
  • a conductive material is applied to the recess.
  • the electronic device is inserted into the recess so that the bottom terminal is coupled to the conductive material.
  • a dielectric or other planarizing material is applied into the recess.
  • Top and bottom contacts are then applied to form the electronic component so that it may be used as a ball grid array (BGA) package.
  • the top contact is electrically coupled to the top terminal of the
  • multiple recesses are created on a single silicon wafer and electronic devices are each inserted into one of the multiple recesses.
  • the silicon wafer may then be cut to form multiple electronic components. Prior to the step of cutting, each of the electronic components may be tested.
  • one of the terminals of the device is a top contact located on the top of the device and the package has a top in which the recess is located.
  • the top of the package also includes a contact coupled electrically via the conductive region to the non-top terminal.
  • Fig. 1 is a side view of one embodiment of the invention in which an electronic device resides within a silicon package.
  • Fig. 2 is a flow chart of the steps used in creating a silicon package that is a Ball Grid Array (BGA) and that is also a Wafer Level Chip-Scale Package (WLCSP).
  • Fig. 3 is a side view of a silicon wafer having multiple electronic devices.
  • Fig. 4 shows a top view of a silicon wafer that has multiple cavities that are etched into the silicon, each cavity for receiving an electronic device to form multiple packages.
  • Fig. 5 is a side view of a planar electronic device positioned within a package with the terminals of the electronic device redistributed.
  • Fig. 1 is a side view of an electronic component.
  • the electronic component is formed by a silicon package 10 from a silicon wafer surrounding an electronic device 12, preferably a bare die semiconductor device.
  • the silicon package 10 includes a recess 14 in which the electronic device 12 resides.
  • the electronic device 12 in the embodiment shown is a two-terminal device, although other multi-terminal devices, including both vertical and planar devices, may be used.
  • the electronic device shown is a vertical device having a top terminal 15 and a bottom terminal 16. In the recess of the package, a conductive region 17 exists.
  • the conductive region 17 covers all or a portion of the recess 14 and extends to a portion of the top 18 of the silicon package 10.
  • the bottom terminal 16 of the two-terminal electronic device is electrically coupled to the conductive region 17.
  • the conductive region is formed from metals such as titanium, copper and chrome.
  • the bottom terminal 16 of the electronic device is secured to the conductive region by a conductive epoxy or solder 19.
  • the recess 14 is filled with dielectric material 20 that surrounds the electronic device 12. If the dielectric layer 20 covers the top terminal 15 of the electronic device 12, the dielectric 20 that resides above the top terminal 15 is removed through photolithography. Dielectric may also be removed at a point where a solder contact for the bottom terminal is desired.
  • a metalization layer 22 is applied over the dielectric after the top terminal 15 of the electronic device 12 is exposed.
  • the metalization is deposited and patterned by standard methods to the desired routing including solder contact areas.
  • another layer of dielectric 25 resides on top of the metalization layer 22 fully encasing the electronic device 12 and only leaving the contacts exposed. It should be understood by those of ordinary skill in the art that for certain electronic devices a second layer of dielectric may not be needed.
  • the solder contacts 21 are then created and preferably reside in the same plane so that the completed electronic component may be easily flip mounted onto a circuit board.
  • the electronic device is a diode.
  • WLCSP Wafer Level Chip-Scale Package
  • solder contacts for the terminals of the electronic device reside on the same side of the package allowing for surface mount assembly operation similar to a Ball Grid Array (BGA) package.
  • BGA Ball Grid Array
  • other package materials may be used for creating a WLCSP instead of silicon. These other package materials must be sufficiently rigid to prevent breakage or exposure of the bare die. Further, the package material should be capable of being metalized, and should be capable of having a portion of the material removed so as to create a cavity or a recess.
  • Fig. 2 is shown a flowchart of the steps for packaging a bare die electronic device creating an electronic component.
  • the method as described uses a standard silicon wafer to create one or more packages.
  • the silicon wafer may be processed with most of the same tooling as used for wafer level device creation.
  • a silicon package creates a WLCSP.
  • a recess is formed in a silicon wafer by either etching or sawing a trench in the wafer (200).
  • the etching process could be dry etching or chemical wet etching which is known to those skilled in the art.
  • the chemical etching step is normally performed by using Si 3 N 4 as mask on the top surface of the silicon wafer.
  • the mask is patterned to the desired cavity size(s) and location(s).
  • the cavity etch is an anisotropical etch using a solution of KOH and treta-methyl ammonium hydroxide.
  • the cavities created by this process will typically have sloped side walls of about 54 degrees.
  • the recess is created so that an electronic device may reside within the recess.
  • the depth of the recess is approximately the thickness of the electronic device.
  • To the recess is applied at least one layers of conductive material (210). In case of devices with small contacts (approximately .003 inches in diameter or less), it is preferred that a layer of a dielectric such as bisbenzocyclobutene (BCB) is deposited on top of the electronic device covering the entire top surface except for contact terminals and saw/scribe borders seperation for device clearance (Fig. 3).
  • BCB bisbenzocyclobutene
  • the conductive material is applied in three layers.
  • the first layer is titanium followed by a layer of copper and a layer of chrome, which cover the contour of the recess and at least a portion of the top of the silicon wafer.
  • a layer of electrically conductive epoxy or solder is placed in the recess to assure that the device is mechanically secured and the electric device is electrically coupled to the conductive material for devices with non-top terminals.
  • the electronic device is placed within the recess of the silicon wafer so that the bottom of the electronic device comes into contact with the conductive material within the recess (220). Silver epoxy is then cured or the solder is reflown, attaching the device to the bottom of the recess.
  • a layer of dielectric such as BCB
  • BCB dielectric
  • the cavity fill process is done by covering a preheated silicon wafer (to reduce the viscosity of the BCB) and driving the BCB dielectric into the cavities and removing the excess material using a roller and blade drawn across the wafer. If needed another layer of dielectric can be spun on to achieve the desired planarization.
  • the dielectric layer completely covers the electronic device, but it is desirable to keep the top terminal of the electronic device exposed. Dielectric must be subsequently removed from the top terminal and also an area on the top surface of the silicon wafer adjacent to the recess allowing direct exposure to the conductive material.
  • One method of achieving this is by masking and removing the dry-etch BCB from the top terminal of the electronic device and desired area on the top surface of the silicon wafer.
  • a sufficient amount of the dielectric material is removed to expose the entire top surface of the silicon wafer and the top terminal of the electric device.
  • a layer of photo definable BCB is deposited and defined exposing the desired contact areas.
  • a patterned metalization layer is applied to the top of the dielectric and the exposed surface.
  • a last layer of dielectric is added for further insulation so that the only exposed conductive elements are the contacts for the top and bottom terminals.
  • Solder is then deposited onto the exposed conductive elements, forming solder contacts in the appropriate positions such that an electronic coupling occurs between the solder contact and the top (240) and bottom terminals (250) of the device. This process does not require wire /tab bonding nor does it need a flip-chip to create this wafer level BGA CSP.
  • the method may be implemented on a silicon wafer of adequate depth for holding an electronic device. Multiple cavities may be formed for creating multiple packages on the same silicon wafer as shown in Fig.4.
  • the silicon wafer may be etched to create cavities or sawn to create trenches that are spaced to allow for the silicon wafer to be cut so that individual packaged electronic components may be produced.
  • Fig. 4 a 4 x 4 array of cavities is shown on a silicon wafer. Wafer probing of the electronic components may be accomplished prior to the sawing process for separating the completed electronic components.
  • multiple-die electronic components may be packaged by using the above-described technique.
  • a silicon wafer having multiple cavities is formed where the cavities have different dimensions to accommodate different bare die electronic devices.
  • the various bare die electronic devices are placed into their respectively dimensioned cavities and processed as before to create individual Chip-CSP's wherein each chip has metalized contacts.
  • an additional layer of metalization may be applied which electrically couples the multiple electronic devices.
  • a further layer of dielectric may be applied and solder contacts placed in appropriate positions. Separation of the completed multiple-die electronic components may occur by sawing the package.
  • multiple multiple-die electronic components may be created from a single silicon wafer. In Fig.
  • FIG. 5 is shown a package 510 for a bare die planar electronic device 520 that has all terminals 540 on one side of the chip.
  • the terminals 540 of the device 520 are repositioned using the technique above.
  • the bare die 520 is placed into a recess 515 of the package 510 and is adhered to the package using an adhesive 530 to mechanically couple the bare die 520 and the package 510.
  • a planarizing dielectric material 550 Into the portion of the recess 515 that is not filled by the bare die is placed a planarizing dielectric material 550.
  • the planarizing material 550 creates an essentially planar surface for applying a layer of metalization 560 so that the terminals 540 of the bare die 520 may be repositioned.
  • a second layer of dielectric 570 is applied keeping only the positions of the final contacts exposed.
  • a metal contact 580 or soldering bump is added.
  • the electronic component 500 is electrically exposed only at the repositioned contact points 580 with the rest of the electronic device 520 shielded from electrical coupling by the package 510 or dielectric 570.
  • planar electronic devices having terminals that are positioned too close together and are at such a small scale that the terminals cannot maintain their electrical independence when placed on a circuit board may be made effectively larger by repositioning the contacts on the top of the package.
  • the terminals can be repositioned in any configuration that is more convenient for the end user of the electronic components.
  • a smaller device may be made to be compatible with the dimensional requirements of a circuit board for fabrication of a more complicated product or subassembly.
  • non-silicon based semiconductor bare die electronic devices for example Gallium Arsenide electronic devices, may be made into Chip-CSPs by applying the process described above.placing.
  • passive elements such as resistors, capacitors, and inductors may be added on a redistribution layer or on the additional dielectric layers to provide a higher-level integrated electronic component.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un composant électronique et un procédé de fabrication de ce composant électronique doté d'un boîtier en silicium présentant un évidement dans lequel sont logés une zone conductrice et un dispositif électronique à puce nue. Le dispositif, quant à lui, présente un haut, un bas, des parties latérales et une pluralité de terminaux, y compris un terminal sans haut couplé électriquement à la zone conductrice. Le composant électronique est obtenu après avoir ménagé un évidement dans une plaquette de silicium à une profondeur pratiquement égale à la première dimension du dispositif électronique à puce nue. Un matériau conducteur est ensuite appliqué sur l'évidement qui reçoit le dispositif électronique de manière que le terminal inférieur soit couplé au matériau conducteur. Un isolant ou un matériau planarisant est enduit dans l'évidement. Les contacts supérieur et inférieur sont ensuite appliqués pour obtenir le composant électronique de manière qu'il serve de boîtier BGA. Le contact supérieur est couplé électriquement au terminal supérieur du dispositif électronique et le contact inférieur est couplé électriquement au matériau conducteur.
EP00967264A 1999-09-30 2000-10-02 Encapsulation de semi-conducteurs Ceased EP1243025A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15673999P 1999-09-30 1999-09-30
US156739P 1999-09-30
PCT/US2000/027206 WO2001024259A2 (fr) 1999-09-30 2000-10-02 Encapsulation de semi-conducteurs

Publications (1)

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EP1243025A2 true EP1243025A2 (fr) 2002-09-25

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EP00967264A Ceased EP1243025A2 (fr) 1999-09-30 2000-10-02 Encapsulation de semi-conducteurs

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EP (1) EP1243025A2 (fr)
AU (1) AU7748800A (fr)
WO (1) WO2001024259A2 (fr)

Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
DE10047213A1 (de) * 2000-09-23 2002-04-11 Philips Corp Intellectual Pty Elektrisches oder elektronisches Bauteil und Verfahren zum Herstellen desselben
US6686642B2 (en) 2001-06-11 2004-02-03 Hewlett-Packard Development Company, L.P. Multi-level integrated circuit for wide-gap substrate bonding
PL1711058T3 (pl) 2004-01-23 2022-02-07 Eden Research Plc Sposoby zabijania nicieni obejmujące aplikację składnika terpenowego
DE102005007423B3 (de) * 2005-02-18 2006-06-14 Atmel Germany Gmbh Verfahren zur Integration eines elektronischen Bauteils oder dergleichen in ein Substrat
DE102010042567B3 (de) * 2010-10-18 2012-03-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen eines Chip-Package und Chip-Package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5944849A (ja) * 1982-09-08 1984-03-13 Hitachi Ltd 半導体装置およびその製造方法
JPS61214444A (ja) * 1985-03-18 1986-09-24 Fujitsu Ltd 半導体装置
EP0288052A2 (fr) * 1987-04-21 1988-10-26 Sumitomo Electric Industries Limited Dispositif semi-conducteur comprenant un substrat et son procédé de fabrication

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3436604A (en) * 1966-04-25 1969-04-01 Texas Instruments Inc Complex integrated circuit array and method for fabricating same
KR910006706B1 (ko) * 1988-12-12 1991-08-31 삼성전자 주식회사 발광다이오드 어레이 헤드의 제조방법
US5198963A (en) * 1991-11-21 1993-03-30 Motorola, Inc. Multiple integrated circuit module which simplifies handling and testing
US5420460A (en) * 1993-08-05 1995-05-30 Vlsi Technology, Inc. Thin cavity down ball grid array package based on wirebond technology
DE19720300B4 (de) * 1996-06-03 2006-05-04 CiS Institut für Mikrosensorik gGmbH Elektronisches Hybrid-Bauelement und Verfahren zu seiner Herstellung

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5944849A (ja) * 1982-09-08 1984-03-13 Hitachi Ltd 半導体装置およびその製造方法
JPS61214444A (ja) * 1985-03-18 1986-09-24 Fujitsu Ltd 半導体装置
EP0288052A2 (fr) * 1987-04-21 1988-10-26 Sumitomo Electric Industries Limited Dispositif semi-conducteur comprenant un substrat et son procédé de fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0124259A3 *

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WO2001024259A2 (fr) 2001-04-05
AU7748800A (en) 2001-04-30
WO2001024259A3 (fr) 2001-11-29

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