Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C5/00—Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
  • H03F1/0216—Continuous control
  • H03F1/0222—Continuous control by using a signal derived from the input signal
  • H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
  • H03F1/0244—Stepped control
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
  • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
  • H03F3/1935—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices with junction-FET devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
  • H03F3/2176—Class E amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/004—Control by varying the supply voltage
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
  • H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
  • H03F2201/3215—To increase the output power or efficiency

Definitions

• the present invention relates to RF amplifiers and signal modulation.
• Battery life is a significant concern in wireless communications devices such as cellular telephones, pagers, wireless modems, etc. Radio-frequency transmission, especially, consumes considerable power. A contributing factor to such power consumption is inefficient power amplifier operation. A typical RF power amplifier for wireless communications operates with only about 10% efficiency. Clearly, a low-cost technique for significantly boosting amplifier efficiency would satisfy an acute need.
• the transmitted information is sent in a series of one or more short bursts, where the transmitter is active only during the burst times and inactive at all other times. It is therefore also desirable that control of burst activation and deactivation be controlled in an energy-efficient manner, further contributing to extended battery life.
• Power amplifiers are classified into different groups: Class A, Class B, Class AB, etc.
• the different classes of power amplifiers usually signify different biasing conditions. In designing an RF power amplifier, there is usually a trade-off between linearity and efficiency.
• the different classes of amplifier operation offer designers ways to balance these two parameters.
• Linear amplifiers e.g. Class A amplifiers and Class B push-pull amplifiers
• non-linear amplifiers e.g. single-ended Class B and Class C ampli- fiers
• the output signal is not directly proportional to the input signal.
• the resulting amplitude distortion on the output signal makes these amplifiers most applicable to signals without any amplitude modulation, which are also known as constant-envelope signals.
• Amplifier output efficiency is defined as the ratio between the RF output power and the input (DC) power.
• a major source of power amplifier inefficiency is power dissipated in the transistor.
• a Class A amplifier is inefficient since current flows continuously through the device. Conventionally, efficiency is improved by trading-off linearity for increased efficiency.
• biasing conditions are chosen such that the output signal is cut off during half of the cycle unless the opposing half is provided by a second transistor (push-pull). As a result, the waveform will be less linear.
• the output waveform may still be made sinusoidal using a tank circuit or other filter to filter out higher and lower frequency components.
• Class C amplifiers conduct during less than 50% of the cycle, in order to further increase efficiency; i.e., if the output current conduction angle is less than 180 degrees, the amplifier is referred to as Class C.
• This mode of operation can have a greater efficiency than Class A or Class B, but it typically creates more distortion than Class A or Class B amplifiers.
• a Class E power amplifier uses a single transistor, in contrast with a Class D power amplifier, which uses two transistors
• switches are not ideal. (Switches have turn on/off time and on-resistance.) The associated dissipation degrades efficiency.
• the prior art has therefore sought for ways to modify so-called "switch-mode" amplifiers (in which the transistor is driven to act as a switch at the operating frequency to minimize the power dissipated while the transistor is conducting current) so that the switch voltage is zero for a non-zero interval of time about the instant of switching, thereby decreasing power dissipation.
• the Class E amplifier uses a reactive output network that provides enough degrees of freedom to shape the switch voltage to have both zero value and zero slope at switch turn-on, thus reducing switching losses.
• Class F amplifiers are still a further class of switch-mode amplifiers.
• Class F amplifiers generate a more square output waveform as compared to the usual sinewave. This "squaring-up" of the output waveform is achieved by encouraging the generation of odd-order harmonics (i.e., x3, x5, x7, etc.) and suppressing the even-order harmonics (i.e., x2, x4, etc.) in the output network.
• odd-order harmonics i.e., x3, x5, x7, etc.
• even-order harmonics i.e., x2, x4, etc.
• FIG. 1 An example of a known power amplifier for use in a cellular telephone is shown in Figure 1.
• GSM cellular telephones for example, must be capable of programming output power over a 30dBm range.
• the transmitter turn-on and turn-off profiles must be accurately controlled to prevent spurious emissions.
• Power is controlled directly by the DSP (digital signal processor) of the cellular telephone, via a DAC (digital to analog converter).
• a signal GCTL drives the gate of an external AGC amplifier that controls the RF level to the power amplifier. A portion of the output is fed back, via a directional coupler, for closed-loop operation.
• the amplifier in Figure 1 is not a switch-mode amplifier. Rather, the amplifier is at best a Class AB amplifier driven into saturation, and hence demonstrates relatively poor efficiency.
• FIG. 2 shows an example of a known Class E power amplifier, described in U.S. Patent 3,919,656.
• An RF input signal is coupled over a lead 1 to a driver stage 2, the latter controlling the active device 5 via a signal coupled over a lead 3.
• the active device 5 acts substantially as a switch when appropriately driven by the driver 2.
• the output port of the active device is therefore represented as a single- pole single-throw switch 6.
• Connected across the switch 6 is the series combination of a DC power supply 7 and the input port of a load network 9.
• the output port of the load network 9 is connected to the load 1 1.
• the switch 6 is cyclically operated at the desired AC output frequency, DC energy from the power supply 7 is converted into AC energy at the switching frequency (and harmonics thereof).
• the Class E amplifier arrangement of Figure 2 although it is theoretically capable of achieving high conversion efficiency, suffers from the disadvantage that large voltage swings occur at the output of the active device, due to ringing. This large voltage swing, which typically exceeds three times the supply voltage, precludes the use of the Class E circuit with certain active devices which have a low breakdown voltage.
• the driving circuit in the RF amplifier of Figure 2 typically includes a matching network consisting of a tuned (resonant) circuit.
• a driver amplifier typically of Class A operation.
• An output signal of the driver amplifier is coupled through the matching network to a control terminal of the switching transistor, shown in Figure 3 as an FET.
• the PAE of a power amplifier is set by the amount of DC supply power required to realize the last 26dB of gain required to achieve the final output power. (At this level of gain, the power input to the amplifier through the driving signal—which is not readily susceptible to measurement— becomes negligible.)
• the amplifying devices capable of producing output powers of 1 W or greater at radio frequencies and that also provide a power gain of at least 26dB. Accordingly, one or more amplifiers must be provided ahead of the final stage, and the DC power consumed by such amplifiers must be included in the determination of overall PAE.
• An example of an RF amplifier circuit in accordance with the foregoing approach is shown in Figure 4.
• An interstage "T section" consisting of an inductor LI , a shunt capacitor C and an inductor L2 is used to match the driver stage to an assumed 50 ohm load (i.e., the final stage).
• This conventional practice treats the interstage between the drive and final stages as a linear network, which it is not. Further, the conventional practice maximizes power transfer between the driver and final stages (an intended consequence of impedance matching). Thus, for example, in order to develop the required drive voltage for a FET as the switching transistor, the driver must also develop in-phase current as well to provide the impedance-matched power.
• FIG. 5 Another example of a conventional RF power amplifier circuit is shown in Figure 5.
• This circuit uses "resonant interstage matching" in which the drive and final stages are coupled using a coupling capacitor Ccpl.
• a related problem is the generation of modulated signals, e.g., amplitude modulated (AM) signals, quadrature amplitude modulated signals (QAM), etc.
• a known IQ modulation structure is shown in Figure 6.
• a data signal is applied to a quadrature modulation encoder that produces I and Q signals.
• the I and Q signals are applied to a quadrature modulator along with a carrier signal.
• the carrier signal is generated by a carrier generation block to which a tuning signal is applied.
• an output signal of the quadrature modulator is then applied to a variable attenuator controlled in accordance with a power control signal.
• power control is implemented by vaying the gain of the amplifier. This is achieved by adjusting the bias on transistors within the inear amplifier, taking advantage of the effect where transistor transconductance varies with the aplied bias conditions. Since amplifier gain is strongly related to the transistor transconductance, varying the transconductance effectively varies the amplifier gain. A resulting signal is then amplified by a linear power amplifier and applied to an antenna.
• AM signals the amplitude of the signal is made substantially proportional to the magnitude of an information signal, such as voice.
• Information signals such as voice are not constant in nature, and so the resulting AM signals are continuously varying in output power.
• a method for producing accurate amplitude modulated signals using nonlinear Class C amplifiers, called "plate modulation,” has been known for over 70 years as described in texts such as Terman's Radio Engineers Handbook (McGraw-Hill, 1943).
• output current from the modulator amplifier is linearly added to the power supply current to the amplifying element (vacuum tube or transistor), such that the power supply current is increased and decreased from its average value in accordance with the amplitude modulation.
• This varying current causes the apparent power supply voltage on the amplifying element to vary, in accordance with the resistance (or conductance) characteristics of the amplifying element.
• AM By using this direct control of output power, AM can be effected as long as the bandwidth of the varying operating voltage is sufficient. That is, these nonlinear amplifiers actually act as linear amplifiers with respect to the amplifier operating voltage. To the extent that this operating voltage can be varied with time while driving the nonlinear power amplifier, the output signal will be linearly amplitude modulated.
• U.S. Patent 5,126,688 to Nakanishi et al. addresses the control of linear amplifiers using feedback control to set the actual amplifier output power, combined with periodic adjustment of the power amplifier operating voltage to improve the operating efficiency of the power amplifier.
• the primary drawback of this technique is the requirement for an additional control circuit to sense the desired output power, to decide whether (or not) the power amplifier operating voltage should be changed to improve efficiency, and to effect any change if so decided.
• This additional control circuitry increases amplifier complexity and draws additional power beyond that of the amplifier itself, which directly reduces overall efficiency.
• a further challenge has been to generate a high-power RF signal having desired modulation characteristics.
• This object is achieved in accordance with the teachings of U.S. Patent 4,580,1 1 1 to Swanson by using a multitude of high efficiency amplifiers providing a fixed output power, which are enabled in sequence such that the desired total combined output power is a multiple of this fixed individual amplifier power.
• the smallest change in overall output power is essentially equal to the power of each of the multitude of high efficiency amplfiers. If finely graded output power resolution is required, then potentially a very large number of individual high efficiency amplifiers may be required. This clearly increases the overall complexity of the amplifier.
• U.S. Patent 5,321,799 performs polar modulation, but is restricted to full- response data signals and is not useful with high power, high-efficiency amplifiers.
• the patent teaches that amplitude variations on the modulated signal are applied through a digital multiplier following phase modulation and signal generation stages. The final analog signal is then developed using a digital-to-analog converter.
• signals with information already implemented in amplitude variations are not compatible with high-efficiency, nonlinear power amplifiers due to the possibly severe distortion of the signal amplitude variations.
• the present invention provides for high-efficiency power control of a high-efficiency (e.g., hard-limiting or switch-mode) power amplifier in such a manner as to achieve a desired control or modulation.
• a high-efficiency (e.g., hard-limiting or switch-mode) power amplifier in such a manner as to achieve a desired control or modulation.
• feedback is not required. That is, the amplifier may be controlled without continuous or frequent feedback adjustment.
• the spread between a maximum frequency of the desired modulation and the operating frequency of a switch-mode DC-DC converter is reduced by following the switch- mode converter with an active linear regulator.
• the linear regulator is designed so as to control the operating voltage of the power amplifier with sufficient bandwidth to faithfully reproduce the desired amplitude modulation waveform.
• the linear regulator is further designed to reject variations on its input voltage even while the output voltage is changed in response to an applied control signal. This rejection will occur even though the variations on the input voltage are of commensurate or even lower frequency than that of the controlled output variation.
• Amplitude modulation may be achieved by directly or effectively varying the operating voltage on the power amplifier while simultaneously achieving high efficiency in the conversion of primary DC power to the amplitude modulated output signal. High efficiency is enhanced by allowing the switch-mode DC-to-DC converter to also vary its output voltage such that the voltage drop across the linear regulator is kept at a low and relatively constant level.
• Time-division multiple access (TDMA) bursting capability may be combined with efficient amplitude modulation, with control of these functions being combined.
• the variation of average output power level in accordance with commands from a communications system may also be combined within the same structure.
• the high-efficiency amplitude modulation structure may be extended to any arbitrary modulation. Modulation is performed in polar form, i.e., in a quadrature-free manner.
• Figure 1 is a block diagram of a known power amplifier with output power controlled by varying the power supply voltage
• FIG. 2 is a simplified block diagram of a known single-ended switch mode RF amplifier
• Figure 3 is a schematic diagram of a portion of a known RF amplifier
• Figure 4 is a schematic diagram of a conventional RF power amplifier circuit
• Figure 5 is a schematic diagram of another conventional RF power amplifier circuit
• Figure 6 is a block diagram of a known IQ modulation structure
• Figure 7 is a block diagram of a power amplifier in accordance with an exemplary embodiment
• Figure 9 is a waveform diagram illustrating operation of one embodiment
• Figure 10 is a waveform diagram illustrating operation of another embodiment
• Figure 1 1 is a waveform diagram illustrating bursted AM operation
• Figure 12 is a waveform diagram illustrating bursted AM operation with power level control
• Figure 13 is a block diagram of a polar modulation structure using a high- efficiency amplifier
• Figure 14 is a block diagram of a first high power, high efficiency, amplitude modulating RF amplifier
• Figure 15 is a waveform diagram illustrating operation of the amplifier of Figure 14;
• Figure 16 is a block diagram of a second high power, high efficiency, amplitude modulating RF amplifier
• Figure 17 is a waveform diagram illustrating operation of the amplifier of Figure 16;
• Figure 18 is a block diagram of an RF switch mode amplifier in accordance with one embodiment
• Figure 19 is a schematic diagram of a portion of an RF switch mode amplifier in accordance with one embodiment of the present invention.
• Figure 20 is a schematic diagram of a suitable load network for use in the RF switch mode amplifier of Figure 19;
• Figure 21 is a waveform diagram showing input voltage and related waveforms for the RF switch mode amplifier of Figure 19;
• Figure 22 is a waveform diagram showing base and collector current waveforms of the switching transistor of Figure 19;
• Figure 23 is a waveform diagram showing output voltage for the RF switch mode amplifier of Figure 19;
• Figure 24 is a schematic diagram of a portion of an RF switch mode amplifier in accordance with another embodiment
• Figure 25 is a waveform diagram showing input voltage and related waveforms for the RF switch mode amplifier of Figure 24;
• Figure 26 is a waveform diagram showing collector current waveforms of the drive transistors of Figure 24;
• Figure 27 is a waveform diagram showing a gate voltage waveform of the switching transistor of Figure 24;
• Figure 28 is a schematic diagram of an RF power amplifier circuit in accordance with another embodiment.
• Figure 29 is a waveform diagram showing waveforms occurring at selected nodes of the amplifier circuit of Figure 28.
• FIG. 7 a block diagram is shown of a power amplifier that overcomes many of the aforementioned disadvantages.
• a switch-mode (or saturated) nonlinear amplifier has applied to it a voltage produced by a power control stage.
• the voltage V applied to the nonlinear ampli - bomb is controlled substantially in accordance with the equation
• the power control stage receives a DC input voltage, e.g., from a battery, and receives a power level control signal and outputs a voltage in accordance with the foregoing equation.
• a power control circuit in accordance with an exemplary embodiment.
• a power control circuit includes a switch-mode converter stage and a linear regulator stage connected in series.
• the switch-mode converter may be a Class D device, for example, or a switch-mode power supply (SMPS).
• SMPS switch-mode power supply
• the switch-mode converter efficiently steps down the DC voltage to a voltage that somewhat exceeds but that approximates the desired power-amplifier operating voltage level. That is, the switch-mode converter performs an efficient gross power level control.
• the switch-mode converter may or may not provide sufficiently fine control to define ramp portions of a desired power envelope.
• the linear regulator performs a filtering function on the output of the switch-mode converter. That is, the linear regulator controls precise power-envelope modulation during a TDMA burst, for example.
• the linear regulator may or may not provide level control capabilities like those of the switch-mode converter.
• the power control circuit may be used to perform power control and/or amplitude modulation.
• a control signal PL/BURST/MOD is input to a control block, which outputs appropriate analog or digital control signals for the switch-mode converter and the linear regulator.
• the control block may be realized as a ROM (read-only memory) and/or a DAC (digital to analog converter).
• the waveforms A and B represent analog control signals applied to the switch-mode converter and to the linear regulator, respectively.
• the waveforms Vj and V 2 represent the output voltages of the switch-mode converter and to the linear regulator, respectively.
• the switch-mode converter has a relatively large time constant, i.e., that it ramps relatively slowly.
• the control signal A is set to a first non-zero power level
• the voltage V j will then begin to ramp toward a commensurate voltage.
• the voltage V j may have a considerable amount of ripple.
• An amount of time required to reach the desired voltage defines the wakeup period.
• the control signal B When that voltage is reached, the control signal B is raised and lowered to define a series of transmission bursts.
• the control signal B When the control signal B is raised, the voltage V 2 ramps quickly up to a commensurate voltage, and when the control signal B is lowered, the voltage V 2 ramps quickly down.
• the control signal A is raised in order to increase the RF power level of subsequent bursts.
• the control signal B remains low during a wait time.
• the control signal B is then raised and lowered to define a further series of transmission bursts.
• the voltage V 2 is shown in dotted lines superimposed on the voltage V j . Note that the voltage V is less than the voltage V j by a small amount, greater than the negative peak ripple on the voltage Vj . This small difference between the input voltage of the linear regulator V j and the output voltage of the linear regulator V 2 makes overall high-efficiency operation possible.
• the switch-mode converter is assumed to have a relatively short time constant; i.e., it ramps relatively quickly.
• the control signal A when the control signal A is raised, the voltage V j ramps quickly to the commensurate voltage.
• the control signal B is then raised, and the voltage V 2 is ramped.
• the time difference between when the control signal A is raised on the control signal B is raised defines the wake up time, which may be very short, maximizing sleep time and power savings.
• the control signal B is then lowered at the conclusion of the transmission burst, after which the control signal A is lowered.
• the control signal A when the control signal A is next raised, it defines a higher power level. Again, the voltage V 2 is superimposed in dotted lines on the voltage V j .
• FIG. 1 a waveform diagram is shown illustrating bursted AM operation.
• An output signal of the switch-mode converted is shown as a solid line.
• the switch-mode converter may ramp up to a fixed level with the linear regulator effecting all of the amplitude modulation on the output signal. More preferably, from an efficiency standpoint, the switch-mode converter effects amplitude modulation, producing an output signal that, ignoring noise, is a small fixed offset ⁇ V above the desired output signal.
• the linear regulator removes the noise from the output signal of the switch-mode converter, effectively knocking down the signal by the amount ⁇ V.
• the output signal of the linear regulator is shown as a dotted line in Figure 1 1. At the conclusion of the burst, the signals ramp down.
• FIG. 13 a block diagram is shown of a polar modulation structure using a high-efficiency amplifier of the type described thus far.
• This polar modulation structure is capable of effecting any desired modulation.
• a data signal is applied to a modulation encoder that produces magitude and phase signals.
• the phase signal is applied to a phase-modulation-capable carrier generation block, to which a tuning signal is also applied.
• a resulting signal is then amplified by a non- linear power amplifier of the type previously described. Meanwhile, the magnitude signal is applied to a magnitude driver.
• the magnitude driver also receives a power control signal. In response, the magnitude driver produces an operating voltage that is applied to the non-linear amplifier.
• the magnitude driver and the non-linear amplifier may be realized in the same manner as Figure 7, described previously, as indicated in Figure 13 by a dashed line.
• modulation structures described thus far are suitable for use in, among other applications, cellular telephone handsets.
• a similar need for high-efficiency RF signal generation exists in cellular telephone basestations.
• Basestations operate at much higher power than handsets.
• the following structure may be used to achieve high-power, high-efficiency RF signal generation.
• a first high power, high efficiency, amplitude modulating RF amplifier includes multiple switch mode power amplifier (SMPA) blocks, each block being realized as shown in Figure 7, for example.
• An RF signal to be amplified is input to all of the SMPA blocks in common.
• Separate control signals for each of the SMPA blocks are generated by a magnitude driver in response to a magnitude input signal.
• Output signals of the SMPA blocks are summed to form a single resultant output signal.
• a common drive signal is generated and applied in common to all of the SMPAs.
• the common drive signal is caused to have a value that is one Nth of an overall magnitude signal applied to the magnitude driver, where N is the number of SMPAs.
• FIG. 18 there is shown a block diagram of an RF switch mode amplifier in accordance with a another embodiment.
• An RF input signal is applied to a non-reactive driving circuit.
• the driving circuit is coupled to an active device to drive the active device switch.
• the active device switch is coupled to a load network that produces an RF output signal for application to a load, e.g., an antenna.
• a load e.g., an antenna.
• power is applied to the active device switch through a rapid time variable power supply, realized by the series combination of a switch mode power supply and a linear regulator, enabling the operating voltage of the active device switch to be varied.
• a rapid time variable power supply realized by the series combination of a switch mode power supply and a linear regulator, enabling the operating voltage of the active device switch to be varied.
• the active device switch may be either a bipolar transistor or a FET transistor.
• a schematic diagram is shown of a portion of an RF switch mode amplifier in which the active device switch is a bipolar transistor having collector, emitter and base terminals.
• the collector of the bipolar transistor Nl is connected through an RF choke L to an operating voltage V PA and is also connected to an output matching network.
• the emitter of the bipolar transistor Nl is connected to circuit (AC) ground.
• the base of the bipolar transistor Nl is connected to the emitter of another bipolar transistor N2 (the driver transistor) in Darlington fashion.
• the collector of the driver transistor N2 is connected to an operating voltage V DR ⁇ ⁇ R and is also connected to a bypass capacitor.
• a bias network including, in the illustrated embodiment, three resistors, Rl, R2 and R3.
• One resistor Rl is connected from the emitter of the driver transistor to circuit ground.
• Another resistor R2 is connected from the base of the driver transistor to ground.
• the final resistor R3 is connected from the base of the driver transistor N2 to V DR JVER- An RF input signal is applied to the base of the driver transistor through a DC isolation capacitor C m .
• the output network may take the form of an impedance-matching transmission line TL and a capacitor C out .
• the RF input voltage signal is sinusoidal as shown by waveform 1 of Figure 21.
• the input voltage is level shifted upward to produce a voltage at the base of the driver transistor N2, shown by waveform 2.
• the emitter voltage of the driver transistor N2, shown by waveform 3, is one V be drop below and is applied to the base of the switching transistor N 1.
• the driver transistor N2 is operating as an emitter follower, with output (emitter) voltage sufficiently below the turn-on voltage of the switching transistor Nl so that the switching transistor N 1 is cut off.
• the driver transistor N2 turns the switching transistor Nl on and drives it into saturation as shown in Figure 22.
• FIG. 23 a schematic diagram is shown of a portion of an RF switch mode amplifier in which the active device switch is a FET transistor (MES- FET, JFET, PHEMT, etc.) having drain, source and gate terminals.
• the drain of the FET transistor Ml is connected through an RF choke LI to an operating voltage Vp A and is also connected to an output network.
• the source of the FET transistor is connected to circuit (AC) ground.
• the gate of the FET transistor is biased from supply -V B through a large value resistor Rl , and is further connected through a DC isolation capacitor C 1 to a pair of bipolar transistors (driver transistors) connected in push-pull arrangement.
• the driver transistors include an NPN transistor Nl and a PNP transistor PI .
• the collector of the NPN driver transistor Nl is connected to an operating voltage V cc and is also connected to a bypass capacitor.
• the collector of the PNP driver transistor PI is connected to a negative reference voltage -V B and is also connected to a bypass capacitor.
• the bases of the driver transistors are connected in common. Large-valued resistors R2 and R3 connect the common node to the respective power supply rails.
• a further NPN bipolar transistor N2 is connected in common base configuration.
• the emitter of the further bipolar transistor is connected through a resistor R4 to -V B and is connected through a capacitor C3 to the RF input signal.
• the collector of the further bipolar transistor is connected through an inductor L2 to V cc and is also connected to a bypass capacitor.
• input voltage waveforms 1-4 are shown for the circuit of Figure 24.
• the input voltage 1 is level shifted down one V be (producing voltage 2) and is then applied to the emitter of the bipolar transistor N2.
• a large voltage swing 3 is produced at the collector of the bipolar transistor N2 by action of the inductor L2.
• This voltage swing is level shifted downward to produce a voltage 4 that is applied to the bases of the driver transistors at node N.
• the further bipolar transistor N2 is turned off. Current flows through the inductor L2 into the capacitor C2 coupled to the bases of the transistor pair, causing the NPN transistor Nl to turn on and causing the PNP transistor PI to turn off ( Figure 26).
• the DC isolation capacitor Cl is charged up from the V cc supply, raising the gate potential of the FET Ml , causing it to turn on ( Figure 27).
• the further bipolar transistor N2 is turned on. Current flows through the inductor L2, through the further transistor N2 to the -V B rail. Current also flows out of the base of the PNP transistor PI, turning it on.
• the DC isolation capacitor Cl discharges, lowering the gate potential of the FET Ml, causing it to turn off.
• the output network operates in the same manner as previously described.
• FIG. 28 a schematic diagram is shown of a multi-stage RF power amplifier circuit with which the foregoing driver circuit may be used.
• An input matching circuit composed of a coupling capacitor C j , a capacitor C and an inductor L j is used to set the input impedance of the circuit.
• a driver stage M j and a final stage M 2 are shown as FETs, although in other embodiments bipolar transistors may be used.
• the drain electrode of the FET M j is coupled to a supply voltage V dl through a drain bias network including an RF choke L 3 and a capacitor C 5 .
• the drain electrode of the FET M 2 is coupled to a supply voltage V d2 through a drain bias network including an RF choke L 7 and a capacitor C 10 .
• Respective gate bias networks are provided for the stages M j and M 2 .
• the gate bias network is composed of an inductor L 2 , a capacitor C 3 and a capacitor C 4 connected at a common node to a voltage V gl .
• the gate bias network is composed of an inductor L 6 , a capacitor C 8 and a capacitor C Q connected at a common node to a voltage V g2 .
• the driver stage and the final stage are coupled by an interstage network, shown here as a series LC combination composed of an inductor L and a capacitor C 6 , values of which are chosen so as to provide a resonance with the input capacitance of the final stage M 2 .
• the final stage M 2 is coupled to a conventional load network, illustrated in this example as a CLC Pi network composed of a capacitor Ci ⁇ , an inductor L 8 and a capacitor C i2 , values of which are determined in accordance with characteristics of the final stage M 2 .
• component values may be as follows, where capacitance is measured in picofarads and inductance is measured in nanohenries:
• the driver stage, stage M j is operated in switch mode.
• waveforms diagrams are provided showing the input voltage to the stage M 2 at node A, the drain voltage of the stage M j at node B, the drain voltage of the stage M 2 at node C, the drain current of the stage Mi at node D, and the drain current of the stage M 2 at node E.
• the peak value of the gate voltage of the final stage, stage M 2 (waveform A), is considerably greater than in conventional designs.
• the input drive of the switch may be sufficiently high that the operating voltage of the driver stage may be reduced. This reduction further reduces the DC supply power to the driver, enhancing PAE.
• PAE of 72% has been measured at an output power of 2W.

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• 2000
  • 2000-07-31 KR KR1020027001158A patent/KR20020059343A/ko not_active Application Discontinuation
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  • 2000-07-31 JP JP2001514531A patent/JP2003506941A/ja active Pending
  • 2000-07-31 WO PCT/US2000/020841 patent/WO2001010013A1/en not_active Application Discontinuation
  • 2000-07-31 CN CNB008120587A patent/CN1249912C/zh not_active Expired - Lifetime
  • 2000-07-31 AU AU66157/00A patent/AU6615700A/en not_active Abandoned

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