Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
  • H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
  • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
  • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
  • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
  • H04N21/4383—Accessing a communication channel

Definitions

• the present invention relates to the demodulation and processing of signals modulated according to different modulation schemes, such as satellite signals and terrestrial broadcast high definition signals, for example.
• DSS direct satellite system
• HDTV High Definition
• ATSC Advanced Television Standards Committee
• FCC US Federal Communications Committee
• DVB direct video broadcast
• the different digital signals are modulated onto carriers for transmission to consumers using different modulation schemes.
• the DSS signals are modulated using a quadrature phase shift keyed (QPSK) modulation scheme.
• the ATSC signals are modulated using a vestigial sideband (VSB) modulation scheme.
• the DVB satellite signals are modulated using a QPSK modulation scheme, and DVB cable signals are modulated using a quadrature amplitude modulation (QAM) scheme with either a 64 or 256 point constellation.
• QAM quadrature amplitude modulation
• One skilled in the art will further understand that even similar modulation schemes (e.g. QPSK) may use different parameters, such as the excess bandwidth factor, requiring that demodulators for the different QPSK signals be configured differently.
• each set top box includes a demodulator adapted to the modulation scheme of the modulated digital signal, and a transport processor adapted to the protocol of the demodulated digital signal.
• each set top box may have its own remote control that may be incompatible with those of the other set top boxes.
• Such a receiver must include a demodulator section which can selectively demodulate signals modulated by different modulation schemes, and a transport decoder section which can selectively process the demodulated digital signals according to the respectively different protocols.
• Such systems include a single adaptive demodulator which can be fabricated on a single integrated circuit (IC) chip and demodulate signals modulated according to different modulation schemes.
• IC integrated circuit
• additional demodulators may be more easily added, but it still requires augmenting the multiplexer connecting those demodulators to the transport processor. This could mean using multiplexer input terminals available but unused. For example, an example of a preexisting multiplexer has four input terminals. In a system originally including three demodulators, a fourth may be added using the fourth available but unused input terminal in such a multiplexer. However, the addition of a fifth demodulator would require a complete redesign of the multiplexer circuit. In either case, addition of demodulators requires additional control signals for that multiplexer and additional pins on the multiplexing chip, or additional complexity in the control signal distribution system.
• receivers for signals transmitted in a plurality of protocols, and modulated according to a plurality of corresponding modulation schemes be constructed so that adding new demodulators is made easy and inexpensive.
• a multiple protocol receiver includes a demodulator section.
• the demodulator section includes a plurality of demodulators, each demodulator having a tri-state output terminal for generating demodulated digital data.
• the tri-state output terminals are coupled to a signal bus.
• the signal bus is coupled to a signal processor, such as a transport processor, for processing the demodulated digital data.
• a demodulator section designed in such a manner makes it easy to add an additional demodulator.
• the additional demodulator need only have a tri-state output terminal, as the others do, and be connected to the system bus.
• Fig. 1 is a block diagram of a demodulator section of a receiver according to the present invention.
• Fig. 2 is a more detailed block diagram of a demodulator section of a receiver according to the present invention illustrated in Fig. 1 .
• Fig. 1 is a block diagram of a demodulator section of a receiver according to the present invention.
• a plurality 10 of N demodulators are coupled to respective sources (not shown) of baseband modulated signals, modulated according to one of a plurality of respectively different modulation schemes.
• Demodulator 1 1 0( 1 ) demodulates signals according to one modulation scheme (e.g. VSB for HDTV), demodulator 2 1 0(2) demodulates signals according to a different modulation scheme (e.g. QPSK for DSS).
• the remainder of the demodulators demodulate signals according to respectively different modulation schemes (e.g. QPSK and QAM for DVB).
• the respective output terminals of the plurality 1 0 of demodulators are coupled to a signal bus 20 including data and control signal lines (not shown), in a known manner.
• the signal bus 20 is also coupled to an input terminal of a transport processor 30.
• a system controller 40 provides control signals to the plurality 10 of demodulators (and to other circuits - not shown).
• Each of the plurality 10 of demodulators includes a tri-state output buffer
• Each such tri-state output buffer includes a control input terminal OE.
• the system controller 40 provides a control signal to each of the output enable input terminals of the tri-state buffers 1 2.
• the system controller 40 provides an output enable control signal to the tri-state buffer 1 2 of only a selected one of the plurality 10 of demodulators.
• the tri-state buffer 1 2 in the selected demodulator 10 produces logic level signals representing the demodulated digital data from that demodulator 10.
• the remainder (i.e. non- selected ones) -of the plurality 10 of demodulators receive control signals to disable the outputs of the tri-state buffer 1 2.
• the output terminals of the tri-state buffers are conditioned to exhibit a high output impedance.
• the selected one of the plurality 10 of demodulators is coupled to the signal bus 20, while the other ones of the plurality 1 0 of demodulators are isolated from the signal bus 20.
• Signals from the selected one of the plurality 10 of demodulators are, thus, supplied to the transport processor 30 via the signal bus 20.
• the system controller 40 supplies control signals (not shown) to the transport processor 30, in a known manner.
• the transport processor 30 processes the demodulated digital signals from the selected one of the plurality 10 of demodulators in the appropriate manner to generate a payload signal (not shown) which is further processed, also in a known manner.
• Fig. 2 is a more detailed block diagram of the demodulator section of a receiver according to the present invention illustrated in Fig. 1 .
• Fig. 2 those elements which are the same as those illustrated in Fig. 1 are designated by the same reference numbers and are not described in detail below.
• demodulators 10(1 ) and 10(2) are illustrated.
• More than two demodulators may be included in a system in accordance with the present invention.
• each of the plurality 1 0 of demodulators generates four signals carrying the demodulated digital data from that demodulator.
• the digital data is carried in the form of a serial bit stream.
• a data signal (DATA) is generated carrying a non-return-to-zero (NRZ) format serial data stream signal representing the demodulated digital data, and a corresponding clock signal
• CLOCK is generated carrying timing information to permit clocking of that data into following circuitry.
• the serial data is produced at substantially 42 MHz
• the serial data is produced at substantially 43 MHz.
• Other formats produce serial data at different data rates.
• the transport processor 30 is fabricated to be able to process serial data at all of the data rates produced by the plurality 1 0 of demodulators.
• Further signals produced by the plurality 1 0 of demodulators are a packet valid signal (PACKET VALID), and a packet data signal (PACKET DATA) .
• the packet valid signal (PACKET VALID) is conditioned to assume one logic state when the data in the packet currently being carried on the signal bus 20 is valid and the other logic state when the current packet had so many errors that the data could not be accurately recovered.
• the packet data signal (PACKET DATA) is conditioned to assume one logic state when the serial data currently being carried on the signal bus 20 represents transport data and the other logic state when the serial data currently being carried by the signal bus 20 represents overhead information, such as error detection and correction code information.
• the transport processor 30 will ignore packets that are not valid, and serial data that does not represent transport data, as indicated by the PACKET VALID and PACKET DATA signals.
• the system controller 40 generates control signals for the plurality 10 of demodulators.
• a control register 14 in each one of the plurality 10 of demodulators is coupled to receive the control signal from the system controller 40 in a known manner.
• An output terminal of the control register 14 is coupled in common to the output enable input terminal of the tri-state buffers 1 2.
• control signals may be supplied from the system controller 40 to the plurality 1 0 of demodulators by any of a number of known schemes.
• the system controller 40 may be implemented with a microprocessor, and each one of the plurality 10 of demodulators may be coupled in common to the control bus of the microprocessor.
• the plurality 1 0 of demodulators are coupled to and controlled by a microprocessor via a Philips I2C control bus, in a known manner.
• the signal bus 20 consists of four signal lines: a first for the serial data signal DATA and a second for the serial data clock signal CLOCK. These two lines comprise the data portion of the signal bus 20.
• a third signal line is for the packet valid signal (PACKET VALID) and a fourth signal line is for the packet data signal (PACKET DATA). These two signal lines comprise the control portion of the signal bus 20.
• the transport processor 30 receives these signals, extracts the digital data, and if it the packet is valid, and the current data bits represent transport data, processes the data to extract the payload, all in a known manner.
• the signal bus 20 is coupled to the transport processor 30 through an optional buffer circuit 25, shown in phantom in Fig. 2.
• the buffer circuit 25 provides additional drive power for the signals in the signal bus 20. This may be necessary if the plurality 1 0 of demodulators are not collocated with the transport processor 30. For example, if the plurality 10 of demodulators are on one or more IC chips, and the transport processor is on a different IC chip, then the signal bus must travel through e.g. printed circuit board (PCB) traces. In order to provide relatively robust transmission, the buffer 25 is required.
• PCB printed circuit board
• the plurality 10 of demodulator circuits are fabricated using a 3.3 volt CMOS process, while the transport processor 30 is fabricated using 5 volt TTL process.
• the buffer circuit 25 also includes specially designed power-on circuitry to keep the output terminals off during power up. This prevents the 3.3 v. CMOS output terminals of the plurality 10 of demodulator IC chips from inadvertently latching the 5 v. input terminals of the transport processor 30 during power up.
• the signal bus 20 is illustrated as including 4 signal lines.
• the demodulated digital data could be represented in parallel form instead of serial form.
• the clock signal CLOCK would be a byte clock in this arrangement. This increases the number of pins necessary on the plurality 10 of demodulators and the transport processor 30 (and the buffer 25), and increases the number of tri-state buffers 12 required in each demodulator 10, but decreases the output bit rate of the signal bus 20 by a factor of e.g. eight.

Landscapes

• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Communication Control (AREA)
• Television Systems (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
• Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Applications Claiming Priority (3)

Publications (1)

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Family Applications (1)

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• 2000
  • 2000-06-21 WO PCT/US2000/017040 patent/WO2001006759A1/en active IP Right Grant
  • 2000-06-21 EP EP00941606A patent/EP1197068A1/en not_active Ceased
  • 2000-06-21 JP JP2001511079A patent/JP2003505942A/ja not_active Withdrawn
  • 2000-06-21 CN CNB008121877A patent/CN1174606C/zh not_active Expired - Fee Related
  • 2000-06-21 MX MXPA02000479A patent/MXPA02000479A/es active IP Right Grant
  • 2000-06-21 KR KR1020027000372A patent/KR20020035097A/ko not_active Application Discontinuation
  • 2000-06-21 AU AU56297/00A patent/AU766152B2/en not_active Ceased
  • 2000-07-13 MY MYPI20003199 patent/MY123527A/en unknown
  • 2000-07-15 TW TW089114171A patent/TW483280B/zh not_active IP Right Cessation

Non-Patent Citations (1)

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