EP1189132A3 - Architecture de périphérique partagé - Google Patents

Architecture de périphérique partagé Download PDF

Info

Publication number
EP1189132A3
EP1189132A3 EP01307328A EP01307328A EP1189132A3 EP 1189132 A3 EP1189132 A3 EP 1189132A3 EP 01307328 A EP01307328 A EP 01307328A EP 01307328 A EP01307328 A EP 01307328A EP 1189132 A3 EP1189132 A3 EP 1189132A3
Authority
EP
European Patent Office
Prior art keywords
processors
peripheral
shared
peripheral units
shared peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP01307328A
Other languages
German (de)
English (en)
Other versions
EP1189132A2 (fr
EP1189132B1 (fr
Inventor
Sonya Gary
Karen Tyger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of EP1189132A2 publication Critical patent/EP1189132A2/fr
Publication of EP1189132A3 publication Critical patent/EP1189132A3/fr
Application granted granted Critical
Publication of EP1189132B1 publication Critical patent/EP1189132B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658Controller construction arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0683Plurality of storage devices
    • G06F3/0689Disk arrays, e.g. RAID, JBOD

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
EP01307328A 2000-09-13 2001-08-29 Architecture de périphérique partagé Expired - Lifetime EP1189132B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US660577 2000-09-13
US09/660,577 US6662253B1 (en) 2000-09-13 2000-09-13 Shared peripheral architecture

Publications (3)

Publication Number Publication Date
EP1189132A2 EP1189132A2 (fr) 2002-03-20
EP1189132A3 true EP1189132A3 (fr) 2006-06-14
EP1189132B1 EP1189132B1 (fr) 2011-03-16

Family

ID=24650091

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01307328A Expired - Lifetime EP1189132B1 (fr) 2000-09-13 2001-08-29 Architecture de périphérique partagé

Country Status (4)

Country Link
US (2) US6662253B1 (fr)
EP (1) EP1189132B1 (fr)
JP (1) JP2002117002A (fr)
DE (1) DE60144211D1 (fr)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8671460B1 (en) * 2000-09-25 2014-03-11 Fisher-Rosemount Systems, Inc. Operator lock-out in batch process control systems
US7248597B2 (en) * 2001-05-02 2007-07-24 Nvidia Corporation General purpose input/output controller
US6931470B2 (en) * 2002-02-11 2005-08-16 Motorola, Inc. Dual access serial peripheral interface
GB2399917B (en) * 2002-03-19 2005-01-19 Sun Microsystems Inc Computer system
US7080188B2 (en) 2003-03-10 2006-07-18 Marvell International Ltd. Method and system for embedded disk controllers
US7039771B1 (en) 2003-03-10 2006-05-02 Marvell International Ltd. Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers
US7492545B1 (en) 2003-03-10 2009-02-17 Marvell International Ltd. Method and system for automatic time base adjustment for disk drive servo controllers
US7870346B2 (en) * 2003-03-10 2011-01-11 Marvell International Ltd. Servo controller interface module for embedded disk controllers
US20040181601A1 (en) * 2003-03-14 2004-09-16 Palsamy Sakthikumar Peripheral device sharing
TWI220476B (en) * 2003-03-18 2004-08-21 Aten Int Co Ltd Resources sharing device
US7412588B2 (en) 2003-07-25 2008-08-12 International Business Machines Corporation Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
US7353362B2 (en) * 2003-07-25 2008-04-01 International Business Machines Corporation Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus
US7590776B1 (en) * 2003-12-24 2009-09-15 Emc Corporation Data storage techniques utilizing host-side multiplexers
JP4233446B2 (ja) * 2003-12-25 2009-03-04 富士通マイクロエレクトロニクス株式会社 集積回路装置
JP4451687B2 (ja) * 2004-03-22 2010-04-14 株式会社日立製作所 ストレージシステム
JP4377279B2 (ja) * 2004-05-06 2009-12-02 株式会社日立製作所 ストレージシステム、コンピュータシステム、およびストレージシステムの設定方法
US8279886B2 (en) * 2004-12-30 2012-10-02 Intel Corporation Dataport and methods thereof
AU2006318607B2 (en) * 2005-11-21 2011-07-07 Nightgear Llc Seating accessory
US20080005749A1 (en) * 2006-06-01 2008-01-03 Broadcom Corporation, A California Corporation Hard disk controller having multiple, distributed processors
JP4233585B2 (ja) * 2006-07-25 2009-03-04 株式会社エヌ・ティ・ティ・ドコモ ペリフェラル切替装置及びペリフェラル切替制御装置
JP2008045507A (ja) * 2006-08-18 2008-02-28 Nikki Co Ltd 電磁燃料ポンプ
US7512723B2 (en) * 2006-12-29 2009-03-31 Freescale Semiconductor, Inc. Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system
US8589141B2 (en) * 2007-07-24 2013-11-19 Aten International Co., Ltd. Resource sharing apparatus which disconnects an input device when detecting a standby indication of a switching command
JP5217786B2 (ja) * 2008-08-27 2013-06-19 セイコーエプソン株式会社 リクエスト調停装置及びリクエスト調停方法
US8040631B2 (en) * 2009-05-18 2011-10-18 Seagate Technology Llc Servo processors that alternately control head positioning relative to sequential servo patterns
US8560750B2 (en) * 2011-05-25 2013-10-15 Lsi Corporation Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment
US8773789B1 (en) * 2013-02-14 2014-07-08 Lsi Corporation In-channel channel optimization for hard-disc drive read/write chips
US9704355B2 (en) * 2014-10-29 2017-07-11 Clover Network, Inc. Secure point of sale terminal and associated methods

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5974058A (en) * 1998-03-16 1999-10-26 Storage Technology Corporation System and method for multiplexing serial links
WO2000033201A1 (fr) * 1998-11-30 2000-06-08 Koninklijke Philips Electronics N.V. Interconnexion en serie simultanee pour l'integration de blocs fonctionnels dans un dispositif de circuits integres

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4796179A (en) * 1986-08-20 1989-01-03 Integrated Systems, Inc. Multirate real time control system code generator
US5182801A (en) * 1989-06-09 1993-01-26 Digital Equipment Corporation Apparatus and method for providing fast data transfer between multiple devices through dynamic reconfiguration of the memory space of the devices
US5408627A (en) * 1990-07-30 1995-04-18 Building Technology Associates Configurable multiport memory interface
US5617575A (en) * 1991-03-19 1997-04-01 Hitachi, Ltd. Interprocessor priority control system for multivector processor
JP2743608B2 (ja) * 1991-03-27 1998-04-22 日本電気株式会社 共有レジスタ制御方式
DE69230462T2 (de) 1991-11-19 2000-08-03 Sun Microsystems, Inc. Arbitrierung des Multiprozessorzugriffs zu gemeinsamen Mitteln
US5317749A (en) * 1992-09-25 1994-05-31 International Business Machines Corporation Method and apparatus for controlling access by a plurality of processors to a shared resource
JP3160149B2 (ja) * 1994-05-13 2001-04-23 株式会社日立製作所 ディスク制御装置の無停止プログラム変更方法およびディスク制御装置
US6438720B1 (en) * 1995-06-07 2002-08-20 Texas Instruments Incorporated Host port interface
US5678026A (en) * 1995-12-28 1997-10-14 Unisys Corporation Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues
US5907862A (en) * 1996-07-16 1999-05-25 Standard Microsystems Corp. Method and apparatus for the sharing of a memory device by multiple processors
US5889947A (en) * 1996-12-16 1999-03-30 International Business Machines Corporation Apparatus and method for executing instructions that select a storage location for output values in response to an operation count
US5922057A (en) * 1997-01-10 1999-07-13 Lsi Logic Corporation Method for multiprocessor system of controlling a dynamically expandable shared queue in which ownership of a queue entry by a processor is indicated by a semaphore
US5937428A (en) * 1997-08-06 1999-08-10 Lsi Logic Corporation Method for host-based I/O workload balancing on redundant array controllers
US6480952B2 (en) * 1998-05-26 2002-11-12 Advanced Micro Devices, Inc. Emulation coprocessor
US6378017B1 (en) * 1998-07-08 2002-04-23 Nms Communications Corporation Processor interconnection
JP3716126B2 (ja) * 1999-03-17 2005-11-16 株式会社日立製作所 ディスクアレイ制御装置及びディスクアレイ
US6499131B1 (en) * 1999-07-15 2002-12-24 Texas Instruments Incorporated Method for verification of crosstalk noise in a CMOS design
US6473821B1 (en) * 1999-12-21 2002-10-29 Visteon Global Technologies, Inc. Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5974058A (en) * 1998-03-16 1999-10-26 Storage Technology Corporation System and method for multiplexing serial links
WO2000033201A1 (fr) * 1998-11-30 2000-06-08 Koninklijke Philips Electronics N.V. Interconnexion en serie simultanee pour l'integration de blocs fonctionnels dans un dispositif de circuits integres

Also Published As

Publication number Publication date
JP2002117002A (ja) 2002-04-19
EP1189132A2 (fr) 2002-03-20
US20040088459A1 (en) 2004-05-06
DE60144211D1 (de) 2011-04-28
US6662253B1 (en) 2003-12-09
US6915367B2 (en) 2005-07-05
EP1189132B1 (fr) 2011-03-16

Similar Documents

Publication Publication Date Title
EP1189132A3 (fr) Architecture de périphérique partagé
FR2763136B1 (fr) Systeme et procede d'imagerie a ultrasons et carte-mere de multiplexeur utilisee dans ce systeme
EP0588084A3 (fr) Ordinateur portable ayant un groupe de registres dédicacés et un bus par contrÔleur périphérique entre le bus système et le contrÔleur périphérique.
SG85582A1 (en) Active matrix display device
DE69840039D1 (de) Bildanzeigesystem und Informationsverarbeitungseinrichtung mit Anzeige-Attributsteuerung, die spezifisch für einen bestimmten Anzeigebreich ist
BR9602518A (pt) Dispositivo de entrada periférica controlador joystick de trés eixos e montagem de rotor
GB2299434B (en) LED display device and its assembled structure
EP1296229A3 (fr) Mécanisme d'affichage des dépendances dans un pipeline avec réexécution et réacheminement d'instructions
EP0512840A3 (en) An active matrix display device
AU2802097A (en) Computer games having optically acquired images which are combined with computergenerated graphics and images
EP2273483A3 (fr) Dispositif d'affichage à matrice active et sa méthode de commande
EP1193591A3 (fr) Réseau de mémoire de données et procédé d'accès de données
HUP0201997A2 (en) Polymorphisms in the human mdr-1 gene and their use in diagnostic and therapeutic applications
GB2367368B (en) Method of displaying battery capacity using leds of the notebook computer system and the device of the same
JP2001276367A5 (fr)
DE59000136D1 (de) Bewehrungsanschluss sowie halter fuer einen bewehrungsanschluss.
KR0137108B1 (en) Bus driving system and integrated circuit device using the same
EP0753818A3 (fr) Processeur de données comprenant un circuit de commande de bus pour commander indépendemment une pluralité de bus
FR2750307B1 (fr) Dispositif de separation et d'affichage ainsi que le presentoir equipe de ce dispositif
Bushimata Trend and Problems in the Sociological Studies of Sentencing
TH75201S (th) หน่วยคำนวณและควบคุม
EP1615136A3 (fr) Dispositif USB avec consommation de courant réduite
KR950022127U (ko) 모니터의 메인기판과 주변기판 결합장치
AU5410198A (en) Display system in game parlor and display used therefor
Kim et al. The Spatial Structure of the Globular Cluster System in NGC 4472

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RIN1 Information on inventor provided before grant (corrected)

Inventor name: TYGER, KAREN

Inventor name: GARY, SONYA

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

17P Request for examination filed

Effective date: 20061206

AKX Designation fees paid

Designated state(s): DE FR GB IT

17Q First examination report despatched

Effective date: 20070131

RIN1 Information on inventor provided before grant (corrected)

Inventor name: TYGER, KAREN

Inventor name: GARY, SONYA

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 3/06 20060101ALN20101011BHEP

Ipc: G06F 15/16 20060101AFI20101011BHEP

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 60144211

Country of ref document: DE

Date of ref document: 20110428

Kind code of ref document: P

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 60144211

Country of ref document: DE

Effective date: 20110428

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20111219

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 60144211

Country of ref document: DE

Effective date: 20111219

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110316

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 60144211

Country of ref document: DE

Effective date: 20120301

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120301

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 16

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 17

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 18

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20180720

Year of fee payment: 18

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20180720

Year of fee payment: 18

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20190829

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190831

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190829