Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/04—Synchronising
  • H04N5/06—Generation of synchronising signals
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
  • H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will

Definitions

• the present invention relates generally to video signal processing and more particularly to a method and apparatus for selecting and presenting one or more different video syncs to a video system.
• the PC industry follows the VESA (Video Electronics Standards Association) standard for video synchronization, allowing one to buy a monitor and plug it into a different brand computer.
• VESA Video Electronics Standards Association
• a composite sync on green is used, eliminating the need for two extra wires.
• computer standards are becoming more commonplace in the military.
• the present invention allows both formats to be present simultaneously, with a programmable prioritization for use of a valid sync source with the highest priority.
• the invention automatically switches to the next highest priority valid sync source.
• This invention can be used to include other sync sources as well.
• the present technology allows for use of a single sync source with no alternative selection of secondary sync sources or automatic shifting of sync sources, if a failure to the primary sync source occurs.
• the present invention also allows both sync formats, VESA which is a separate horizontal and vertical sync, and a composite sync on green video.
• a preferred method of selecting a valid digital video sync source from at least two digital sync sources comprises the steps of independently determining a validity of the at least two digital sync sources, selecting the valid digital sync source with a highest priority and utilizing the valid digital sync source as an input to a video system.
• the preferred step of independently determining a validity of the at least two digital sync sources comprises independently determining whether each of the at least two digital sync sources is stuck high or stuck low.
• the step of independently determining a validity of the at least two digital sync sources also can comprise independently determining whether each of the at least two digital sync sources comprises a predetermined frequency.
• the step of independently determining a validity of the at least two digital sync sources can also comprise independently determining whether each of the at least two digital sync sources comprises a predetermined high time and a predetermined low time.
• the preferred step of selecting a valid digital sync source with a highest priority comprises a programmable selection.
• the preferred programmable selection comprises prioritizing each of the at least two digital sync sources, validating each of the at least two digital sync sources, and if a sync source with a highest priority is invalid, select a sync source with the next highest priority as the valid sync source.
• An alternative step of selecting a valid digital sync source with a highest priority comprises a manual selection.
• the preferred method further comprises the step of periodically repeating steps a), b) and c).
• the method can also further comprise the step of generating a signal when an invalid digital sync source is determined.
• the invention also comprises a method of selecting a valid digital video sync source from at least two digital sync sources comprising the steps of independently determining a validity of the at least two digital sync sources, selecting a valid digital sync source with a highest priority, automatically shifting to a next highest priority valid digital sync source if the highest priority sync source becomes invalid, utilizing the valid digital sync source with the highest priority as an input to a video system.
• the preferred apparatus for selecting a video sync source from at least two digital sync sources comprises structure for independently determining a validity of the at least two digital sync sources, an apparatus for prioritizing each of the at least two digital sync sources and structure for selecting a highest priority valid sync source from the at least two digital sync sources as the video sync source.
• the preferred invention further comprises an apparatus to automatically switch to a next highest priority sync source as the video sync source, if a highest priority sync source becomes invalid.
• the preferred structure for independently determining a validity of the at least two digital sync sources comprises a member from the group of ASIC, FPGA and EPLD.
• the structure for independently determining a validity of the at least two digital sync sources can also comprise structure for determining whether each of the at least two digital sync sources is stuck high or stuck low.
• the structure for independently determining a validity of the at least two digital sync sources can also comprise structure for determining whether each of the at least two digital sync sources comprises a predetermined frequency.
• the structure for independently determining a validity of the at least two digital sync sources can also comprise structure for determining whether each of the at least two digital sync sources comprises a predetermined high time and a predetermined low time.
• the invention can also further comprise a signal when each of the at least two digital sync sources is invalid.
• the invention also further comprises an apparatus to automatically switch from an invalid digital sync source to a next highest priority digital sync source.
• the invention also further comprises an apparatus to periodically activate the structure for independently determining a validity of the at least two digital sync sources.
• a primary object of this invention is to be as universal as possible, that is to accept as many commonly used formats as possible.
• Another object of the invention is to provide an apparatus that is transparent to the user. So if both sync sources are available, then use the primary, if the primary source is not available, then automatically switch to the secondary source if it is available.
• a primary advantage of the present invention is to provide commonality with the military standard and with the computer industry standard (VESA).
• Another advantage is that of redundancy, since this invention automatically switches from the primary sync source to the secondary sync source if the primary source becomes un-useable for any reason.
• FIG. 1 is a flow chart depicting the operation of the preferred automatic sync selector.
• Video sync for commercial computer monitors is standardized using VESA standards. This contains a separate vertical and horizontal sync signal. A loss of sync makes the system inoperable.
• Most military applications utilize a composite sync on green for displays. This composite sync was created and used to remove two wires for operation.
• this invention is necessary and also has the added advantage of creating a redundancy for an additional safeguard.
• FIG. 1 is a flow chart showing how the preferred invention operates.
• Composite video has the sync encoded along with the video.
• the composite sync 10 is detected and converted into a signal that is voltage compatible with the field programmable gate array (FPGA) or application specific integrated circuit (ASIC). This can be done using one of several methods well known in the art, such as Integrated Circuits or using a comparator.
• Separate H sync (VESA H Sync) 12 is buffered and level shifted if required to meet the required input level of the FPGA or ASIC.
• separate V sync (VESA V Sync) 14 is buffered and level shifted if required to meet the input level of the FPGA or ASIC.
• Composite sync 10 is sent to composite sync validation 16 to determine if the composite video sync is active and at approximately the correct timing.
• LOSJL (LOS_CS & !SSB) # (VESA_ACT & SSB);
• LOSS0 LOS_SR
• LOSSl LOSS0
• LOSS2 LOSSl
• LOSA.s LOSS0 & LOSS1 & LOSS2 & LOSS3;
• LOSS5 LOSS4
• LOSB.r ILOSS4 & ILOSS5 & ILOSS6 & ILOSS7;
• An output from the composite sync validation 16 indicating composite invalid sync 31 can be used to provide a signal elsewhere in the system to indicate a "Composite Loss Of Sync".
• H sync validation 18 determines whether H sync is valid. Stuck low or stuck high are checked and are invalid H sync 13 states. Approximate frequency and low time and high time can all be determined to aid in determining the validity of the signal as shown in FPGA horizonal sync validity equations 2.
• HVAA.s HVA0 & HVA1 & HVA2 & HVA3;
• HVAA.r IHVAO & !HVA1 & !HVA2 & !HVA3;
• V Sync validation 20 is performed to determine its validity. Stuck low or stuck high are checked and are invalid V sync 15 states. Approximate frequency and low time and high time can all be determined to aid in determining the validity of the signal as shown in FPGA vertical sync validity equations 3.
• VSVO VS_VESA
• VSV1 VSV0
• VSV2 VSV1;
• VSV_EDGE !VSV1 & VSV2; % FIND LEADING EDGE OF
• VV_RST !VSV_EDGE & VS3; % DELAY VV_ACT.r 1 CLK
• VVA2 VVA1
• VVA3 VVA2
• VVAA.s VVAO & VVA1 & VVA2 & VVA3;
• VVAA.r ! WAO & ! WA1 & !VVA2 & !VVA3;
• comparator 22 which is essentially an "and" gate.
• Valid comparator information 23 is passed onto programmable priority sync selection 26.
• An invalid comparator output 29 indicating invalid sync can be used elsewhere as a signal in the system to indicate a "VESA Loss Of Sync".
• Sync priority input 24 can be any number of commonly used interfaces.
• a peripheral connect interface (PCI) bus is an example of such a common interface in which the priority can be loaded.
• Valid composite sync 17 and valid comparator information 23 are both fed to programmable priority sync selection 26.
• the programmable priority sync selection 26 determines which sync input is valid, both, one or the other, or neither. The other input is where the priority is loaded from. If both syncs are valid 17 and 23 the sync source with the highest priority loaded from the sync priority input 24 is selected to be output 30 by multiplexer 28. If only composite sync is valid then composite sync is selected as the output 30 of the multiplexer 28, regardless of the priority. If only VESA sync is valid than VESA sync is selected as the output of the multiplexer 28, regardless of the priority.
• Multiplexer 28 is essentially a 2 to 1 multiplexer that has the composite sync 11 as one input and H sync 13 and V sync 15 as the other input.
• the output 30 is selected based upon the output of the programmable priority sync selection 26.
• This disclosure has described a system in which to two different sync formats are checked and the highest priority valid format is output to be used elsewhere in the system.
• the output in the implemented case is used by a phase locked loop (PLL) as the reference input.
• PLL phase locked loop
• this invention automatically switches to the secondary sync source. Two independent inputs must both fail before the system is unable to display the appropriate video.
• this invention can be used with two or more composite sync sources or two or more separate horizontal and vertical sync sources or any combination of these types of sync sources.
• the primary and secondary sources are programmable. As set forth in equations 1, 2, and 3.
• the primary source could be set as the separate syncs for one unit and set for the composite syncs for another unit.
• the selection of the primary source can be accomplished through methods well known in the art such as bezel buttons, a communications port or any other interface.
• RGB inputs with sync on green are becoming more common. This compatibility to legacy displays, supporting the current computer monitor standard VESA and supporting the higher performance RGB will have benefits.
• This display system quantized video at a pixel clock rate, 65MHz for this system.
• the clock must be stable and at the correct frequency, in order to properly quantize the video signal.
• a phase locked loop (PLL) was used to meet these requirements, however, there are other ways of meeting the requirement of a stable clock as well.
• the clock generator (PLL in this case) had as one input a valid sync reference from the video signal. The generation of the pixel clock is well known in the art. Once the stable pixel clock had been generated and was phase locked to the reference sync, this clock was used as the system clock and was used to create all control signals required for the display surface.
• VCS LCELL
• VBLNK_L SRFF
• HBP_L SRFF
• VVAA SRFF
• VBLNK_L.clk CLK
• HSYNC_L.clk CLK
• GB4 QX3; % 4MHz IN SYNC WITH VIDEO %
• RX RXA & RXB & RXC;
• YRY RYY3 & RYY2 & RYY1; % ALLOW VERTICAL RESET PULSE TO RESET Y COUNTER ONCE PER 15 LINES %
• RVO QYO & QY1 & QY2 & QY3;
• VBR.r YRY
• VBR.s RVO
• TPRY (FF_TP & LVS3) # (GS_TP & LVS3); % RESET Y CNTR WHEN IN TEST PATTERN %
• VB7 VB4 & VB5 & VB6 & CYE;
• VBLNK_L.r VB3;
• VBLNKJ s VB7;
• CBLNK L CHBL & VBLNK L;
• HS2 QX8 & !QX9 & QX10;
• HS3 HS0&HS1&HS2;
• HS4 !QX0 & !QX1 & QX2 & !QX3;
• HS5 !QX4 & !QX5 & !QX6 & QX7;
• HS6 !QX8 & !QX9 & IQX10;
• HS7 HS4 & HS5 & HS6;
• HSYNC_L.s HS3;
• VS3 VSO & VS1 & VS2 & CYE
• VS7 VS4 & VS5 & VS6 & CYE;
• CSL7 CSL4 & CSL5 & CSL6;
• BP3 BP0&BP1&BP2;
• BP7 BP4 & BP5 & BP6;
• LHB3 LHB0 & LHB1 & LHB2;
• LVS4 QYO & !QY1 & QY2 & !QY3;
• LVS5 !QY4 & !QY5 & !QY6 & !QY7;
• LVS6 !QY8&!QY9;
• LVS7 LVS4 & LVS5 & LVS6 & CYE;
• LOS_L (LOS_CS & !SSB) # (VESA_ACT & SSB);
• LOSA.s LOSS0 & LOSS1 & LOSS2 & LOSS3;
• LOSA.r ILOSSO & ILOSSl & ILOSS2 & 1LOSS3;
• LOSS4 !LOS_SR
• LOSS5 LOSS4
• LSS3 LSSO & LSS1 & LSS2 & IVSYNC;
• SSA SSO & SSI & SS2 & SS3; % FOUR FRAMES OF LOS ON
• HSVO HS VESA
• HSV1 HSVO
• HSV2 HSV1 ;
• HSV_EDGE IHSV1 & HSV2;
• HVAA.s HVAO & HVA1 & HVA2 & HVA3;
• HVAA.r IHVAO & IHVA1 & IHVA2 & IHVA3;
• VSV_EDGE IVSVl & VSV2; % FIND LEADING EDGE OF VS VESA %
• VV_RST !VSV_EDGE & VS3; % DELAY VV_ACT.r 1 CLK TO MATCH VVA[] .ena %
• VV_ACT.s VSVJEDGE
• VV_ACT.r VV_RST
• VV_EN % (VS3 & LOSJL) # %(VS3 & VV_ACT% & !LOS_L%);
• VVA3 VVA2
• WAA.s VVA0 & VVA1 & VVA2 & VVA3;
• VVAA.r IVVAO & IVVA1 & IVVA2 & IVVA3;
• VESA_ACT HVAA & VVAA

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Signal Processing (AREA)
• Television Systems (AREA)
• Synchronizing For Television (AREA)
• Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
• Controls And Circuits For Display Device (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=22836088

Family Applications (1)

Country Status (7)

Family Cites Families (4)

• 1999
  • 1999-12-14 JP JP2000593017A patent/JP2002534722A/ja not_active Withdrawn
  • 1999-12-14 EP EP99967287A patent/EP1169852A1/de not_active Withdrawn
  • 1999-12-14 KR KR1020017008449A patent/KR20020013829A/ko not_active Application Discontinuation
  • 1999-12-14 CA CA002358196A patent/CA2358196A1/en not_active Abandoned
  • 1999-12-14 IL IL14407999A patent/IL144079A0/xx unknown
  • 1999-12-14 WO PCT/US1999/029519 patent/WO2000041388A1/en not_active Application Discontinuation
  • 1999-12-17 TW TW088122298A patent/TW441187B/zh not_active IP Right Cessation

Non-Patent Citations (1)

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