CA2358196A1

CA2358196A1 - Automatic sync selector with programmable priority

Info

Publication number: CA2358196A1
Application number: CA002358196A
Authority: CA
Inventors: Kurt M. Conover
Original assignee: Honeywell Inc
Current assignee: Individual
Priority date: 1998-12-30
Filing date: 1999-12-14
Publication date: 2000-07-13
Also published as: EP1169852A1; JP2002534722A; IL144079A0; TW441187B; WO2000041388A1; KR20020013829A

Abstract

Two or more independent video sync sources are input along with a programmable priority or order for each sync source. The sync source with the highest priority that is valid is the output. This invention shall automatically switch the highest priority valid sync to the output. The priority associated with each independent sync source is programmable and can be changed or set differently with each unit.

Description

AUTOMATIC SYNC SELECTOR WITH PROGRAMMABLE PRIORITY
GOVERNMENT RIGHTS
The invention was made with United States Government support under Contract No. DAAE30-95-C-0009 awarded by the U.S. Army. The Government has certain rights to this invention.
BACKGROUND OF THE INVENTION
The present invention relates generally to video signal processing and more l0 particularly to a method and apparatus for selecting and presenting one or more different video syncs to a video system.
The PC industry follows the VESA (Video Electronics Standards Association) standard for video synchronization, allowing one to buy a monitor and plug it into a different brand computer. However, in most military systems a composite sync on 15 green is used, eliminating the need for two extra wires. As the commercialization of military hardware continues, computer standards are becoming more commonplace in the military. The present invention allows both formats to be present simultaneously, with a programmable prioritization for use of a valid sync source with the highest priority. In addition, if the selected sync source fails, the invention automatically 2o switches to the next highest priority valid sync source. This invention can be used to include other sync sources as well. The present technology allows for use of a single sync source with no alternative selection of secondary sync sources or automatic shifting of sync sources, if a failure to the primary sync source occurs. The present invention also allows both sync formats, VESA which is a separate horizontal and 25 vertical sync, and a composite sync on green video.
BRIEF SUMMARY OF THE INVENTION
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is 3o not intended to be a full description. A full appreciation of the various aspects of the invention can only be gained by taking the entire specification, claims, drawings, and abstract as a whole.

In accordance with the present invention there is provided a method and apparatus for selecting and prioritizing two or more video sync sources for use as a primary sync source as input to a video system. A preferred method of selecting a valid digital video sync source from at least two digital sync sources comprises the steps of independently determining a validity of the at least two digital sync sources, selecting the valid digital sync source with a highest priority and utilizing the valid digital sync source as an input to a video system. The preferred step of independently determining a validity of the at least two digital sync sources comprises independently determining whether each of the at least two digital sync sources is stuck high or stuck low. The step of independently determining a validity of the at least two digital sync sources also can comprise independently determining whether each of the at least two digital sync sources comprises a predetermined frequency. The step of independently determining a validity of the at least two digital sync sources can also comprise independently determining whether each of the at least two digital sync sources comprises a predetermined high time and a predetermined low time. The preferred step of selecting a valid digital sync source with a highest priority comprises a programmable selection.
The preferred programmable selection comprises prioritizing each of the at least two digital sync sources, validating each of the at least two digital sync sources, and if a sync source with a highest priority is invalid, select a sync source with the next highest 2o priority as the valid sync source. An alternative step of selecting a valid digital sync source with a highest priority comprises a manual selection. The preferred method further comprises the step of periodically repeating steps a), b) and c). The method can also further comprise the step of generating a signal when an invalid digital sync source is determined.
The invention also comprises a method of selecting a valid digital video sync source from at least two digital sync sources comprising the steps of independently determining a validity of the at least two digital sync sources, selecting a valid digital sync source with a highest priority, automatically shifting to a next highest priority valid digital sync source if the highest priority sync source becomes invalid, utilizing the 3o valid digital sync source with the highest priority as an input to a video system.
The preferred apparatus for selecting a video sync source from at least two digital sync sources comprises structure for independently determining a validity of the at least two digital sync sources, an apparatus for prioritizing each of the at least two digital sync sources and structure for selecting a highest priority valid sync source from the at least two digital sync sources as the video sync source. The preferred invention further comprises an apparatus to automatically switch to a next highest priority sync source as the video sync source, if a highest priority sync source becomes invalid. The preferred structure for independently determining a validity of the at least two digital sync sources comprises a member from the group of ASIC, FPGA and EPLD. The structure for independently determining a validity of the at least two digital sync sources can also comprise structure for determining whether each of the at least two digital sync sources is stuck high or stuck low. The structure for independently determining a validity of the at least two digital sync sources can also comprise structure for determining whether each of the at least two digital sync sources comprises a predetermined frequency. The structure for independently determining a validity of the at least two digital sync sources can also comprise structure for determining whether each of the at least two digital sync sources comprises a predetermined high time and a predetermined low time. The invention can also further comprise a signal when each of the at least two digital sync sources is invalid. The invention also further comprises an apparatus to automatically switch from an invalid digital sync source to a next highest priority digital sync source. The invention also further comprises an apparatus to periodically activate the structure for independently determining a validity of the at least two digital sync sources.
A primary object of this invention is to be as universal as possible, that is to accept as many commonly used formats as possible.
Another object of the invention is to provide an apparatus that is transparent to the user. So if both sync sources are available, then use the primary, if the primary source is not available, then automatically switch to the secondary source if it is available.
A primary advantage of the present invention is to provide commonality with the military standard and with the computer industry standard (VESA).
Another advantage is that of redundancy, since this invention automatically switches from the primary sync source to the secondary sync source if the primary source becomes un-useable for any reason.
Other objects, advantages and novel features, and further scope of applicability of the present invention will be set forth in part in the detailed description to follow, taken in conjunction with the accompanying drawings, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawing, which is incorporated into and form a part of the specification, illustrates the preferred embodiment of the present invention and, together 1o with the description, serves to explain the principles of the invention.
The drawing is only for the purpose of illustrating a preferred embodiment of the invention and is not to be construed as limiting the invention. In the drawings:
FIG. 1 is a flow chart depicting the operation of the preferred automatic sync selector.
DETAILED DESCRIPTION OF THE INVENTION
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in 2o the U. S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
Video sync for commercial computer monitors is standardized using VESA
standards. This contains a separate vertical and horizontal sync signal. A
loss of sync makes the system inoperable. Most military applications utilize a composite sync on green for displays. This composite sync was created and used to remove two wires for operation. However, in order to utilize off the-shelf monitors or displays for military applications, this invention is necessary and also has the added advantage of creating a redundancy for an additional safeguard.
FIG. l, is a flow chart showing how the preferred invention operates.
Composite video has the sync encoded along with the video. The composite sync 10 is detected and converted into a signal that is voltage compatible with the field programmable gate array (FPGA) or application specific integrated circuit (ASIC). This can be done using one of several methods well known in the art, such as Integrated Circuits or using a _ _5_ comparator. Separate H sync (VESA H Sync) 12 is buffered and level shifted if required to meet the required input level of the FPGA or ASIC. In addition, separate V
sync (VESA V Sync) 14 is buffered and level shifted if required to meet the input level of the FPGA or ASIC. Composite sync 10 is sent to composite sync validation 16 to determine if the composite video sync is active and at approximately the correct timing.
This is accomplished in an FPGA, an ASIC or other technology can be used as well. If the FPGA or ASIC determines if the signal is stuck low or stuck high, both are invalid states for composite sync 11. If composite sync is toggling, an approximate determination of low time versus high time and/or a frequency measurement can be 1o made to help in determining validity. The level of checking for determination of validity on the composite sync input is defined by system requirements as shown in FPGA validity equations 1.
LOSS OF SYNC % (1) LOS L = (LOS CS & !SSB) # (VESA ACT & SSB);
EDO = !CS;
ED 1 = EDO;
ED2 = ED 1;
CSEDGE = !ED1 & ED2; % LEADING EDGE OF CS
LOS SR.r = CSEDGE;
LOS SR.s = CSL7; % RISING EDGE OF CSPLL
LOSS[3..0].ena = HB3; % ENABLED ON FALLING EDGE OF
HBLANK
LOSSO = LOS SR;
LOSS1 =LOSSO;
3o LOSS2 = LOSS1;
LOSS3 = LOSS2;
LOSA.s = LOSSO & LOSSl & LOSS2 & LOSS3;
LOSA.r = !LOSSO & !LOSSI & !LOSS2 & !LOSS3;

LOSS[7..4].ena = LSS3; % ENABLED IN MIDDLE OF ACTIVE
SYNC
LOSS4 = !LOS SR;
LOSSS = LOSS4;
LOSS6 = LOSSS;
LOSS7 = LOSS6;
LOSB.s = LOSS4 & LOSSS & LOSS6 & LOSS7;
LOSB.r = !LOSS4 & !LOSSS & !LOSS6 & !LOSS7;
l0 LOSC = LOSA & LOSB;
LOS CS.r = !LOSC;
LOS CS.s = LOSC & VS3;
% LOSS OF SYNC ENABLE AT 64 LSSO = !QXO & !QXl & !QX2 & !QX3;
LSSI = !QX4 & !QXS & QX6 & !QX7;
LSS2 = !QX8 & !QX9 & !QX10;
LSS3 = LSSO & LSSl & LSS2 & !VSYNC;
An output from the composite sync validation 16 indicating composite invalid sync 31 can be used to provide a signal elsewhere in the system to indicate a "Composite Loss Of Sync".
Separate H sync validation 18 determines whether H sync is valid. Stuck low or stuck high are checked and are invalid H sync 13 states. Approximate frequency and low time and high time can all be determined to aid in determining the validity of the signal as shown in FPGA horizonal sync validity equations 2.
DETERMINE IF HS VESA IS ACTIVE % (2) 3o HSVO = HS VESA;
HSV 1 = HSVO;
HSV2 =HSV1;

HSV EDGE = !HSV1 & HSV2;
HV ACT.s = HSV EDGE;
HV ACT.r = !HSV_EDGE & RX;
HVA[].ena = RX;
HVAO = HV ACT;
HVAl = HVAO;
HVA2 = HVAI;
to HVA3 = HVA2;
HVAA.s = HVAO & HVA1 & HVA2 & HVA3;
HVAA.r = !HVAO & !HVA1 & !HVA2 & !HVA3;
Similarly, separate V Sync validation 20 is performed to determine its validity. Stuck low or stuck high are checked and are invalid V sync 15 states. Approximate frequency and low time and high time can all be determined to aid in determining the validity of the signal as shown in FPGA vertical sync validity equations 3.
% DETERMINE IF VS VESA IS ACTIVE % (3) VSVO = VS VESA;
VSVl = VSVO;
VSV2 = VSV l;
VSV EDGE = !VSVI & VSV2; % FIND LEADING EDGE OF
VS VESA
VV RST = !VSV EDGE & VS3; % DELAY VV ACT.r 1 CLK
TO MATCH VVA[].ena VV ACT.s = VSV EDGE;
VV ACT.r = VV RST;

_g_ VV EN = % (VS3 & LOS L) # %(VS3 & VV ACT% & !LOS L%);
VVA[].ena = VV EN;
VVAO = VV ACT;
s VVAI = VVAO;
VVA2 = VVA1;
VVA3 = VVA2;
VVAA.s = VVAO & VVA1 & VVA2 & VVA3;
1o VVAA.r= !VVAO & !VVAI & !VVA2 & !VVA3;
Again, the level of checking for determination of validity on the separate syncs is defined by system requirements.
When both valid separate H sync 19 and valid separate V sync 21 are 15 determined, the information is sent to comparator 22 which is essentially an "and" gate.
Valid comparator information 23 is passed onto programmable priority sync selection 26. An invalid comparator output 29 indicating invalid sync can be used elsewhere as a signal in the system to indicate a "VESA Loss Of Sync".
Sync priority input 24 can be any number of commonly used interfaces. A
2o peripheral connect interface (PCI) bus is an example of such a common interface in which the priority can be loaded.
Valid composite sync 17 and valid comparator information 23 are both fed to programmable priority sync selection 26. The programmable priority sync selection 26 determines which sync input is valid, both, one or the other, or neither. The other input 25 is where the priority is loaded from. If both syncs are valid 17 and 23 the sync source with the highest priority loaded from the sync priority input 24 is selected to be output 30 by multiplexer 28. If only composite sync is valid then composite sync is selected as the output 30 of the multiplexer 28, regardless of the priority.
If only VESA
sync is valid than VESA sync is selected as the output of the multiplexer 28, regardless 30 of the priority. If neither sync is valid, depending upon system requirements, the invalid sync with the highest priority could be output by the multiplexer 30 and the system could wait for a valid input from one of the sources. There are many other options, e.g.

on some systems an internal source can be available such that information can be displayed to indicate the display is functioning properly. Multiplexer 28 is essentially a 2 to 1 multiplexer that has the composite sync 11 as one input and H sync 13 and V sync 15 as the other input. The output 30 is selected based upon the output of the programmable priority sync selection 26.
This disclosure has described a system in which to two different sync formats are checked and the highest priority valid format is output to be used elsewhere in the system. The output in the implemented case is used by a phase locked loop (PLL) as the reference input. However this could easily be modified to any number of different sync inputs each with a unique and programmable priority. This also allows for redundancy in a system. First of all, if the primary sync source fails, this invention automatically switches to the secondary sync source. Two independent inputs must both fail before the system is unable to display the appropriate video.
Although only describing separate horizontal and vertical sync and composite sync, this invention can be used with two or more composite sync sources or two or more separate horizontal and vertical sync sources or any combination of these types of sync sources.
The primary and secondary sources are programmable. As set forth in equations l, 2, and 3. The primary source could be set as the separate syncs for one unit and set for the composite syncs for another unit. The selection of the primary source can be 2o accomplished through methods well known in the art such as bezel buttons, a communications port or any other interface. As computer monitors move towards higher performance with higher resolution, RGB inputs with sync on green are becoming more common. This compatibility to legacy displays, supporting the current computer monitor standard VESA and supporting the higher performance RGB will have benefits.
Industrial Applicability:
The invention is further illustrated by the following non-limited example. An example for an entire system is set forth in equations 4. The "Automatic Sync Selector with Programmable Priority" was used in a display system which had two sync inputs.
This display system quantized video at a pixel clock rate, 65MHz for this system. The clock must be stable and at the correct frequency, in order to properly quantize the video signal. A phase locked loop (PLL) was used to meet these requirements, however, there are other ways of meeting the requirement of a stable clock as well. The clock generator (PLL in this case) had as one input a valid sync reference from the video signal. The generation of the pixel clock is well known in the art. Once the stable pixel clock had been generated and was phase locked to the reference sync, this clock was used as the system clock and was used to create all control signals required for the display surface.
TITLE "PLL FEEDBACK"; (4) SUBDESIGN PLLFB
CS, HS VESA, VS VESA, FF TP, GS TP, PCLK, OCLK, CLKIN
INPUT;
CLKOUT, PLLSYNC, QX[ 10..0], QY[9..0], EVEN L, RX, BITEN
OUTPUT;
TPKNT, CBLNK L, RY, VBLNK L, HBLNK L, HBP_L, HSYNC L
OUTPUT;
VSYNC, CSYNC L, GB4, LHSYNC L, LVSYNC L, ENAB, LOS L, SSB
OUTPUT;
2o LOS CS, VVAA, VV EN, SSA
VARIABLE
CLK : GLOBAL;
********** CLOCK MUX **********
CLKOUT :LCELL;
********** X counter ********** oho 3o QX[10..0] : DFF;
CX[10..0] : CARRY;
RX : DFF;
RXA, RXB, RXC : DFF;

GB4 : DFF;
% ********** Y counter **********
%

QY[9..0] : DFFE;

CY[9..0] : CARRY;

CYE : DFF;

RY, TPRY : DFF;

**** VERTICAL SYNC DETECTOR ***

RYY[3..0] : DFFE;

to RRYY, YRY, RVO : DFF;

VBR : SRFF;

CRY[3..0] : CARRY;

CRYY, CRYYA : DFF;

VCS : LCELL;

**** H, V AND CSYNC FOR
PLL ****

PLLSYNC : LCELL;

PLLS : LCELL;

HSYNC L : SRFF;

2o HS[7..0] : DFF;

VSYNC : SRFF;

VS[7..0] : DFF;

CSYNC_L : DFF;

CSSR : SRFF;

CSL[7..0] : DFF;

**** H AND V BLANK ****
HBLNK_L, CHBL : SRFF;
HB [7..0] : DFF;
3o VBLNK L : SRFF;
VB[7..0] : DFF;
CBLNK_L : DFF;

**** BACK PORCH ****
HBP L : SRFF;
BP[7..0] : DFF;
% **** LVDS CONTROL ****
EVEN L : DFF;
LHSYNC L : SRFF;
LHS [7..0] : DFF;
LVSYNC L : SRFF;
1o LVS[7..0] : DFF;
LHBLNK L : SRFF;
LHB[7..0] : DFF;
LCHBL : SRFF;
ENAB : DFF;
**** LOSS OF SYNC ****

LOS L : DFF;

ED[2..0] : DFF;

CSEDGE : DFF;

2o LOS SR : SRFF;

LOSS[7..0] : DFFE;

LOSA, LOSB : SRFF;

LOSC : DFF;

LOS CS :SRFF;

LSS[3..0] : DFF;

SS[3..0] : DFFE;

SSA, SSB : DFF;

HSV[2..0] : DFF;

HSV EDGE : DFF;

3o HV ACT : SRFF;

HVA[3..0] : DFFE;

HVAA : SRFF;

VSV[2..0] : DFF;

VSV EDGE : DFF;

V V ACT : SRFF;

VVA[3..0] : DFFE;

VVAA : SRFF;

VESA ACT : DFF;

VV EN, VV RST : DFF;

TEST PATTERNS AND BIT
TPKNT : DFF;
1o BITEN : SRFF;
BIT[7..0] : DFF;
BEGIN
set all register clocks CLK = CLKIN;
clocks QX[].clk = CLK;

RX.clk = CLK;

2o RXA.cIk = CLK;

RXB.cIk = CLK;

RXC.cIk = CLK;

GB4.clk = CLK;

QY[].clk = CLK;

CYE.cIk = CLK;

RY.clk = CLK;

RYY[].clk = CLK;

RRYY.cIk = CLK;

CRYY.cIk = CLK;

CRYYA.cIk = CLK;

YRY.cIk = CLK;

VBR.cIk = CLK;
RVO.cIk = CLK;
TPRY.cIk = CLK;
CBLNK-L.clk = CLK;

VBLNK_L.clk = CLK;

VB[].clk = CLK;

HBLNK L.clk = CLK;

HB[].clk = CLK;

1o CHBL.cIk = CLK;

HSYNC L.clk = CLK;

HS[].clk = CLK;

VSYNC.cIk = CLK;

VS[].clk = CLK;

CSYNC_L.clk = CLK;

CSSR.cIk = CLK;

CSL[].clk = CLK;

2o HBP_L.clk = CLK;

BP[].clk = CLK;

EVEN L.clk = CLK;

LHSYNC_L.clk = CLK;

LHS[].clk = CLK;

LVSYNC L.clk = CLK;

LVS[].clk = CLK;

LHBLNK L.clk = CLK;

LHB[].clk = CLK;

3o LCHBL.cIk = CLK;

ENAB.cIk = CLK;

LOS L.clk = CLK;

WO 0_0/41388 PCT/US99/29519 ED[].clk = CLK;

CSEDGE.cIk = CLK;

LOS SR.clk = CLK;

LOSS[].clk = CLK;

s LOSA.cIk = CLK;

LOSB.cIk = CLK;

LOSC.cIk = CLK;

LOS CS.clk = CLK;

LSS[].clk = CLK;

SS[].clk = CLK;

SSA.cIk = CLK;

SSB.cIk = CLK;

HSV[].clk = CLK;

HSV EDGE.cIk = CLK;

1s HV ACT.cIk = CLK;

HVA[].clk = CLK;

HVAA.cIk = CLK;

VSV[].clk = CLK;

VSV EDGE.cIk = CLK;

2o VV ACT.cIk = CLK;

VVA[].clk = CLK;

VVAA.cIk = CLK;

VV EN.clk = CLK;

VV RST.cIk = CLK;

2s VESA ACT.cIk = CLK;

TPKNT.cIk = CLK;

BITEN.cIk = CLK;

BIT[].clk = CLK;

MUX BETWEEN CLOCKS, SO TEST PATTERN CAN BE DISPLAYED
WITHOUT SYNC
CLKOUT = (PCLK & !FF TP & !GS_TP) # (OCLK & FF_TP) # (OCLK & GS TP);
SWITCH BETWEEN COMP SYNC AND HORIZONTAL SYNC FOR PLL
REFERENCE
PLLS = (CS & !VSYNC & !SSB) # (!CSSR & VSYNC & !SSB);
PLLSYNC = PLLS # (!HS_VESA & SSB);
Horizontal line length counter 1344 clocks per line Qx[lo..o] _ (!Rx & Qx[lo..o]) $ (!Rx & Cx[lo..o]);
1o GB4 = QX3; % 4MHz IN SYNC WITH VIDEO
HORIZONTAL CARRY CHAIN
CXO = VCC;
CX[10..1] = CX[9..o] & QX[9..0];

RXA = QX[3..0] _= H"D";

RXB = QX[7..4] _= H"3";

RXC = QX[10..8]= H"5";

RX = RXA & RXB & RXC;

CYE = RXA & RXB & RXC;

SWITCH BETWEEN COMP SYNC AND VERTICAL SYNC
VCS = (CS & !SSB) # (!VS VESA & SSB);
% Vertical line counter QY[].ena = CYE;
QY[] = QY[] $ CY[];
QY[].clrn = !RY;
3o % VERTICAL CARRY CHAIN
CYO = VCC;
CY[9..1 ] = CY[8..0] & QY[8..0];

_. -17-VERTICAL SYNC DETECTOR
RYY[].ena = CRYY; % COUNT EVERY O.SuS THAT CS IS ACTIVE
VERTICAL SYNC DET COUNTER
RYY[] _ (RYY[]) $ (CRY[]);
RYY[].clrn = !RRYY;
VERTICAL SYNC DET COUNTER CARRY CHAIN
CRYO = VCC;
CRY[3..1] = CRY[2..0] & RYY[2..0];
l0 % DECODE X COUNTER FOR O.SuS
CRYYA = !QXO & !QX1 & !QX2 & !QX3;
CRYY = !QX4 & CRYYA & VCS;
RESET V SYNC COUNTER WHEN CS IN INACTIVE
RRYY = !QX4 & CRYYA & !VCS;
% WHEN CS IS ACTIVE FOR 7uS GENERATE RESET PULSE
YRY = RYY3 & RYY2 & RYY 1;
ALLOW VERTICAL RESET PULSE TO RESET Y COUNTER ONCE

RVO = QYO & QYl & QY2 & QY3;
VBR.r = YRY;
VBR.s = RVO;
TPRY = (FF TP & LVS3) # (GS TP & LVS3); % RESET Y CNTR
WHEN IN TEST PATTERN
RY = (YRY & VBR) # TPRY;

HBO = QX[3..0] _=
H"3";

HBl= QX[7..4]==H"3";

HB2 = QX[10..8] _=
H"5";

HB3 = HBO & HB 1 & HB2;

_18_ HB4 = QX[3..0] =
H"3";

HB5 = QX[7..4] _=
H"3";

HB6=QX[10..8] _=H"1";

HB7 = HB4 & HB5 &
HB6;

HBLNK_L.r = HB3;
HBLNK L.s = HB7;

1o VBO = QY[3..0] _= H"2";

VB 1 = QY[7..4] = H"2";

VB2 = QY[9..8] _= H"3";

VB3 = VBO & VBl & VB2 & CYE;

VB4 = QY[3..0] _= H"2";

VB5 = QY[7..4] = H"2";

VB6 = QY[9..8] _= H"0";

VB7 = VB4 & VBS & VB6 & CYE;

VBLNK L.r = VB3;
VBLNK-L.s = VB7;
COMPOSITE BLANK INTERVAL
CHBL.r = HB3;
CHBL.s = HB7;
CBLNK L = CHBL & VBLNK L;

HSO = !QXO & QXl & QX2 & QX3;
3o HS 1 = QX4 & QX5 & ! QX6 & ! QX7;
HS2 = QX8 & !QX9 & QX10;
HS3 = HSO & HS 1 & HS2;
HS4 = ! QXO & ! QX 1 & QX2 & ! QX3;

HSS = ! QX4 & ! QXS & ! QX6 & QX7;
HS6 = !QX8 & !QX9 & !QX10;
HS7 = HS4 & HSS & HS6;
HSYNC L.r = HS7;
HSYNC_L.s = HS3;

VSO = QYO & !QY1 & !QY2 & !QY3;
1 o V S l = ! QY4 & ! QYS & ! QY6 & ! QY7;
VS2 = !QY8 & !QY9;
VS3 = VSO & VSl & VS2 & CYE;
VS4 = QYO & !QY1 & QY2 & !QY3;
VSS = !QY4 & !QYS & !QY6 & !QY7;
VS6 = !QY8 & !QY9;
VS7 = VS4 & VSS & VS6 & CYE;
VSYNC.r = VS7;
2o VSYNC.s = RY;

CSLO = QXO & !QX1 & QX2 & QX3;
CSL1 = QX4 & QXS & !QX6 & !QX7;
2s CSL2 = QX8 & !QX9 & QX10;
CSL3 = CSLO & CSL1 & CSL2;
CSL4 = !QXO & !QXl & QX2 & QX3;
CSLS = ! QX4 & ! QXS & ! QX6 & ! QX7;
3o CSL6 = !QX8 & QX9 & !QX10;
CSL7 = CSL4 & CSLS & CSL6;
CSSR.r = CSL3;

WO 0_0/41388 PCT/US99/29519 CSSR.s = CSL7;
PLL FEEDBACK IS H AND V WHEN CS IS USED, H WHEN HS VESA
IS USED
CSYNC L = (!CSSR & !SSB) # (!CSSR & SSB);
BACK PORCH INTERVAL RESET AT 144, SET AT 273 BPO = QX[3..0] _=
H"0";

BP1 = QX[7..4] = H"9";

BP2 = QX[10..8] -H"0";

BP3 = BPO & BPl & BP2;

BP4 = QX[3..0] _= H" 1";
BPS = QX[7..4] _= H" 1 ";
BP6 = QX[10..8] _= H"1";
BP7 = BP4 & BPS & BP6;
HBP L.r = BP3 & LVSYNC L;
HBP L.s = BP7;
LVDS CONTROL
EVEN L = QXO; % ODD PIXEL IS FIRST PIXEL DISPLAYED

LHBO = QX[3..0]= H"D";
_ LHB = QX[7..4]= H"3";
1 _ LHB2 = QX[10..8]= H"5";
_ LHB3 = LHBO
& LHB1 & LHB2;

LHB4 = QX[3..0]= H"D";
_ LHBS = QX[7..4]= H"3";
_ LHB6 = QX[ = H" 1 10..8] ";
_ _ -21-LHB7 = LHB4 & LHBS & LHB6;
LHBLNK L.r = LHB3;
LHBLNK L.s = LHB7;
LVDS COMPOSITE BLANK INTERVAL, ENAB
LCHBL.r = LHB3;
LCHBL.s = LHB7;
ENAB = LCHBL & VBLNK L;

LHSO = QX[3..0] _=
H"2";

LHS 1 = QX[7..4] = H"
1 ";

LHS2 = QX[10..8] ---H"0";

LHS3 = LHSO & LHS 1 & LHS2;

LHS4 = QX[3..0] _=
H"8";

LHSS = QX[7..4] _=
H"9";

LHS6 = QX[10..8] _=
H"0";

2o LHS7 = LHS4 & LHSS
& LHS6;

LHSYNC L.r = LHS3;
LHSYNC L.s = LHS7;
% LVDS VERTICAL SYNC INTERVAL RESET AT 805 SET AT 5 LVSO = QYO & !QY1 & QY2 & !QY3;
LV S 1 = ! QY4 & QY5 & ! QY6 & ! QY7;
LVS2 = QY8 & QY9;
LVS3 = LVSO & LVSl & LVS2 & CYE;
LVS4 = QYO & !QY1 & QY2 & !QY3;
LVSS = !QY4 & !QY5 & !QY6 & !QY7;
LVS6 = !QY8 & !QY9;

LVS7 = LVS4 & LVSS & LVS6 & CYE;
LVSYNC L.r = LVS3;
LVSYNC L.s = LVS7;
LOSS OF SYNC
LOS L = (LOS CS & !SSB) # (VESA_ACT & SSB);
EDO = !CS;
1 o ED 1 = EDO;
ED2 = EDI;
CSEDGE = !ED1 & ED2; % LEADING EDGE OF CS
LOS SR.r = CSEDGE;
LOS SR.s = CSL7; % RISING EDGE OF CSPLL
LOSS[3..0].ena = HB3; % ENABLED ON FALLING EDGE OF
HBLANK
LOSSO = LOS SR;
LOSSI =LOSSO;
LOSS2 = LOSS1;
LOSS3 = LOSS2;
LOSA.s = LOSSO & LOSS1 & LOSS2 & LOSS3;
LOSA.r = !LOSSO & !LOSS1 & !LOSS2 & !LOSS3;
LOSS[7..4].ena = LSS3; % ENABLED IN MIDDLE OF ACTIVE
SYNC
LOSS4 = !LOS SR;
3o LOSSS = LOSS4;
LOSS6 = LOSSS;
LOSS7 = LOSS6;
LOSB.s = LOSS4 & LOSSS & LOSS6 & LOSS7;

LOSB.r = !LOSS4 & !LOSSS & !LOSS6 & !LOSS7;
LOSC = LOSA & LOSB;
LOS CS.r = !LOSC;
LOS CS.s = LOSC & VS3;

LSSO = !QXO & !QX1 & !QX2 & !QX3;
LS S 1 = ! QX4 & ! QXS & QX6 & ! QX7;
1o LSS2 = !QX8 & !QX9 & !QX10;
LSS3 = LSSO & LSSl & LSS2 & !VSYNC;
SYNC SELECT
SS[].ena = VS3;
SSO = !LOS CS;
SSl = SSO;
SS2 = SS1;
SS3 = SS2;
2o SSA = SSO & SS1 & SS2 & SS3; % FOUR FRAMES OF LOS ON
COMP SYNC
SSB = SSA & VESA ACT; % SELECT COMP SYNC WHEN LOW
% DETERMINE IF HS VESA IS ACTIVE
HSVO = HS VESA;
HSVl =HSVO;
HSV2 = HSVl;
3o HSV EDGE = !HSV1 & HSV2;
HV ACT.s = HSV EDGE;
HV ACT.r = !HSV EDGE & RX;

WO 0_0/41388 PCT/US99/29519 HVA[].ena = RX;
HVAO = HV ACT;
HVA1 = HVAO;
HVA2 = HVAI;
HVA3 = HVA2;
HVAA.s = HVAO & HVAI & HVA2 & HVA3;
HVAA.r = !HVAO & !HVAI & !HVA2 & !HVA3;
l0 DETERMINE IF VS VESA IS ACTIVE
VSVO = VS VESA;
VSV1 = VSVO;
VSV2 = VSV1;
VSV EDGE = !VSV1 & VSV2; % FIND LEADING EDGE OF
VS VESA
VV RST = !VSV EDGE & VS3; % DELAY VV ACT.r 1 CLK
2o TO MATCH VVA[].ena VV ACT.s = VSV EDGE;
VV ACT.r = VV RST;
VV EN = % (VS3 & LOS L) # %(VS3 & VV ACT% & !LOS L%);
VVA[].ena = VV EN;
VVAO = VV ACT;

VVAI = VVAO;

3o VVA2 = VVA1;

VVA3 = VVA2;

VVAA.s = VVAO & VVAl & VVA2 & VVA3;

WO 0_0/41388 PCT/US99/29519 VVAA.r= !VVAO & !VVA1 & !VVA2 & !VVA3;
VESA ACT = HVAA & VVAA;
% TEST PATTERN COUNT ENABLE
TPKNT = QX[3..0] _= H"0";
BITEN.s = BIT3;
BITEN.r = BIT7;
l0 BITO = !QYO & !QY1 & !QY2 & !QY3;
BIT 1 = ! QY4 & ! QYS & ! QY6 & ! QY7;
BIT2 = !QY8 & !QY9;
BIT3 = BITO & BIT1 & BIT2 & CYE;
BIT4 = !QYO & QY1 & !QY2 & !QY3;
BITS = ! QY4 & ! QYS & ! QY6 & ! QY7;
BIT6 = !QY8 & !QY9;
BIT7 = BIT4 & BITS & BIT6 & CYE;
END;
The preceding example can be repeated with similar success by substituting the generically or specifically described reactants and/or operating conditions of this invention for those used in the preceding example.
Although the invention has been described in detail with particular reference to these preferred embodiments, other embodiments can achieve the same results.
Other variations and modifications of the present invention will be apparent to those of skill in the art, and it is the intent of the appended claims that such variations and modifications be covered. The particular values and configurations discussed above can be varied and are cited merely to illustrate a particular embodiment of the present invention and are not intended to limit the scope of the invention. It is contemplated that the use of the present invention can involve components having different characteristics as long as the principle of the invention is followed. It is intended that the scope of the present invention be defined by the claims appended hereto.

Claims

-27- The embodiments of an invention in which an exclusive property or right is claimed are defined as follows:

1. A method of selecting a valid digital video sync source from at least two digital sync sources, the method comprising the steps of:
a) independently determining a validity of the at least two digital sync sources;
b) selecting the valid digital sync source with a highest priority; and c) utilizing the valid digital sync source as an input to a video system.

2. The method of Claim 1 wherein the step of independently determining a validity of the at least two digital sync sources comprises independently determining whether each of the at least two digital sync sources is stuck high or stuck low.

3. The method of Claim 1 wherein the step of independently determining a validity of the at least two digital sync sources comprises independently determining whether each of the at least two digital sync sources comprises a predetermined frequency.

4. The method of Claim 1 wherein the step of independently determining a validity of the at least two digital sync sources comprises independently determining whether each of the at least two digital sync sources comprises a predetermined high time and a predetermined low time.

5. The method of Claim 1 wherein the step of selecting a valid digital sync source with a highest priority comprises a programmable selection.

6. The method of Claim 5 wherein the programmable selection comprises prioritizing each of the at least two digital sync sources, validating each of the at least two digital sync sources, and if a sync source with a highest priority is invalid, select a sync source with the next highest priority as the valid sync source.

7. The method of Claim 1 wherein the step of selecting a valid digital sync source with a highest priority comprises a manual selection.

8. The method of Claim 1 further comprising the step of periodically repeating steps a), b) and c).

9. The method of Claim 1 further comprises the step of generating a signal when an invalid digital sync source is determined.

10. A method of selecting a valid digital video sync source from at least two digital sync sources, the method comprising the steps of independently determining a validity of the at least two digital sync sources;
selecting a valid digital sync source with a highest priority;
automatically shifting to a next highest priority valid digital sync source if the highest priority sync source becomes invalid; and utilizing the valid digital sync source with the highest priority as an input to a video system.

11. An apparatus for selecting a video sync source from at least two digital sync sources comprising:
a means for independently determining a validity of said at least two digital sync sources;
a means for prioritizing each of said at least two digital sync sources; and structure for selecting a highest priority valid sync source from said at least two digital sync sources as said video sync source.

12. The invention of Claim 11 further comprising a means to automatically switch to a next highest priority sync source as said video sync source, if a highest priority sync source becomes invalid.

13. The invention of Claim 11 wherein said means for independently determining a validity of said at least two digital sync sources comprises a member from the group consisting of ASIC, FPGA and EPLD and combinations thereof.

14. The invention of Claim 11 wherein the means for independently determining a validity of said at least two digital sync sources comprises a means of determining whether each of said at least two digital sync sources is stuck high or stuck low.

15. The invention of Claim 11 wherein the means of independently determining a validity of said at least two digital sync sources comprises a means of determining whether each of said at least two digital sync sources comprises a predetermined frequency.

16. The invention of Claim 11 wherein the means of independently determining a validity of said at least two digital sync sources comprises a means of determining whether each of said at least two digital sync sources comprises a predetermined high time and a predetermined low time.

17. The invention of Claim 11 further comprises a signal when each of said at least two digital sync sources is invalid.

18. The invention of Claim 11 further comprises a means to automatically switch from an invalid digital sync source to a next highest priority digital sync source.

19. The invention of Claim 11 further comprising a means to periodically activate said means for independently determining a validity of the at least two digital sync sources.