JPS6180195A - Video signal receiving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal receiving circuit for accurately receiving a display data signal in a video signal.

[Prior Art] In recent years, the price of small computer systems has been reduced, and personal computers for home use have also appeared. Along with this, CRT display devices have conventionally been connected to a dedicated device and have a dedicated interface with the display device, but due to the high price, low-priced systems are not suitable for general households. TV receiver for computer system CRT
It is often used as a display device.

In such a small computer system, a horizontal synchronization signal (hereinafter referred to as H5YNC), a vertical synchronization signal (hereinafter referred to as VSYNC), and a display data signal (R .

It is common to use an RF-modulated video signal (video composite signal) in which H3YNC and VSYNC and display data signals (R, G , B) and other video signals (video separator signals) that are separated and output are used. For this reason, a small computer system has a built-in interface for outputting control data to be displayed as a video signal for interfacing with the television receiver.

On the other hand, when a CRT image is printed by a video printer through this interface, it becomes necessary to store display data in this video signal.

Here, the display data often corresponds directly to the pixels of the video printer on a one-to-one basis. Therefore, accurate printing cannot be achieved unless the video signal is accurately received.

In order to accomplish this, an accurate reception synchronization clock signal (hereinafter referred to as dot clock) for receiving the display data signal was required. However, generally this dot clock is not output, and this signal must be generated by a receiving device such as a printer.

Conventionally, the following methods have been mainly used to generate this clock signal.

■Method of generating using a unified internal clock used to control the entire device.

■Method of generating using a multivibrator circuit.

・→+PLL method of generation.

However, in the method (2), it is impossible to completely synchronize HSYNC1 or VSYNC of the video signal sent from the external device with the internal clock, and the circuit for synchronizing with the internal clock has an impenetrable configuration. be.

In addition, in the method (■), even if a dot clock signal is generated, the output width of the first output signal becomes long, and if the output width duty of the multivibrator is too large, the oscillation frequency becomes incomplete. be.

Furthermore, it is difficult to keep the oscillation frequency constant against fluctuations in power supply voltage.

, the circuit configuration was complex, and there were also problems in terms of reliability.

[Object of the Invention] The present invention has been made in view of the above-mentioned drawbacks of the prior art, and its purpose is to provide a simple structure and to ensure accurate synchronization with a horizontal synchronization signal or a vertical synchronization signal in a video signal. An object of the present invention is to provide a video signal receiving circuit capable of outputting a synchronized clock signal for separating display data outputted to a video signal.

[Summary of the Invention] The present invention provides a method for detecting HSYNC or V
In order to accurately synchronize with SYNC and generate a dot clock signal for display data separation, a crystal oscillation circuit using a dedicated digital IC is provided, and this crystal oscillation circuit is equipped with a control input terminal, and HSYNC1 or VSYN
By providing a control signal that becomes "0" when C is detected, an accurate dot clock signal is generated without using a digital IC and without having a small output amplitude at the start of oscillation, unlike a crystal oscillation doubler circuit that uses only a linear circuit. can do.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment according to the present invention, in which 1 indicates a video signal (video composite signal) 6
HSY that detects SYNC7 and VSYNC8 and outputs them separately
NC-VSYNC detection circuit, 2 is HSYNC-VSYN
+7) HSYNC-VSYNC signal 9 from C detection circuit 1
3 is a clock generation circuit that generates and outputs a dot clock signal (CLOCK) 10 for receiving display data in the video signal 6; 3 is a CLOCK from the clock generation circuit 2;
4 is a chromaticity signal circuit that detects the chromaticity signal included in the video signal 6 when the video signal 6 is a color video signal; 5 is the display data from the data separator circuit 3; According to the chromaticity signal from the chromaticity signal detection circuit 4, the display data of the received video signal 6 is converted into red (R), green (G), and blue (B) and output. This is a data output buffer that outputs data separately.

The processing device δ such as a CPU printer connected to this embodiment receives HsYNc7 and VSYNC8, and both are CLO
Color-based output from data output buffer 5 in synchronization with CKLO (
It is possible to receive display data (red, green, blue).

A detailed circuit diagram of this clock generation circuit 2 is shown in the second [Δ.

Reference numeral 21 in FIG. 2 is a crystal oscillator, and in this embodiment, a crystal oscillator with an oscillation period of 3.58 MHz is used in accordance with the video signal standard.

Here it is a Nant gate, and one input terminal has H5
From YNC-VSYNC detection circuit (7) H5YNC-V
A SYNC signal is input as a control signal, and when this control signal 9 is "L" (HIGHT), this circuit oscillates, and when it is "O" (LOW), the oscillation of this circuit is stopped.

The clock generation circuit 2 of this embodiment uses a crystal oscillator as a pulsed oscillator, and the inverter circuit and NAND circuit (22), which are digital ICs shown in FIG.
5N74S manufactured by Texas Instruments, which is a TL
OO1 or 5N74304 is used. By using this Schottky TTL that performs high-speed switching, it is possible to obtain an output with a very accurate uniform level from the rise of the oscillation start accompanying the input of the control signal 10, and whose oscillation frequency does not fluctuate even with power supply voltage fluctuations. was completed.

FIG. 3 shows a timing chart for generating various synchronizing signals from the video signal 6 in this embodiment.

In the video signal 6, 31 is a horizontal synchronizing signal waveform, 32
is the color synchronization signal waveform in the bank porch period, 33 is the chromaticity signal waveform, 34 is the luminance signal waveform, and 35 is the vertical synchronization signal waveform. H3YNC from 31
7, VSYNC8 is generated from the vertical signal waveform 35, and H5YNC/VSYNC9 is generated from these two signals.

In the clock generation circuit 2, this H5YNC/vSYNC9
As a control signal, a dot clock signal lO is output as shown in FIG. Therefore, in the processing device, this CLOCKI
It is only necessary to receive the display data signal from the data output buffer 5 in synchronization with O.

In the above explanation, the video signal receiving circuit was explained when a video composite signal is output as a video signal. However, when a video separator signal is output as a video signal, H5YNC7, VS shown in FIG.
Since YNC8 and display data R, G, and B are output as they are, only the clock generation circuit 2 may be used as the video signal receiving circuit.

Of course, in this case as well, accurate CLOCKIO can be obtained as described above.

[Effects of the Invention] As explained above, according to the present invention, it is possible to generate a clock signal for display data reception in accurate synchronization with a horizontal synchronization signal and a vertical synchronization signal included in a video signal. In addition, even if an error occurs in the oscillation frequency, it is reset every time a synchronization signal is detected, allowing accurate reception of display data without accumulation of errors, and highly reliable separation and detection of display data signals. A video signal receiving circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a detailed block diagram of the clock generation circuit shown in FIG. 1, and FIG. 3 is a timing chart of this embodiment. In the figure, 1-HS YNC detection circuit, 2... clock generation circuit, 21... crystal oscillator.

Claims (4)

[Claims] (1) A video signal receiving circuit that receives a video signal including a horizontal synchronization signal, a vertical synchronization signal, and a display data signal, and detects whether or not the horizontal synchronization signal and the vertical synchronization signal in the video signal arrive. and generating means for generating a synchronized clock signal for receiving the display data signal in the video signal, the generating means comprising a crystal oscillation circuit, and the crystal oscillation circuit is configured such that the detecting means A video signal receiving circuit characterized in that the circuit is controlled to oscillate when detecting non-arrival of a synchronization signal. (2) In the crystal oscillator circuit, one end of the crystal oscillator is connected to the input terminal of the first inverter circuit and the first resistor, and the other end is connected to the output terminal of the NAND circuit and the input terminal of the second inverter circuit, which are connected to each other. The first inverter circuit output is connected to one input terminal of the NAND circuit, a non-detection signal from the detection means is input to one input terminal of the NAND circuit, and the first inverter circuit output is connected to one input terminal of the NAND circuit. The other end of the crystal oscillator connection terminal is connected to a grounded capacitor at one end and a second resistor terminal whose one end is connected to the output terminal of the second inverter circuit. 2. The video signal receiving circuit according to claim 1, wherein the circuit output is a synchronous clock. (3) The video signal receiving circuit according to claim 1 or 2, wherein the video signal is a video composite signal in which a horizontal synchronization signal, a vertical synchronization signal, and a display data signal are mixed. (4) The video according to claim 1 or 2, wherein the video signal is a video separator signal in which a horizontal synchronization signal, a vertical synchronization signal, and a display data signal are output independently. signal receiving circuit.