Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
  • H03K3/356—Bistable circuits
  • H03K3/356104—Bistable circuits using complementary field-effect transistors
  • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
  • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
  • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Definitions

• the present invention relates generally to electrical circuits and more particularly to a self-calibrating self-regenerative comparator circuit and method.
• Analog circuits rely very often on the matching of transistors. Unfortunately, with the advent of smaller feature size technology, the spread on several transistor parameters becomes more pronounced. As an example, transistors fabricated in Silicon on Insulator (SOI) show unwanted "kink” effects, which can be seen as a change in transistor's parameters with time, mostly depending on the transistor's operational history. In this case, even if the circuit is tuned at fabrication, the transistor operation
• U.S. Patent No. 5,568,438 discloses offset auto zeroing for reducing the access time of a RAM cell.
• the auto zeroing stage is not self-regenerative.
• the circuit disclosed in U.S. Patent No. 5,237,533 has similar merits and is not self-regenerative either.
• U.S. Patent No. 5,300,839 discloses a circuit that overcomes the threshold voltage mismatch of a differential pair of transistors at the input of a sense-amplifier.
• the present invention discloses a comparator building block that includes a positive feedback and a negative feedback mechanism.
• the negative feedback mechanism is stronger by construction, and can be enabled and disabled by switches. For example, when the switches are in the conductive state, the comparator is forced in a self- calibration mode where finally no current flows through the switches, even if there are substantial mismatches in the transistors constituting the comparator.
• This mismatch tolerant comparator building block can perform current comparisons. For example, when combined with two capacitors and one or more switches, the comparator can perform rail-to-rail voltage comparisons with offset errors more than ten times lower than the threshold voltage mismatch of the pairs of transistors defining the comparator.
• a sense-amplifier for memory cell read out can be constructed with mismatch insensitivity by including two cascode transistors between the memory bit-lines and the comparator building block.
• a self-calibration comparator stage and a self-regenerative digitizing stage are merged into one stage operating with two phases.
• a self-regenerative amplification process amplifies the initial signal difference up to a desired level, e.g. the digital rail-to-rail level. Mismatches in transistor's parameters are allowed since their effects are cancelled by the self-calibration principle. Voltages and currents can be compared with improved precision.
• the present invention can be implemented with six transistors.
• the first transistor has a current path coupled between a first supply voltage (e.g., ground) and a first switching node.
• the second transistor has a current path coupled between the first supply voltage node and a second switching node.
• the third transistor is coupled between a second supply voltage node and the first switching node and the fourth transistor between the second supply voltage node and the second switching node. These two transistors are cross-coupled.
• the fifth transistor has a current path coupled between the first switching node and the control terminal of the first transistor and the sixth transistor has a current path being coupled between the second switching node and control terminal of the second transistor.
• the present invention is advantageous compared to prior art circuits that use an OTA stage. Since the slower OTA stage is avoided, faster self-regeneration can be achieved. In addition, the basic comparator building block requires only six small area transistors, keeping the occupied transistor area small.
• Figure 1 is a preferred embodiment building block of the comparator having six transistors
• Figure 2 is a voltage comparator using the building block of Figure 1 and including de-coupling capacitors and three switches;
• Figure 3 is a timing diagram showing the voltages versus time as a result of a spice simulation
• Figure 4 shows an alternative voltage comparator that includes one switch
• Figure 5 depicts a current comparator with two cascode transistors
• Figure 6 is an extension of the six-transistor system with two more transistors acting as internal cascodes making the basic building block contain eight transistors;
• Figure 7 is a post amplifier that can be used with any of the comparators of the
• Figure 8 is a block diagram of a memory device that includes sense amplifiers that
• FIG. 1 the basic building block of the preferred embodiment of the present invention is illustrated.
• the circuit is coupled between a negative supply node 1 (labeled SN) and a positive supply node 2 (labeled SP).
• negative supply node 1 (SN) can be connected to ground (Gnd) and positive supply node 2 (SP) can be connected to the V cc supply (e.g., 5V, 3.3V or 2.5V relative to Gnd).
• V cc supply e.g., 5V, 3.3V or 2.5V relative to Gnd.
• nodes 1 (SN) and 2 (SP) can also be connected to a current source (not shown), which will then tune the current consumption of the circuit.
• the current level will also affect the g m of transistors Ml - M4, and hence influence the comparator speed and thermal noise equivalent input level.
• a direct connection of nodes 1 (SN) and 2 (SP) to the power supply lines will suffice, and by tuning the W/L (width to length) ratios of transistors M 1 -M4 with enough consideration, sufficient precision on the current consumption can be obtained.
• transistors Ml and M2 are n-channel MOS (metal oxide semiconductor) transistors that have their sources coupled to the negative supply node 1 (SN).
• the drain nodes of these transistors Ml and M2 are coupled to the switching nodes 3 and 4 of the comparator. In this example, these nodes 3 and 4 serve as the output terminals Outl and Out2, respectively.
• the transistors Ml and M2 each have a current path, e.g., through the channel, between the negative supply node 1 (SN) and the respective switching node 3 or 4.
• Transistor M5 and M6 are n-channel MOS transistors that act as switches to allow the gates of transistors Ml and M2 to be coupled to their own drain nodes 3 and 4.
• the impedance delivered by transistors Ml and M2 is (goi + g m ⁇ ) when M5 and M6 are conducting (and Ml and M2 are then configured as "diodes"), and g 0 ] when switches M5 and M6 are non-conducting (and Ml and M2 configured as current sources).
• the parameters goi and g m ⁇ are the output conductance and the transconductance parameters of transistor Ml .
• the parameter g 0x is the go of transistor MX.
• Transistors M3 and M4 are p-channel MOS transistors that have their sources coupled to the positive power supply 2 (SP), and their drains coupled to the switch nodes 3 and 4, respectively.
• the gates of these transistors M3 and M4 are cross-coupled. That is, the gate of transistor M3 is coupled to the drain of transistor M4 (at node 4), and the gate of transistor M4 is coupled to the drain of transistor M3 (at node 3).
• This configuration adds to the impedance of the switching nodes with g 03 - g m3 .
• transistors Ml to M4 typically operate in saturation.
• each transistor has an impedance go that is much smaller than its impedance g m Therefore, for the sake of simplicity, the go's will be neglected in the following analysis.
• the period of time when M5 and M6 are conducting is a resetting phase, and as will be explained later on, can also be a self-calibration phase.
• the end voltage at both switching nodes 3 and 4 is somewhere between the two supply voltages SP and SN. In the situation where the set up is fully symmetric (i.e., Ml matches M2 in all aspects and M3 matches M4 in all aspects), the end voltage of switching node 3 is exactly equal to the end voltage of switching node 4 (except for the thermal noise difference). When the circuit is not fully symmetric, however, the voltage at node 3 may differ from that at node 4.
• V ' 4 - ' V3 - i V V 4 - V ' 3 / I01
• the transconductance g m ⁇ is preferably larger than the transconductance g m3 .
• transistors Ml and M2 have more than twice as much g m as transistors M3 and M4 (e.g., g m ⁇ > 2g m3 ).
• the resetting time is reduced.
• the capacitance C sw is kept as low as possible, resetting time and amplification speed are enhanced.
• the stable end situation in an asymmetric situation such as this differs from the end situation of the symmetric situation in the fact that the reached equilibrium state has two different voltages on switching nodes 3 and 4, and that two different currents flow through the drains of transistors Ml and M2.
• transistors Ml and M2 remain at a fixed level and no current flows through transistors M5 and M6. Since no current is flowing, these transistors M5 and M6 can as well be brought into the non-conductive state, without change. The equilibrium is maintained. However, a stable situation has been transformed into a meta-stable situation.
• the circuit evolves during resetting to the "real" equilibrium state, even though it is created from an asymmetric construction.
• real equilibrium is defined to mean that the switching direction from that point depends essentially on the externally applied input signal(s) and on the thermal noise and not on the matching of the transistor pairs.
• the first phase can be referred to as a "self-calibration phase” rather than a “reset phase”. This asymmetry is in contrast from most other existing
• the system of Figure 1 can serve as a current (or voltage) comparator. By applying a current difference into the input terminals Inl and In2 just after the clock transition from high to low. a switching direction can be induced. The current difference will change the bias on the gates of transistors Ml and M2 differently, thereby inducing
• the output terminals Outl and Out2 (e.g., nodes 3 and 4) will reach quite different voltages (at least a much larger difference than the difference at equilibrium originating from the mismatches).
• a post amplifier (not shown in Figure 1 , see Figure 7) can force the output to clear digital levels. Symmetrical impedance loading, e.g., same capacitive and resistive load, of the switching nodes 3 and 4 is thereby advised for good operation.
• the post amplifier can be either synchronous or asynchronous. In most cases, however, it is suitable to form the post amplifier from two schmitt triggers and an RS flip-flop as shown in Figure 7. For low loading of the switching nodes 3 and 4, voltage followers can be used, speeding up the operation if required.
• the circuit of Figure 2 shows a method to compare two voltages VI and V2 using the principles of the present invention. Three switches 10, 11 and 12 are included in this circuit. Two capacitors Cl and C2 serve to de-couple the DC voltage from the comparator (transistors M1-M6) and to de-couple the equilibrium mismatch of the
• switch 1 1 has a current path (when conductive) between input node VI and a first plate of capacitor Cl .
• switch 12 has a current path (when conductive) between input node V2 and a first plate of capacitor C2.
• the switch 10 has a current path (when conductive) between the first plate of capacitor Cl and the first plate of capacitor C2.
• switches 10, 11 and 12 are n- channel (or p-channel) MOS transistors, although many other switches could alternatively be used.
• Signal ClockN coupled to the control input of switch 10 is the inverse of the signal Clock, coupled to the control inputs of switches 1 1 and 12.
• the circuit could be built with switches 11 and 12 as NMOS transistors, switch 10 as a PMOS transistor, and all of the gates commonly tied to Clock.
• This configuration is not preferred, however, since it limits the input range of the comparator.
• Other configurations are also possible. Since, simplifying a switch into a transistor (and when it can be done) is generally known in the state of the art, no further detailed will be provided herein.
• nodes 13 and 14 carry the input voltages VI and V2 since switches 11 and 12 are conducting.
• nodes 3 and 4 are allowed to converge to an equilibrium state, possibly with different voltages due to mismatches.
• nodes 13 and 14 are forced to the same voltage by switch 10, implying that the previous voltage difference is superimposed on the present existing voltages on the gates of Ml and M2.
• current will flow through transistor 10, the direction of current flow being determined by which voltage V 1 or V2 is greater.
• the switching is started in a direction induced by the sign of the voltage difference between VI and V2.
• input terminals VI and V2 are disconnected since switches 1 1 and 12 are non-conductive during that period.
• the capacitance of capacitors Cl and C2 can be chosen to have a value on the same order of magnitude as the gate capacitance of transistors Ml and M2, typically between a few fF (femtofarads) and several pf (picofarads).
• the capacitance of capacitor Cl is substantially equal to that of capacitor C2.
• capacitors Cl and C2 can be implemented with MOS transistors that are configured as capacitors.
• Figure 3 illustrates some curves showing the node voltages as a function of time.
• Curve 20 shows the clock signal.
• Curves 21 and 22 are the voltages on input nodes VI and V2, respectively.
• Curves 23 and 24 are the voltages on nodes 13 and 14, respectively.
• Curves 25 and 26 are the gate voltages on nodes 15 and 16, respectively.
• Curves 27 and 28 are the voltages on output nodes 3 and 4 respectively, when the circuit is simulated without mismatches.
• Curves 29 and 30 are the voltages on the same output
• FIG. 4 shows an alternative embodiment whereby switches 1 1 and 12 have been eliminated.
• Switch 10 remains.
• the switches 11 and 12 have been replaced by two (preferably substantially equal) resistors Rl and R2.
• the voltage difference between VI and V2 will now be enforced on nodes 13 and 14 with a time constant on the order of about R1.C1.
• the maximum value of Rl can be calculated.
• the resistors Rl and R2 can be formed from a CMOS transistor (either n-channel or p-channel) operating in its linear regime.
• the transistor could have its gate tied to Vcc or Gnd (or somewhere in between). This can limit the input common mode swing to a certain extent, as is known to a person ordinary skilled in the art.
• the sources generating VI and V2 contain their own output
• resistors Rl and R2 can be implemented by a diffusion region or a layer of
• Figure 5 teaches one way to extend the current comparing capability. There are several applications whereby currents (II, 12) acting on relatively large capacitors (C3, C4) are to be compared. In these cases, the scheme of Figure 5 could be used. This scheme is useful, for example, in memory sense-amplifiers, where the bit-lines represent relatively large capacitance values. Also in optical receiver systems, the capacitors C3 and C4 can represent the input photo-diode(s) and can be large as compared to the sum of the capacitance on the switching nodes 3 and 4.
• two cascode transistors M9 and M10 de-couple the high capacitive nodes 43 and 44 (with their respective capacitances C3 and C4).
• Four current- biases lb form the biasing environment of the cascode transistors M9 and M10. What remains is the current difference which is passed through M9 and M10 (biased by Vbias) to the low capacitive nodes 41 and 42.
• the error voltage difference due to transistor mismatches in transistors Ml to M6 will be build up on the nodes 41 (coupled to node 3 through transistor M5 during that period) and 42 (coupled to node 4 through transistor M6).
• This transient is relatively fast because these nodes are low capacitive nodes by construction.
• the g m of M9 and Ml 0 are chosen such that enough bandwidth is available to pass sufficiently fast the incoming current 12 and II to these nodes 42 and 41. After the falling edge of the clock, the current difference will induce a steep change of voltage on the gates of transistors Ml and M2, inducing the switching direction.
• the current biases lb can be made with transistors as is known in the art of electronics. These biases are preferentially made with degeneration, a technique known by the person skilled in the art, in order to lower the mismatch effects due to these sources. This degeneration technique is also known to lower the injected noise of a
• Cascode transistors M9 and M10 can have some mismatch and this will not affect the passage of current into the nodes 41 and 42.
• the current bias lb required to bias M9 and M10 is low as compared to the currents flowing through M3 and M4 during self calibration, then it is possible to leave out the two lower positioned current sources lb in Figure 5.
• the bias current can then be drained by the system formed by transistors Ml to M6. However, the designer should then verify good operation.
• Sense-amplifier designers working on memory read out systems should appreciate this set-up since the bit-lines (located at nodes 43 and 44) are clamped by the low impedance input of the cascodes, giving only little voltage changes during sensing, which induces less interference between bit-lines of neighboring columns.
• the larger voltage output changes obtained on nodes 41 and 42 form the input to a self-calibrated, fast self- regenerative amplification system.
• the designer skilled in the art can add some extra transistors to restore the measured digital value in the RAM cell (after being read out).
• the lower current biases lb in Figure 5 can be omitted (simplifying the circuit) when the current biasing the cascode transistors M9 and M10 is small compared to the currents flowing through transistors Ml and M2 at equilibrium.
• the upper current sources lb are preferred for every sense-amplifier, and should operate during the reading
• Figure 8 illustrates an example of a DRAM circuit that uses a sense amplifier of the present invention.
• a row decoder 63, an array of memory cells 60, and a row of sense amplifiers (including 61 and 62) of the present invention are utilized for row readout.
• the voltage comparator set-up from Figure 4 or the cascode version from Figure 6 can serve to retrieve the digital-state from the memory cell.
• the sense amplifier could alternatively be used with other types of memory cells such as SRAMs or non-volatile memories (e.g., EPROMs, EEPROMs, flash, ROMs, or others).
• the cycle utilizes at least a self-calibration phase and an evaluation phase. At the transient between these two phases, the row of interest is selected. The voltage difference induced by the small charge coming from the selected memory cell determines the direction of switching of the sense-amplifier.
• bitlines be precharged during the self-calibration phase, for example to halfway between the power supply levels SP and SN.
• Precharging when using the set-up from Figure 6 is recommended up to a voltage a few times 10 mV (up to a maximally a few hundred mV) higher than the voltage which would be present at the bitlines (Bit and BitN) reached in steady state during self calibration situation. This precharging should take place before or at the start of the calibration phase.
• FIG. 6 is an extension of the present invention whereby two transistors M7 and M8 are added to the self-calibration and self-regenerative stages to enhance speed.
• Transistors M7 and M8 act as cascode transistors.
• two extra switching nodes 51 and 52 are now included.
• nodes 3 and 4 have a relatively low voltage change, whereas nodes 51 and 52 show a larger voltage difference.
• the designer can decide whether to use this type of set-up in a particular application. A somewhat higher speed can be obtained, during self-calibration and or self-regeneration but an extra biasing voltage Vbias and extra transistors M7 and M8 are also required.

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• 1999
  • 1999-02-22 AU AU27803/99A patent/AU2780399A/en not_active Abandoned
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  • 1999-02-22 EP EP99908349A patent/EP1155412A1/de not_active Withdrawn
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