EP1148633B1 - High frequency circuit using high output amplifier cell block and low output amplifier cell block - Google Patents

High frequency circuit using high output amplifier cell block and low output amplifier cell block Download PDF

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Publication number
EP1148633B1
EP1148633B1 EP01303251A EP01303251A EP1148633B1 EP 1148633 B1 EP1148633 B1 EP 1148633B1 EP 01303251 A EP01303251 A EP 01303251A EP 01303251 A EP01303251 A EP 01303251A EP 1148633 B1 EP1148633 B1 EP 1148633B1
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Prior art keywords
cell block
amplifier cell
output amplifier
amplifier
output
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EP01303251A
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German (de)
French (fr)
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EP1148633A1 (en
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Keiichi c/o Intellectual Property Div. Yamaguchi
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Toshiba Corp
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Toshiba Corp
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    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0283—Reducing the number of DC-current paths
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    • H01P5/10—Coupling devices of the waveguide type for linking dissimilar lines or devices for coupling balanced lines or devices with unbalanced lines or devices
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Definitions

  • the present invention relates to a high frequency circuit for realizing a high efficiency power amplifier with a wide output power range which is suitable for use in a portable telephone or the like, for example, and a communication device using such a high frequency circuit.
  • the power amplifier has an efficiency which lowers at low output, because its power addition efficiency increases as the output power is increased and takes the maximum value in a vicinity of the saturation point of the output power.
  • Fig. 1A shows an exemplary relationship between the efficiency and the output power at low output in a general amplifier.
  • the efficiency is a value obtained by dividing an RF (high output) output power by a DC (direct current) input power, which corresponds to a collector efficiency of a bipolar transistor and a drain efficiency of a field effect transistor.
  • Fig. 1B shows an inverse of the efficiency shown in Fig. 1A in the logarithmic scale.
  • the efficiency is sequentially degraded from 72% at the output power of 30 dBm (dBmW to be accurate, but will be abbreviated as dBm hereafter) to 21.8% at the output power of 20 dBm, 4.7% at the output of 10 dBm, and 1,5% at the output power of 5 dBm. Accordingly, a ratio of the DC input power with respect to the RF output power sequentially increases to 1.4 at the 30 dBm output, 4.6 at the 20 dBm output, 21.2 at the 10 dBm output, and 67.1 at the 5 dBm output.
  • FIGs. 2A and 2B show graphs indicating a relationship between current and voltage in the alternating currents.
  • a load line is as indicated by a chain line KB
  • the output voltage is in a form of a sinusoidal wave with an average value set at a bias voltage
  • the output current is in a form of a half-wave rectified wave Iout(t). Note that a point B in Figs. 2A and 2B corresponds to the bias point.
  • Figs. 2A and 2B show the case of the class B operation.
  • the RF output power is given by a product of an effective value of the fundamental wave component Vout of the output power and an effective value of the fundamental wave component I 1 (t).
  • Vout of the output power an effective value of the fundamental wave component
  • I 1 (t) an effective value of the fundamental wave component
  • the DC input power is given by a product of the bias and an average value of the output current Iout(t), which corresponds to an area of a rectangle with a point D and a point B as diagonal corners (which will be referred to as a rectangle DB hereafter) in Figs. 2A and 2B.
  • the efficiency is given by a ratio of these two areas.
  • the current amplitude and the voltage amplitude are both reduced to 1/2 so that the output power is 1/4.
  • the direct current is given by an average value of the RF current so that it is also reduced to 1/2 but the direct current voltage is fixed at a point B, so that the area of the rectangle DB is 1/2.
  • the efficiency is reduced to 1/2 whenever the RF output power is reduced to 1/4 (-6 dB).
  • a rate of the degradation of the efficiency is greater than 1/2 due to the influence of the knee voltage or the fact that the operation is actually the class AB operation.
  • a plurality of amplifiers with different maximum output powers AMP1 (with maximum output of -20 dBm) AMP2 (with maximum output of 5 dBm), and AMP3 (with maximum output of 30 dBm) are arranged in series, while bias circuits 75 and 76 are provided with respect to the AMP2 and AMP3 of the later stages, and a connection form is selected by switching switch circuits S71. S72, S73 and S74, so as to realize an appropriate power amplification.
  • the gain of each stage is usually about 25 dB, so that it is difficult to improve the degradation of the efficiency considerably by the method described above.
  • the minimum unit for the amplification stages that is practically feasible is expected to be 10 dB to 15 dB corresponding to the gain per one stage of a transistor.
  • Fig. 4A shows a circuit for realizing this conventional optimization method schematically.
  • a circuit shown in Fig. 4A realizes a method for switching an effective transistor size of the amplifier, where a plurality of amplifiers 14a and 14b are connected in parallel, while input switches Si1 and Si2 and output switches So1 and So2 are provided at the input side and the output side of these transistors 14a and 14b respectively, and input signals entered from a variable matching circuit 13i are entered into a transistor with appropriate gate length or emitter area by switching the switches Si1, Si2, So1 and So2 and amplified signals are outputted to a variable matching circuit 13o.
  • the matching to a matching condition suitable for a respective transistor size is made by the variable matching circuits 13i and 13o.
  • the maximum output power is reduced to 1/2 by reducing the transistor size to 1/2, so that the efficiency can be maximized for the power in a narrow range of about 3 dB.
  • Such a variable matching circuit can be realized by any of a circuit shown in Fig. 5A in which a variable inductance 11 and a variable capacitor 12 are combined, a circuit shown in Fig. 5B in which distributed constant circuits 14 to 16 are connected through switches S1 and S2, and a circuit shown in Fig. 5C in which matching circuits 13a and 13b of different types are switched by switches Si11, Si12, So11 and So12.
  • a circuit shown in Fig. 5C in which matching circuits 13a and 13b of different types are switched by switches Si11, Si12, So11 and So12.
  • FIG. 6A Another way of compensating the degradation of the efficiency at low output is to use an amplifier circuit as shown in Fig. 6A.
  • This amplifier circuit realizes a method for optimizing the power source voltage to be supplied to the amplifier according to the output power, where a voltage Vdc to be applied to a transistor 17 is adjusted by variable voltage sources 9 and 10 so as to move the bias point from B2 to B1 and change the load line from K2B2 to K1B1 as shown in Fig. 6B, such that the power and the voltage amplitude on the load line are maximized.
  • the matching of input/output can be made by constant matching circuits 18i and 18o rather than variable matching circuits.
  • a variable voltage source with sufficiently high efficiency capable of supplying a large amount of currents to be consumed by the power amplifier can be realized by a step-down DC-DC converter as shown in Fig. 6C in which a resistance L and a capacitor C are appropriately connected by switches Q1 and Q2 controlled by a control circuit.
  • the lowest output voltage is only about 1 V due to the reference voltage of the internal regulator, and the efficiency of the variable voltage source is degraded at the low voltage output, so that it is difficult to maintain the high efficiency over a wide output power range and there is also a problem that the implementation area is large.
  • the transmission power control is carried out in the communication system using the CDMA scheme, such that the transmission power varies within a range (dynamic range) of about 75 dB. Consequently, the power addition efficiency of the power amplifier is required to be high at the powers other than the maximum output power.
  • the probability density function for the transmission powers is roughly in a form of the normal distribution, and the average transmission power of the mobile terminal is in a range of 10 dBm to 16 dBm, although it varies due to system related factors such as the arrangement of the base stations.
  • a high frequency circuit comprising: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted.
  • a communication device comprising: at least one antenna configured to transmit or receive radio signals; at least one power amplifier configured to amplify the radio signals to be transmitted or received by the at least one antenna, including a high frequency circuit formed by: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted; and
  • a phrase "amplifier cells connected in parallel AC-wise" will be used to imply that target amplifier cells of nearly identical size are connected at nearly identical phase with nearly identical amplitude. Strictly speaking from a viewpoint of distributed constant circuits, a connection at exactly identical phase with exactly identical amplitude is difficult to realize in practice, so that a phase "amplifier cells connected in parallel AC-wise" can be construed as meaning that the efficiencies of the power distribution at the input side and the power composition at the output side of a plurality of cell blocks, such as cell blocks 4a and 4b, 4c and 4d shown in Figs. 9A and 9B to be described below or transistors Q1 and Q2 shown in Figs.
  • a phrase “DC power source voltage is supplied in parallel” will be used to imply that nearly identical level of voltage is applied to target cells. Strictly speaking, it is practically difficult to apply exactly identical level of voltage because of a voltage dropping due to circuit losses, so that a phrase “DC power source voltage is supplied in parallel” can be construed as meaning that the voltage is applied within a tolerable range of ⁇ 20% with respect to a plurality of cell blocks, such as cell blocks 4a to 4c shown in Figs. 9A and 9B to be described below, or cells that constitute these cell blocks.
  • a phrase "DC power source voltage is supplied in series” will be used to imply that, when the "amplifier cells connected in parallel AC-wise" are transistor cells Q1 and Q2 as shown in Fig. 11B to be described below, the voltage given at a collector of the transistor cell Q1 is applied to these plurality of transistor cells in division, in such a way that the DC flows from a collector of the transistor cell Q1 through an emitter to a collector of the transistor cell Q2 and is then grounded, for example.
  • transistor cell will be used to indicate a set of transistors having nearly identical characteristics. Strictly speaking from a viewpoint of the device process, it is practically difficult to fabricate transistors with exactly identical characteristics. Even if geometrically similar transistors are used, they may not operate as identical transistors depending on their layout positions on a semiconductor chip or differences in their surrounding electromagnetic and thermal environments due to a substrate on which the semiconductor chip is implemented, etc. Also, even within a semiconductor wafer, geometrically similar transistors may not necessary have identical characteristics, due to the non-uniformity of characteristics which is a well known problem associated with transistors in general.
  • a set of transistors are formed by bundling a plurality of tiny unit transistors (in units of gate in the case of FETs, in units of emitter or base in the case of bipolar transistors, for example) that are physically independent in the power amplifier. If a sufficient power cannot be obtained in this state, an even larger transistor is formed by bundling these transistors.
  • a transistor used in the power amplifier is a set of a plurality of tiny transistors in general.
  • Fig. 7 shows an exemplary configuration of a power amplifier formed by using a high frequency circuit of this embodiment.
  • the power amplifier comprises an input matching circuit 3i, a first connection unit 2i for splitting signals entered from the input matching circuit 3i, a high output amplifier cell block 1a, a low output amplifier cell block 1b, a second connection unit 2o to which signals from the high output amplifier cell block 1a and the low output amplifier cell block 1b are entered, and an output matching circuit 3o.
  • the high output amplifier cell block 1a has amplifier cells which are connected in parallel AC-wise with respect to input and output signals, and DC power source voltage is supplied in parallel to these amplifier cells.
  • the low output amplifier cell block 1b has amplifier cells that are connected in parallel AC-wise with respect to input and output signals, and DC power source voltage is supplied in series to these amplifier cells.
  • the high output amplifier cell block 1a has a signal input terminal INa, a signal output terminal OUTa, a power source voltage terminal Vdca, and a control voltage terminal Vcnta
  • the low output amplifier cell block 1b has a signal input terminal INb, a signal output terminal OUTb, a power source voltage terminal Vdcb, and a control voltage terminal Vcntb.
  • each one of the first and second connection units 2i and 2o is formed by using only passive elements such as coils and capacitors, so as to provide a splitting circuit formed by transmission paths, for example, as indicated in the second connection unit 2o shown in Fig. 8.
  • the use of active elements for switching signal paths such as switches used in the conventional circuits of Figs. 4A, 5A, 5B and 5C in addition to active elements for amplifying RF signals can cause the complication of a circuit configuration, the increase of the required number of parts, the increase of the implementation area, and the degradation of signals due to distortion or loss, which can lead to the higher cost and the lower performance.
  • the use of such active elements is avoided in this embodiment and the first and second connection units 2i and 2o are formed by using only passive elements in order to achieve the equivalent or better effects by a simpler configuration.
  • Fig. 9A and Fig. 9B show exemplary internal configurations of the high output amplifier cell block 1a and the low output amplifier cell block 1b respectively. Note that amplifier cells 4a, 4b, 4c and 4d used in this embodiment are formed by transistors of the same size.
  • the high output amplifier cell block 1a of this embodiment has two amplifier cells 4a and 4b, and these amplifier cells 4a and 4b are connected in parallel with respect to the input and output signals, and also connected in parallel with respect to the DC power source voltage Vdca.
  • the control voltage Vcnta is also given in parallel to the amplifier cells 4a and 4b.
  • the low output amplifier cell block 1b of this embodiment has two amplifier cells 4c and 4d, and these amplifier cells 4c and 4d are connected in parallel with respect to the input and output signals, and also connected in series with respect to the DC power source voltage Vdcb.
  • the control voltage Vcntb is also given in parallel to the amplifier cells 4c and 4d.
  • the amplifier cells 4c and 4d in the low output amplifier cell block 1b are connected by an AC/DC separation unit 5 such as bias T, for example, and this AC/DC separation unit 5 realizes a grounding of AC of the amplifier cell 4c, while DC is applied to the DC power source terminal of the amplifier cell 4d.
  • the DC power source voltage applied to the amplifier cells 4c and 4d is divided into two equal parts, i.e., 1/2 each.
  • the number of the amplifier cells 4a and 4b in the high output amplifier cell block 1a is set equal to the number of the amplifier cells 4c and 4d in the low output amplifier cell block 1b, so that the input and output impedances are equal ideally speaking. Consequently, the slopes of the load lines can be made identical by using the common input and output matching circuits 3i and 3o.
  • the power source voltage is 1/2 and the load line is identical so that the maximum current also becomes 1/2 and the maximum output power can be reduced to 1/4 (-6 dB).
  • This embodiment is equivalent to a state in which the bias voltage B1 becomes 1/2 of the bias voltage B2 in Fig. 6B.
  • the maximum output power of the high output amplifier cell block 1a is set to 30 dBm
  • the maximum output power of the low output amplifier cell block 1b can be about 24 dBm because the power source voltage is 1/2.
  • the high output amplifier cell block 1a is put in an operation state while the low output amplifier cell block 1b is put in a non-operation state.
  • the efficiency will be lowered as the output power becomes lower than the maximum output power 30 dBm.
  • the output power is about 24 dBm which is the maximum output power of the low output amplifier cell block 1b
  • the efficiency is lowered to 35.4%.
  • the high output amplifier cell block 1a is put in a non-operation state while the low output amplifier block 1b is put in an operation state, such that the efficiency is recovered to 72% again, and them lowered to 35% again as the output power is lowered further.
  • the efficiency can be recovered to about 72% even at the low output, so that a relationship between the efficiency and the output power becomes a saw-tooth shaped line with about 6 dB interval between adjacent peaks as shown in Fig. 10.
  • Figs. 11A and 11B show equivalent circuits of the high output amplifier cell block 1a and the low output amplifier cell block 1b shown in Figs. 9A and 9B respectively.
  • C1, C1' and C2 are DC preventing capacitors
  • L1, L1' and L2 are RF chokes
  • R1 and R1' are stabilizing resistors
  • Q1 and Q2 are bipolar transistors. Note that the same effects can also be realized by using field effect transistors for Q1 and Q2.
  • C3 is a DC preventing capacitor for separating collectors of Q1 and Q2 DC-wise
  • C4 and L4 forms a filter which functions as the AC/DC separation unit 5 in this embodiment. Namely, C4 realizes the AC-wise grounding in the signal frequency of Q1.
  • the power amplifier according to this embodiment in a configuration as described above operates as follows.
  • signals entered from an input terminal IN are entered into the high output amplifier cell block 1a and the low output amplifier cell block 1b through the input matching circuit 3i and the first connection unit 2i.
  • the output signals of the high output amplifier cell block 1a and the low output amplifier cell block 1b are outputted from an output terminal OUT through the second connection unit 2o and the output matching circuit 3o.
  • one of the amplifier cell blocks 1a and 1b is selected according to the power to be outputted, and these amplifier cell blocks 1a and 1b are switched between an amplification operation state and a non-operation state with high impedance, by the control voltages Vcnta and Vcntb. Only one amplifier cell block is put in the amplification operation state at any given moment. For example, as shown in Fig. 8, when the high output amplifier cell block 1a is put in the amplification operation state, the low output amplifier cell block 1b is put in a high impedance non-operation state.
  • the input and output impedances of the low output amplifier cell block 1b in the high impedance non-operation state can be expressed as capacitances Ci and Co respectively.
  • the resistance component that is entered into open capacitances is ignored here as it only causes a negligible loss compared with the output impedance of the high output cell block 1a.
  • the load impedance from a viewpoint of an output node 6a of the high output amplifier cell block 1a is that of a parallel connection of the output matching circuit 3o and a stab with the open capacitance Co beyond a splitting point node 6c.
  • the operating amplifier cell block can be selected without using any switch.
  • the first embodiment described above is directed to the case of using two amplifier cell blocks as shown in Fig. 7, but the present invention is not limited to this specific case.
  • the number of steps connected in series with respect to DC in the low output amplifier cell block is two in the first embodiment, but this number can be increased to four, eight, and so on.
  • four steps for example, the three types of amplifier cell blocks using one step, two steps, and four steps may be used, or two types of amplifier cell blocks using one step and four steps may be used.
  • eight steps four types of amplifier cell blocks using one step, two steps, four steps and eight steps may be used, or any three types out of these four types may be used, or any two types out of these four types may be used. It should be apparent that the circuit configuration becomes more complicated when the number of steps is increased. The number of steps to be used should be selected by taking the effect at a time of the power control into consideration.
  • the number of steps need not takes a form of 2 n , but it is assumed to be in a form of 2 n here.
  • N 2 n
  • up to n+1 types of the amplifier cell blocks using the respective number of steps equal to 1, 2, 4, ⁇ , 2 n can be used.
  • the choice of the types of the amplifier cell blocks to be used in combination is arbitrary as described above, but it should be noted that the use of the same number of steps in different amplifier cell blocks would result in a poor circuit efficiency.
  • the dynamic range greater than or equal to 12 dB can be realized.
  • the power amplifier comprises an input matching circuit 3i, a first connection unit 2i for splitting signals entered from the input matching circuit 3i, a high output amplifier cell block 1c, a middle output amplifier cell block 1d, a low output amplifier cell block 1e, a second connection unit 2o to which signals from the high output amplifier cell block 1c, the middle output amplifier cell block 1d and the low output amplifier cell block 1e are entered, and an output matching circuit 3o.
  • the high output amplifier cell block 1c of this embodiment has four amplifier cells 4e to 4h, and these amplifier cells 4e to 4h are connected in parallel with respect to the input and output signals, and also connected in parallel with respect to the DC power source voltage Vdcc.
  • the control voltage Vcntc is also given in parallel to the amplifier cells 4e to 4h.
  • the middle output amplifier cell block 1d of this embodiment has two amplifier cells 4i and 4l, and these amplifier cells 4i to 4l are connected in parallel with respect to the input and output signals. Also, a pair of the amplifier cells 4i and 4j and a pair of the amplifier cells 4k and 4l are connected in series with respect to the DC power source voltage Vdcd while the first stage amplifier cells 4i and 4k of these pairs are connected in parallel. In addition, the control voltage Vcntd is also given in parallel to the amplifier cells 4i and 4l.
  • Each pair of the amplifier cells 4i and 4j, or 4k and 4l, in the middle output amplifier cell block 1d are connected by an AC/DC separation unit 5 such as bias T, for example, and this AC/DC separation unit 5 realizes a grounding of AC of the amplifier cells 4i and 4k, while DC is applied to the DC power source terminals of the second stage amplifier cells 4j and 4l.
  • the DC power source voltage applied to the amplifier cells 4i to 4l is divided into two equal parts, i.e., 1/2 each.
  • the low output amplifier cell block 1e of this embodiment has four amplifier cells 4m to 4p, and these amplifier cells 4m to 4p are connected in parallel with respect to the input and output signals, and also connected in series with respect to the DC power source voltage Vdce.
  • the control voltage Vcnte is also given in parallel to the amplifier cells 4m to 4p.
  • the amplifier cells 4m to 4p in the low output amplifier cell block 1e are connected by an AC/DC separation unit 5 such as bias T, for example, and this AC/DC separation unit 5 realizes a grounding of AC of the amplifier cell 4m to 4o, while DC is applied to the DC power source terminal of the amplifier cell 4n to 4p.
  • the DC power source voltage applied to the amplifier cells 4m to 4p is divided into four equal parts, i.e., 1/4 each.
  • the dynamic range can be widened easily by increasing the number of steps to be connected in series with respect to DC in the amplifier cell block further.
  • the dynamic range greater than or equal to 18 dB can be realized by using four amplifier cell blocks where each amplifier cell block is formed by eight divided amplifier cells and a division of the DC power source voltage in eight steps (1/8) at most.
  • the DC power source voltage Vdc is entered through L2 and the flow of DC to the output terminal is prevented by the DC preventing capacitor C2.
  • the DC power source voltage Vdc is given from a node 6c side by using a circuit through which DC can flow as the second connection unit 2o.
  • the high output amplifier cell block 1a' of this embodiment has a structure in which the signals entered from the first connection unit 2i are entered into the bipolar transistors Q1H and Q2H in parallel through the DC preventing capacitor C1H while the control voltage Vcnt1 is entered into the bipolar transistors Q1H and Q2H in parallel through the stabilizing resistor R1H and the RF choke L1H.
  • Vdc is entered into the bipolar transistors Q1H and Q2H in parallel from the second connection unit 2o side through L2.
  • the low output amplifier cell block 1b' of this embodiment has a structure in which the signals entered from the first connection unit 2i are entered into the bipolar transistors Q1L and Q2L in parallel through the DC preventing capacitor C1L while the control voltage Vcnt2 is entered into the bipolar transistors Q1L and Q2L in parallel through the stabilizing resistor R1L and the RF choke L1L.
  • Vdc is entered into the bipolar transistors Q1L and Q2L in series DC-wise from the second connection unit 2o side through L2. Namely, using the DC preventing capacitor C3 and the RF choke L4, only DC is allowed to flow from the bipolar transistor Q1L to the bipolar transistor Q2L. Also, the grounding of AC is realized by the decoupling capacitor C4.
  • C2 and L2 are removed from the high output amplifier cell block 1a shown in Fig. 11A and the low output amplifier cell block 1b shown in Fig. 11B, and the DC power source voltage is applied at a common power source voltage terminal Vdc through L2 from the node 6c of the second connection unit 2o.
  • C2 shown in Fig. 14 is a DC cut for the output matching circuit 3o.
  • the DC power source voltage Vdc is supplied from the node 6c side so that L2 and C2 shown in Figs. 11A and 11B in the first embodiment described above become unnecessary, and it is possible to reduce the circuit area.
  • Fig. 15 shows an exemplary configuration in this case.
  • the high output amplifier cell block 1a" of this embodiment has a structure in which the signals entered from the first connection unit 2i are entered into the bipolar transistors Q1H and Q2H in parallel through the DC preventing capacitor C5H while the control voltage Vcnt is entered into a bias circuit BCH also from the first connection unit 2i side.
  • This bias circuit BCH generates the control signal Vcnt1 according to the control voltage Vcnt, and Vcnt1 generated by this bias circuit BCH is entered into the bipolar transistors Q1H and Q2H in parallel.
  • Vdc is entered into the bipolar transistors Q1H and Q2H in parallel from the second connection unit 2o side by the configuration similar to that of the third embodiment.
  • the low output amplifier cell block 1b" of this embodiment has a structure in which the signals entered from the first connection unit 2i are entered into the bipolar transistors Q1L and Q2L in parallel through the DC preventing capacitor C5L while the control voltage Vcnt is entered into a bias circuit BCL also from the first connection unit 2i side.
  • This bias circuit BCL generates the control signal Vcnt2 according to the control voltage Vcnt, and Vcnt2 generated by this bias circuit BCL is entered into the bipolar transistors Q1L and Q2L in parallel.
  • Vdc is entered into the bipolar transistors Q1L and Q2L in series DC-wise from the second connection unit 2o side. Namely, using the DC preventing capacitor C3 and the RF choke L4, only DC is allowed to flow from the bipolar transistor Q1L to the bipolar transistor Q2L. Also, the grounding of AC is realized by the decoupling capacitor C4.
  • control signals Vcnt1 and Vcnt2 are generated according to the common control voltage Vcnt by the bias circuits BCH and BCL respectively.
  • the control signal Vcnt1 generated by the bias circuit BCH is supplied to the transistors Q1H and Q2H through a high frequency choke inductor L6H
  • the control signal Vcnt2 generated by the bias circuit BCL is supplied to the transistors Q1L and Q2L through a high frequency choke inductor L6L.
  • the common control voltage Vcnt is used for the amplifier cell blocks so that even when the number of the amplifier cell blocks is increased, the amount of wirings for the control signals can be reduced and it is possible to reduce the circuit size.
  • FIG. 16A, 16B, 17A, 17B, 17C, 18A and 18B show various configuration s of the power amplifier according to the fifth embodiment.
  • the amplifier cell blocks can be mounted on separate semiconductor chips as shown in Fig. 16A.
  • the high output amplifier cell block 1a and the low output amplifier cell block 1b can be formed by independent semiconductor chips and mounted on a substrate GND.
  • the amplifier cell blocks are connected with the first and second connection units 2i and 2o by bonding wires, and the control voltages Vcnt1 and Vcnt2 are also entered from an external of the substrate GND by bonding wires.
  • the high output amplifier cell block 1a and the low output amplifier cell block 1b are formed by an identical semiconductor chip and mounted on the substrate GND.
  • the amplifier cell blocks are connected with the first and second connection units 2i and 2o by bonding wires, and the control voltages Vcnt1 and Vcnt2 are also entered from an external of the substrate GND by bonding wires.
  • a ground electrode can be formed wide so that the ground inductance can be reduced.
  • the amplifier cells of different amplifier cell blocks can be arranged as upper and lower halves of the amplifier cells as shown in Fig. 17A, or the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged alternately as shown in Fig. 17B.
  • the amplifier cells in more than one rows as shown in Figs. 17C, 18A and 18B, depending on the chip shape.
  • the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged in different rows as shown in Fig. 17C, or the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged as upper and lower halves of the amplifier cells in both rows as shown in Fig. 18A, or the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged in a zigzag pattern as shown in Fig. 18B.
  • FIGS. 19A, 19B and 19C show various configuration s of the power amplifier according to the sixth embodiment.
  • the transistors of each amplifier cell block have the uniform size and the same impedance, and the input and output connection units are provided symmetrically, because the operation principle of the power amplifier of the present invention is based on the parallel shift of the load line using the bias voltage as shown in Fig. 6B.
  • the load line is not necessarily a straight line and the parallel shift of the load line with the fixed source and load impedances may not necessarily be optimal because of the influence of the knee voltage.
  • the fine tuning of the source and load impedances in each amplifier cell block which can be done as follows.
  • the input and output connection units 2i and 2o can be formed asymmetrically along a vertical direction (i.e., with respect to the high output amplifier cell block 1a and the low output amplifier cell block 1b).
  • the fine tuning of the impedances can then be realized by changing widths or lengths of a pattern of a distributed constant lines of the input and output connection units 2i and 2o, changing lengths, numbers or intervals of the bonding wires, or by mounting chip parts.
  • the fine tuning of the impedances can be realized by setting the number of amplifier cells for the high output amplifier cell block 1a greater than that for the low output amplifier cell block 1b such that the transistor size of the high output amplifier cell block 1a becomes larger than that of the low output amplifier cell block 1b.
  • the fine tuning of the impedances can be realized by devising the cell arrangement positions on the chip such that different amplifier cell blocks have different distances with respect to the matching circuits.
  • the arrangement of the high output amplifier cell block 1a can be biased toward the first connection unit 2i side, while the arrangement of the low output amplifier cell block 1b can be biased toward the second connection unit 2o side.
  • This embodiment is directed to an application of the power amplifier according to the present invention to transmit and receive amplifiers used in a communication device of a radio system.
  • the communication device has a radio unit 100 which comprises antennas 101 and 102 for transmitting and receiving radio signals, an antenna duplexer/switch 103 for switching connection of the antennas 101 and 102, a transmit amplifier 104 and a receive amplifier 105 with the power amplifier of any of the above embodiments incorporated therein, a modulator 106 for modulating signals to be inputted into the transmit amplifier 104, a demodulator 108 for demodulating signals outputted from the receive amplifier 105, and a synthesizer 107 for carrying out a synchronization processing with a baseband signal processing unit 109.
  • a radio unit 100 which comprises antennas 101 and 102 for transmitting and receiving radio signals, an antenna duplexer/switch 103 for switching connection of the antennas 101 and 102, a transmit amplifier 104 and a receive amplifier 105 with the power amplifier of any of the above embodiments incorporated therein, a modulator 106 for modulating signals to be inputted into the transmit amplifier 104, a demodulator 108 for demodul
  • the communication device of this embodiment also has the baseband signal processing unit 109 for carrying out a signal processing with respect to input/output signals of the radio unit 100, an input/output unit 110 for inputting/outputting input/output signals of the baseband signal processing unit 109 with respect to an external, a control unit 111 for controlling operations of the radio unit 100, the baseband signal processing unit 109 and the input/output unit 110, and a power source 112 for supplying power source voltages to the radio unit 100, the baseband signal processing unit 109 and the input/output unit 110.
  • the input/output unit 110 has a microphone 110a and keys 110d as input interface for receiving input speeches or operations from the external, and a speaker 110b, a display 110c and a vibrator 110e as output interface with respect to the external.
  • the input speeches or operation signals entered from the microphone 110a or keys 110d of the input/output unit 110 are applied with the signal processing at the baseband signal processing unit 109 under the control of the control unit 111, and entered into the transmit amplifier 104 through the modulator 106.
  • These signals are amplified by the amplification processing as described above at the transmit amplifier 104 and transmitted from the antenna 101 or 102 through the antenna duplexer/switch 103.
  • radio signals received by the antenna 101 or 102 are amplified by the receive amplifier 105 through the antenna duplexer/switch 103 under the control of the control unit 111, and converted into control signals at the baseband signal processing unit 109 through the demodulator 108, to control the operations of the speaker 110b, the display 110c and the vibrator 110e of the input/output unit 110.
  • the base station of the mobile communication system has at least one radio unit 200 which comprises antennas 201 and 202 for transmitting and receiving radio signals, an antenna duplexer/switch 203 for switching connection of the antennas 201 and 202, a transmit amplifier 204 and a receive amplifier 205 with the power amplifier of any of the above embodiments incorporated therein, and a modem 206 for modulating signals to be inputted into the transmit amplifier 204 and demodulating signals outputted from the receive amplifier 205.
  • radio unit 200 which comprises antennas 201 and 202 for transmitting and receiving radio signals, an antenna duplexer/switch 203 for switching connection of the antennas 201 and 202, a transmit amplifier 204 and a receive amplifier 205 with the power amplifier of any of the above embodiments incorporated therein, and a modem 206 for modulating signals to be inputted into the transmit amplifier 204 and demodulating signals outputted from the receive amplifier 205.
  • the base station of this embodiment also has a baseband signal processing unit 207 for carrying out a signal processing with respect to input/output signals of the radio unit 200, a transmission path connection unit 208 for inputting/outputting input/output signals of the baseband signal processing unit 207 with respect to an external, a control unit 209 for controlling operations of the radio unit 200, the baseband signal processing unit 207 and the transmission path connection unit 208, and a power source 210 for supplying power source voltages to the radio unit 200, the baseband signal processing unit 207 and the transmission path connection unit 208.
  • the signals entered from the external are entered into the baseband signal processing unit 207 through the transmission path connection unit 208, applied with the signal processing at the baseband signal processing unit 207, and entered into the transmit amplifier 204 through the modem 206.
  • These signals are amplified by the amplification processing as described above at the transmit amplifier 204 and transmitted from the antenna 201 or 202 through the antenna duplexer/switch 203.
  • radio signals received by the antenna 201 or 202 are amplified by the receive amplifier 205 through the antenna duplexer/switch 203, and converted into control signals at the baseband signal processing unit 207 through the modem 206 and outputted to the external through the transmission path connection unit 208.
  • the power amplifier of the present invention is suitable for a system that requires the power amplifier with a wide output power range. For example, it is effective for communications with a mobile station as described above or even for communications between fixed stations where the radio propagation environment can be easily changed. It is also effective in a mobile communication system such as a portable telephone system, especially a mobile communication system using the CDMA scheme that requires a wide dynamic range.
  • the present invention it is possible to realize a power amplifier capable of realizing a high efficiency operation over a wide output power range, without using variable voltage sources such as switches, variable matching circuits, DC-DC converters, etc.
  • the high frequency circuit of the present invention can be mounted on MMIC (Monolithic Microwave Integrated Circuit) so that it can be utilized in the power amplifier for the portable telephone or the like which has a severe power consumption requirement, and it is possible to extend the continuous operation time of the portable telephone or the like considerably.
  • MMIC Monitoring Microwave Integrated Circuit
  • the high output amplifier cell block is operated at a time of the high output and the low output amplifier cell block is operated at a time of the low output where the low output amplifier cell block has the maximum efficiency, so that it is possible to eliminate the wasteful power consumption by the high output amplifier cell block.
  • the amplifier cell blocks are connected in parallel AC-wise, and the voltage nearly equal to the input voltage is applied to the amplifier cells at nearly the same phase, so that it is possible to realize the high output amplification without causing a phase displacement among the amplifier cells.
  • the amplifier cells are connected in series AC-wise, and a divided low voltage is applied to the amplifier cells at nearly the same phase, so that it is possible to realize the low output amplification without causing a phase displacement among the amplifier cells.
  • only one of the amplifier blocks is put in the amplification operation state according to the output power while the other amplifier cell blocks are put in the high impedance non-operation state, so that the non-operating amplifier cell blocks can be regarded by the connection units as open capacitances with high impedances which do not affect the amplifier cell block in the operation state.
  • the output power with the maximum efficiency can be lowered by about 6 dB per one step.
  • the power amplifier in a compact size can be realized because the variable voltage sources such as switches, variable matching circuits, DC-DC converters, etc. are not required for the purpose of switching signal paths.

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Description

    BACKGROUND OF THE INVENTION FIELD OF THE INVENTION
  • The present invention relates to a high frequency circuit for realizing a high efficiency power amplifier with a wide output power range which is suitable for use in a portable telephone or the like, for example, and a communication device using such a high frequency circuit.
    • DESCRIPTION OF THE RELATED ART
  • In general, the power amplifier has an efficiency which lowers at low output, because its power addition efficiency increases as the output power is increased and takes the maximum value in a vicinity of the saturation point of the output power. Fig. 1A shows an exemplary relationship between the efficiency and the output power at low output in a general amplifier. Here, the efficiency is a value obtained by dividing an RF (high output) output power by a DC (direct current) input power, which corresponds to a collector efficiency of a bipolar transistor and a drain efficiency of a field effect transistor. Fig. 1B shows an inverse of the efficiency shown in Fig. 1A in the logarithmic scale.
  • As shown in Figs. 1A and 1B, the efficiency is sequentially degraded from 72% at the output power of 30 dBm (dBmW to be accurate, but will be abbreviated as dBm hereafter) to 21.8% at the output power of 20 dBm, 4.7% at the output of 10 dBm, and 1,5% at the output power of 5 dBm. Accordingly, a ratio of the DC input power with respect to the RF output power sequentially increases to 1.4 at the 30 dBm output, 4.6 at the 20 dBm output, 21.2 at the 10 dBm output, and 67.1 at the 5 dBm output.
  • The cause of this degradation of the efficiency at low output will now be explained using a simplified ideal transistor model. Figs. 2A and 2B show graphs indicating a relationship between current and voltage in the alternating currents.
  • In Figs. 2A and 2B, it is assumed that a load line is as indicated by a chain line KB, the output voltage is in a form of a sinusoidal wave with an average value set at a bias voltage, and the output current is in a form of a half-wave rectified wave Iout(t). Note that a point B in Figs. 2A and 2B corresponds to the bias point.
  • Figs. 2A and 2B show the case of the class B operation. The RF output power is given by a product of an effective value of the fundamental wave component Vout of the output power and an effective value of the fundamental wave component I1(t). One half of an area of a rectangle with a point R and a point B as diagonal corners corresponds to the RF output power.
  • The DC input power is given by a product of the bias and an average value of the output current Iout(t), which corresponds to an area of a rectangle with a point D and a point B as diagonal corners (which will be referred to as a rectangle DB hereafter) in Figs. 2A and 2B. The efficiency is given by a ratio of these two areas.
  • With respect to the case of Fig. 2A, in the case of Fig. 2B, the current amplitude and the voltage amplitude are both reduced to 1/2 so that the output power is 1/4. On the other hand, the direct current is given by an average value of the RF current so that it is also reduced to 1/2 but the direct current voltage is fixed at a point B, so that the area of the rectangle DB is 1/2. As a result, the efficiency is reduced to 1/2 whenever the RF output power is reduced to 1/4 (-6 dB). In practice, a rate of the degradation of the efficiency is greater than 1/2 due to the influence of the knee voltage or the fact that the operation is actually the class AB operation.
  • Conventionally, one way of compensating such a degradation of the efficiency at low output is to use an amplifier circuit as shown in Fig. 3A.
  • Namely, as shown in Fig. 3A, in this conventional amplifier circuit, a plurality of amplifiers with different maximum output powers, AMP1 (with maximum output of -20 dBm) AMP2 (with maximum output of 5 dBm), and AMP3 (with maximum output of 30 dBm) are arranged in series, while bias circuits 75 and 76 are provided with respect to the AMP2 and AMP3 of the later stages, and a connection form is selected by switching switch circuits S71. S72, S73 and S74, so as to realize an appropriate power amplification.
  • However, as can be seen from a gain diagram shown in Fig. 3B, in the conventional amplifier circuit described above, there are cases for outputting the power that is lower by as much as 25 dB at most with respect to the maximum output power 30 dBm of AMP3 or the maximum output power 5 dBm of AMP2 in a range (B in Fig. 3B) of the output power between 5 dBm and 30 dBm, so that the degradation of the efficiency will be caused. Similarly, even in a range (D in Fig. 3B) of the output power between -20 dBm and 5 dBm, there is an increase of the consumed power due to the degradation of the efficiency although it is not as much as that in the range B described above.
  • Also, as shown in Fig. 3A, the gain of each stage is usually about 25 dB, so that it is difficult to improve the degradation of the efficiency considerably by the method described above. In this regard, it is also possible to consider a method using a greater number of amplification stages, but in such a case, the minimum unit for the amplification stages that is practically feasible is expected to be 10 dB to 15 dB corresponding to the gain per one stage of a transistor.
  • In this case, there is a need to align the input/output impedance of each stage, and a conversion up to a higher impedance may be required instead of the ordinarily required conjugate matching of adjacent transistors, which can cause an increase of losses or a complication of a circuit configuration.
  • For this reason, conventionally, a method for optimizing the load line of the amplifier of arbitrary stage according to the output power has been proposed. Fig. 4A shows a circuit for realizing this conventional optimization method schematically.
  • A circuit shown in Fig. 4A realizes a method for switching an effective transistor size of the amplifier, where a plurality of amplifiers 14a and 14b are connected in parallel, while input switches Si1 and Si2 and output switches So1 and So2 are provided at the input side and the output side of these transistors 14a and 14b respectively, and input signals entered from a variable matching circuit 13i are entered into a transistor with appropriate gate length or emitter area by switching the switches Si1, Si2, So1 and So2 and amplified signals are outputted to a variable matching circuit 13o. At this point, the matching to a matching condition suitable for a respective transistor size is made by the variable matching circuits 13i and 13o.
  • In such a conventional amplifier circuit, as a result of selectively combining a plurality of transistors 14a and 14b appropriately, the unnecessary power consumption can be reduced by reducing the number of transistors that are effective at low output power so as to reduce currents and vary the maximum value thereby maximizing the efficiency at the low output.
  • In the circuit shown in Fig. 4A, the maximum output power is reduced to 1/2 by reducing the transistor size to 1/2, so that the efficiency can be maximized for the power in a narrow range of about 3 dB. However, in order to control a range as wide as 24 dB as in the case of Figs. 3A and 3B, 24/3 = 8 so that as many as 28 = 256 of divided transistor cells would be required.
  • Also, in the circuit shown in Fig. 4A, there is a need to satisfy the matching condition even when the slope of the load line changes from BK1 to BK2, so that there is a need to change the matching circuit simultaneously. Such a variable matching circuit can be realized by any of a circuit shown in Fig. 5A in which a variable inductance 11 and a variable capacitor 12 are combined, a circuit shown in Fig. 5B in which distributed constant circuits 14 to 16 are connected through switches S1 and S2, and a circuit shown in Fig. 5C in which matching circuits 13a and 13b of different types are switched by switches Si11, Si12, So11 and So12. However, the mechanisms of these circuits are all complicated so that the increase of an implementation area can be caused. Also, there are losses in the switch, the variable inductance, and the variable capacity, so that their use in the matching circuit of the power amplifier is not preferable as they can cause a degradation of the efficiency.
  • Another way of compensating the degradation of the efficiency at low output is to use an amplifier circuit as shown in Fig. 6A. This amplifier circuit realizes a method for optimizing the power source voltage to be supplied to the amplifier according to the output power, where a voltage Vdc to be applied to a transistor 17 is adjusted by variable voltage sources 9 and 10 so as to move the bias point from B2 to B1 and change the load line from K2B2 to K1B1 as shown in Fig. 6B, such that the power and the voltage amplitude on the load line are maximized. In this case, the matching of input/output can be made by constant matching circuits 18i and 18o rather than variable matching circuits.
  • In the circuit shown in Fig. 6A, the continuous output power adjustment becomes possible, but as shown in Fig. 6B, the slope of the load lines (K1B1 and K2B2) remains unchanged so that the variable matching circuit is basically unnecessary, and the RF output power for realizing the maximum efficiency is lowered by about 6 dB when the power source voltage is simply reduced to 1/2.
  • A variable voltage source with sufficiently high efficiency capable of supplying a large amount of currents to be consumed by the power amplifier can be realized by a step-down DC-DC converter as shown in Fig. 6C in which a resistance L and a capacitor C are appropriately connected by switches Q1 and Q2 controlled by a control circuit. However, the lowest output voltage is only about 1 V due to the reference voltage of the internal regulator, and the efficiency of the variable voltage source is degraded at the low voltage output, so that it is difficult to maintain the high efficiency over a wide output power range and there is also a problem that the implementation area is large.
  • Also, in the communications using the CDMA scheme, for example, there is a need to change the transmission output power according to a distance between a mobile station and a base station. This is because there is a need to align radio signals from a plurality of mobile stations at receiver input terminals of the base station. Similarly, it is preferable to align radio signals arriving from a plurality of base stations at receiver input terminals of the mobile station.
  • For this reason, the transmission power control is carried out in the communication system using the CDMA scheme, such that the transmission power varies within a range (dynamic range) of about 75 dB. Consequently, the power addition efficiency of the power amplifier is required to be high at the powers other than the maximum output power. The probability density function for the transmission powers is roughly in a form of the normal distribution, and the average transmission power of the mobile terminal is in a range of 10 dBm to 16 dBm, although it varies due to system related factors such as the arrangement of the base stations. Thus, there is a need to maintain a high power addition efficiency throughout a range of about 0 dBm (low output) to 30 dBm (high output).
    • BRIEF SUMMARY OF THE INVENTION
  • It is therefore an object of the present invention to provide a high frequency circuit capable of realizing a power amplifier with a wide dynamic range in which it is hard to degrade the power addition efficiency at low output, using a simple circuit requiring a small implementation area, as well as a compact and lightweight communication device that can be realized by using such a high frequency circuit.
  • According to one aspect of the present invention there is provided a high frequency circuit, comprising: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted.
  • According to another aspect of the present invention there is provided a communication device, comprising: at least one antenna configured to transmit or receive radio signals; at least one power amplifier configured to amplify the radio signals to be transmitted or received by the at least one antenna, including a high frequency circuit formed by: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted; and a control unit configured to control the high output amplifier cell block and the low output amplifier cell block by putting either one of the high output amplifier cell block and the low output amplifier cell block in an amplification operation state and another one of the high output amplifier cell block and the low output amplifier cell block in a high impedance state.
  • Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
    • Figs. 1A and 1B are graphs showing a relationship between the RF output power and the efficiency in a conventional power amplifier.
    • Figs. 2A and 2B are diagrams for explaining a lowering of the efficiency at low output in a conventional power amplifier.
    • Figs. 3A and 3B are a connection diagram and a gain diagram for explaining one exemplary conventional amplifier circuit.
    • Figs. 4A and 4B are a connection diagram and a graph showing a relationship between current and voltage for explaining another exemplary conventional amplifier circuit.
    • Figs. 5A, 5B and 5C are diagrams showing exemplary circuits that can be used as a variable matching circuit in the conventional amplifier circuit of Fig. 4A.
    • Figs. 6A and 6B are a connection diagram and a graph showing a relationship between current and voltage for explaining another exemplary conventional amplifier circuit.
    • Fig. 6C is a diagram showing an exemplary circuit that can be used as a variable voltage source in the conventional amplifier circuit of Fig. 6A.
    • Fig. 7 is a block diagram showing a configuration of a power amplifier using a high frequency circuit according to the first embodiment of the present invention.
    • Fig. 8 is a block diagram showing an operation state of the power amplifier of Fig. 7.
    • Figs. 9A and 9B are diagrams respectively showing internal configurations of a high output amplifier cell block and a low output amplifier cell block in the power amplifier of Fig. 7.
    • Fig. 10 is a graph showing a relationship between the output power and the efficiency in the power amplifier of Fig. 7.
    • Figs 11A and 11B are circuit diagrams respectively showing equivalent circuits of a high output amplifier cell block and a low output amplifier cell block in the power amplifier of Fig. 7.
    • Fig. 12 is a block diagram showing a configuration of a power amplifier using a high frequency circuit according to the second embodiment of the present invention.
    • Figs. 13A, 13B and 13C are diagrams respectively showing internal configurations of a high output amplifier cell block, a middle output amplifier cell block and a low output amplifier cell block in the power amplifier of Fig. 12.
    • Fig. 14 is a block diagram showing a configuration of a power amplifier using a high frequency circuit according to the third embodiment of the present invention.
    • Fig. 15 is a block diagram showing a configuration of a power amplifier using a high frequency circuit according to the fourth embodiment of the present invention.
    • Figs. 16A and 16B are diagrams showing exemplary configurations of a power amplifier using a high frequency circuit according to the fifth embodiment of the present invention.
    • Figs. 17A, 17B and 17C are diagrams showing exemplary configurations of a power amplifier using a high frequency circuit according to the fifth embodiment of the present invention.
    • Figs. 18A and 18B are diagrams showing exemplary configurations of a power amplifier using a high frequency circuit according to the fifth embodiment of the present invention.
    • Figs. 19A, 19B and 19C are diagrams showing exemplary configurations of a power amplifier using a high frequency circuit according to the sixth embodiment of the present invention.
    • Figs. 20A and 20B are diagrams showing exemplary configurations of communication devices using a high frequency circuit of the present invention according to the seventh embodiment of the present invention.
    DETAILED DESCRIPTION OF THE INVENTION
  • In the following description, a phrase "amplifier cells connected in parallel AC-wise" will be used to imply that target amplifier cells of nearly identical size are connected at nearly identical phase with nearly identical amplitude. Strictly speaking from a viewpoint of distributed constant circuits, a connection at exactly identical phase with exactly identical amplitude is difficult to realize in practice, so that a phase "amplifier cells connected in parallel AC-wise" can be construed as meaning that the efficiencies of the power distribution at the input side and the power composition at the output side of a plurality of cell blocks, such as cell blocks 4a and 4b, 4c and 4d shown in Figs. 9A and 9B to be described below or transistors Q1 and Q2 shown in Figs. 11A and 11B to be described below, are both greater than or equal to 50%, for example. In the case of splitting into N, these efficiencies of the power distribution and the power composition are given given by the following expression: S 1 T + S 2 T + S 3 T + ⋯ + S n T / S 1 T + S 2 T + S 3 T + ⋯ + S n T
    Figure imgb0001
    where SnT is an S parameter vector for transmission of a common terminal T of the distribution and composition circuits to an n-th split port.
  • Also, in the following description, a phrase "DC power source voltage is supplied in parallel" will be used to imply that nearly identical level of voltage is applied to target cells. Strictly speaking, it is practically difficult to apply exactly identical level of voltage because of a voltage dropping due to circuit losses, so that a phrase "DC power source voltage is supplied in parallel" can be construed as meaning that the voltage is applied within a tolerable range of ±20% with respect to a plurality of cell blocks, such as cell blocks 4a to 4c shown in Figs. 9A and 9B to be described below, or cells that constitute these cell blocks.
  • Also, in the following description, a phrase "DC power source voltage is supplied in series" will be used to imply that, when the "amplifier cells connected in parallel AC-wise" are transistor cells Q1 and Q2 as shown in Fig. 11B to be described below, the voltage given at a collector of the transistor cell Q1 is applied to these plurality of transistor cells in division, in such a way that the DC flows from a collector of the transistor cell Q1 through an emitter to a collector of the transistor cell Q2 and is then grounded, for example. In this example, the case of the emitter grounding in the bipolar transistor is described, but the above phrase should be construed as meaning that the voltage is applied to a plurality of transistors in division, even in the case of using field effect transistors or different grounding forms.
  • Also, in the following description, a term "transistor cell" will be used to indicate a set of transistors having nearly identical characteristics. Strictly speaking from a viewpoint of the device process, it is practically difficult to fabricate transistors with exactly identical characteristics. Even if geometrically similar transistors are used, they may not operate as identical transistors depending on their layout positions on a semiconductor chip or differences in their surrounding electromagnetic and thermal environments due to a substrate on which the semiconductor chip is implemented, etc. Also, even within a semiconductor wafer, geometrically similar transistors may not necessary have identical characteristics, due to the non-uniformity of characteristics which is a well known problem associated with transistors in general.
  • Note that a set of transistors are formed by bundling a plurality of tiny unit transistors (in units of gate in the case of FETs, in units of emitter or base in the case of bipolar transistors, for example) that are physically independent in the power amplifier. If a sufficient power cannot be obtained in this state, an even larger transistor is formed by bundling these transistors. As such, a transistor used in the power amplifier is a set of a plurality of tiny transistors in general.
    • [First Embodiment] (Overall configuration)
  • Now, the first embodiment of a high frequency circuit according to the present invention will be described in detail with references to the drawings.
  • Fig. 7 shows an exemplary configuration of a power amplifier formed by using a high frequency circuit of this embodiment.
  • As shown in Fig. 7, the power amplifier according to this embodiment comprises an input matching circuit 3i, a first connection unit 2i for splitting signals entered from the input matching circuit 3i, a high output amplifier cell block 1a, a low output amplifier cell block 1b, a second connection unit 2o to which signals from the high output amplifier cell block 1a and the low output amplifier cell block 1b are entered, and an output matching circuit 3o.
  • The high output amplifier cell block 1a has amplifier cells which are connected in parallel AC-wise with respect to input and output signals, and DC power source voltage is supplied in parallel to these amplifier cells. On the other hand, the low output amplifier cell block 1b has amplifier cells that are connected in parallel AC-wise with respect to input and output signals, and DC power source voltage is supplied in series to these amplifier cells.
  • The high output amplifier cell block 1a has a signal input terminal INa, a signal output terminal OUTa, a power source voltage terminal Vdca, and a control voltage terminal Vcnta, and the low output amplifier cell block 1b has a signal input terminal INb, a signal output terminal OUTb, a power source voltage terminal Vdcb, and a control voltage terminal Vcntb.
  • In this embodiment, each one of the first and second connection units 2i and 2o is formed by using only passive elements such as coils and capacitors, so as to provide a splitting circuit formed by transmission paths, for example, as indicated in the second connection unit 2o shown in Fig. 8. Namely, the use of active elements for switching signal paths such as switches used in the conventional circuits of Figs. 4A, 5A, 5B and 5C in addition to active elements for amplifying RF signals can cause the complication of a circuit configuration, the increase of the required number of parts, the increase of the implementation area, and the degradation of signals due to distortion or loss, which can lead to the higher cost and the lower performance. For this reason, the use of such active elements is avoided in this embodiment and the first and second connection units 2i and 2o are formed by using only passive elements in order to achieve the equivalent or better effects by a simpler configuration.
    • (Configuration of amplifier cell blocks)
  • Next, the configurations of the high output amplifier cell block 1a and the low output amplifier cell block 1b will be described.
  • Fig. 9A and Fig. 9B show exemplary internal configurations of the high output amplifier cell block 1a and the low output amplifier cell block 1b respectively. Note that amplifier cells 4a, 4b, 4c and 4d used in this embodiment are formed by transistors of the same size.
  • As shown in Fig. 9A, the high output amplifier cell block 1a of this embodiment has two amplifier cells 4a and 4b, and these amplifier cells 4a and 4b are connected in parallel with respect to the input and output signals, and also connected in parallel with respect to the DC power source voltage Vdca. In addition, the control voltage Vcnta is also given in parallel to the amplifier cells 4a and 4b.
  • As shown in Fig. 9B, the low output amplifier cell block 1b of this embodiment has two amplifier cells 4c and 4d, and these amplifier cells 4c and 4d are connected in parallel with respect to the input and output signals, and also connected in series with respect to the DC power source voltage Vdcb. In addition, the control voltage Vcntb is also given in parallel to the amplifier cells 4c and 4d.
  • The amplifier cells 4c and 4d in the low output amplifier cell block 1b are connected by an AC/DC separation unit 5 such as bias T, for example, and this AC/DC separation unit 5 realizes a grounding of AC of the amplifier cell 4c, while DC is applied to the DC power source terminal of the amplifier cell 4d. As a result, the DC power source voltage applied to the amplifier cells 4c and 4d is divided into two equal parts, i.e., 1/2 each.
  • In this embodiment, the number of the amplifier cells 4a and 4b in the high output amplifier cell block 1a is set equal to the number of the amplifier cells 4c and 4d in the low output amplifier cell block 1b, so that the input and output impedances are equal ideally speaking. Consequently, the slopes of the load lines can be made identical by using the common input and output matching circuits 3i and 3o. In this case, for the high output amplifier cell block 1a and the low output amplifier cell block 1b, the power source voltage is 1/2 and the load line is identical so that the maximum current also becomes 1/2 and the maximum output power can be reduced to 1/4 (-6 dB).
  • This embodiment is equivalent to a state in which the bias voltage B1 becomes 1/2 of the bias voltage B2 in Fig. 6B. For example, in the case of forming a power amplifier with the maximum output power of 30 dBm, if the maximum output power of the high output amplifier cell block 1a is set to 30 dBm, the maximum output power of the low output amplifier cell block 1b can be about 24 dBm because the power source voltage is 1/2.
  • For the output power greater than or equal to 24 dBm, the high output amplifier cell block 1a is put in an operation state while the low output amplifier cell block 1b is put in a non-operation state.
  • As already described with references to Figs. 1A and 1B, the efficiency will be lowered as the output power becomes lower than the maximum output power 30 dBm. When the output power is about 24 dBm which is the maximum output power of the low output amplifier cell block 1b, the efficiency is lowered to 35.4%. At this point, the high output amplifier cell block 1a is put in a non-operation state while the low output amplifier block 1b is put in an operation state, such that the efficiency is recovered to 72% again, and them lowered to 35% again as the output power is lowered further. In this way, by providing a plurality of amplifier cell blocks, the efficiency can be recovered to about 72% even at the low output, so that a relationship between the efficiency and the output power becomes a saw-tooth shaped line with about 6 dB interval between adjacent peaks as shown in Fig. 10.
  • Figs. 11A and 11B show equivalent circuits of the high output amplifier cell block 1a and the low output amplifier cell block 1b shown in Figs. 9A and 9B respectively.
  • In Figs. 11A and 11B, C1, C1' and C2 are DC preventing capacitors, L1, L1' and L2 are RF chokes, R1 and R1' are stabilizing resistors, and Q1 and Q2 are bipolar transistors. Note that the same effects can also be realized by using field effect transistors for Q1 and Q2.
  • Also in Fig. 11B, C3 is a DC preventing capacitor for separating collectors of Q1 and Q2 DC-wise, and C4 and L4 forms a filter which functions as the AC/DC separation unit 5 in this embodiment. Namely, C4 realizes the AC-wise grounding in the signal frequency of Q1.
    • (Operation and effect)
  • The power amplifier according to this embodiment in a configuration as described above operates as follows.
  • First, signals entered from an input terminal IN are entered into the high output amplifier cell block 1a and the low output amplifier cell block 1b through the input matching circuit 3i and the first connection unit 2i. The output signals of the high output amplifier cell block 1a and the low output amplifier cell block 1b are outputted from an output terminal OUT through the second connection unit 2o and the output matching circuit 3o.
  • Here, in the high frequency circuit according to this embodiment, one of the amplifier cell blocks 1a and 1b is selected according to the power to be outputted, and these amplifier cell blocks 1a and 1b are switched between an amplification operation state and a non-operation state with high impedance, by the control voltages Vcnta and Vcntb. Only one amplifier cell block is put in the amplification operation state at any given moment. For example, as shown in Fig. 8, when the high output amplifier cell block 1a is put in the amplification operation state, the low output amplifier cell block 1b is put in a high impedance non-operation state.
  • The input and output impedances of the low output amplifier cell block 1b in the high impedance non-operation state can be expressed as capacitances Ci and Co respectively. The resistance component that is entered into open capacitances is ignored here as it only causes a negligible loss compared with the output impedance of the high output cell block 1a. The load impedance from a viewpoint of an output node 6a of the high output amplifier cell block 1a is that of a parallel connection of the output matching circuit 3o and a stab with the open capacitance Co beyond a splitting point node 6c. Here, there is a need to select a distance between nodes 6a and 6c and a distance between nodes 6b and 6c such that the impedance of the stab with the open capacitance Co does not satisfy a short circuit condition. By setting the non-operating transistor in the high impedance state, the operating amplifier cell block can be selected without using any switch.
    • [Second Embodiment]
  • Next, the second embodiment of the present invention will be described in detail.
  • The first embodiment described above is directed to the case of using two amplifier cell blocks as shown in Fig. 7, but the present invention is not limited to this specific case.
  • For example, the number of steps connected in series with respect to DC in the low output amplifier cell block is two in the first embodiment, but this number can be increased to four, eight, and so on. In the case of four steps, for example, the three types of amplifier cell blocks using one step, two steps, and four steps may be used, or two types of amplifier cell blocks using one step and four steps may be used. Similarly, in the case of eight steps, four types of amplifier cell blocks using one step, two steps, four steps and eight steps may be used, or any three types out of these four types may be used, or any two types out of these four types may be used. It should be apparent that the circuit configuration becomes more complicated when the number of steps is increased. The number of steps to be used should be selected by taking the effect at a time of the power control into consideration.
  • Note that the number of steps need not takes a form of 2n, but it is assumed to be in a form of 2n here. When the largest number of steps is N = 2n, up to n+1 types of the amplifier cell blocks using the respective number of steps equal to 1, 2, 4, ····· , 2n can be used. The choice of the types of the amplifier cell blocks to be used in combination is arbitrary as described above, but it should be noted that the use of the same number of steps in different amplifier cell blocks would result in a poor circuit efficiency.
  • Now, the exemplary case of n = 2 and using three amplifier cell blocks will be described with reference to Fig. 12. In this example, the dynamic range greater than or equal to 12 dB can be realized.
  • As shown in Fig. 12, the power amplifier according to this embodiment comprises an input matching circuit 3i, a first connection unit 2i for splitting signals entered from the input matching circuit 3i, a high output amplifier cell block 1c, a middle output amplifier cell block 1d, a low output amplifier cell block 1e, a second connection unit 2o to which signals from the high output amplifier cell block 1c, the middle output amplifier cell block 1d and the low output amplifier cell block 1e are entered, and an output matching circuit 3o.
  • In further detail, as shown in Fig. 13A, the high output amplifier cell block 1c of this embodiment has four amplifier cells 4e to 4h, and these amplifier cells 4e to 4h are connected in parallel with respect to the input and output signals, and also connected in parallel with respect to the DC power source voltage Vdcc. In addition, the control voltage Vcntc is also given in parallel to the amplifier cells 4e to 4h.
  • Also, as shown in Fig. 13B, the middle output amplifier cell block 1d of this embodiment has two amplifier cells 4i and 4l, and these amplifier cells 4i to 4l are connected in parallel with respect to the input and output signals. Also, a pair of the amplifier cells 4i and 4j and a pair of the amplifier cells 4k and 4l are connected in series with respect to the DC power source voltage Vdcd while the first stage amplifier cells 4i and 4k of these pairs are connected in parallel. In addition, the control voltage Vcntd is also given in parallel to the amplifier cells 4i and 4l.
  • Each pair of the amplifier cells 4i and 4j, or 4k and 4l, in the middle output amplifier cell block 1d are connected by an AC/DC separation unit 5 such as bias T, for example, and this AC/DC separation unit 5 realizes a grounding of AC of the amplifier cells 4i and 4k, while DC is applied to the DC power source terminals of the second stage amplifier cells 4j and 4l. As a result, the DC power source voltage applied to the amplifier cells 4i to 4l is divided into two equal parts, i.e., 1/2 each.
  • Also, as shown in Fig. 13C, the low output amplifier cell block 1e of this embodiment has four amplifier cells 4m to 4p, and these amplifier cells 4m to 4p are connected in parallel with respect to the input and output signals, and also connected in series with respect to the DC power source voltage Vdce. In addition, the control voltage Vcnte is also given in parallel to the amplifier cells 4m to 4p.
  • The amplifier cells 4m to 4p in the low output amplifier cell block 1e are connected by an AC/DC separation unit 5 such as bias T, for example, and this AC/DC separation unit 5 realizes a grounding of AC of the amplifier cell 4m to 4o, while DC is applied to the DC power source terminal of the amplifier cell 4n to 4p. As a result, the DC power source voltage applied to the amplifier cells 4m to 4p is divided into four equal parts, i.e., 1/4 each.
  • In the power amplifier according to this embodiment, by connecting three amplifier cell blocks 1c, 1d and 1e, it becomes possible to realize a wider dynamic range compared with the first embodiment described above. Note that the dynamic range can be widened easily by increasing the number of steps to be connected in series with respect to DC in the amplifier cell block further. For example, the dynamic range greater than or equal to 18 dB can be realized by using four amplifier cell blocks where each amplifier cell block is formed by eight divided amplifier cells and a division of the DC power source voltage in eight steps (1/8) at most.
    • [Third Embodiment]
  • Next, the third embodiment of the present invention will be described in detail.
  • In the first embodiment described above, as shown in Figs. 11A and 11B, the DC power source voltage Vdc is entered through L2 and the flow of DC to the output terminal is prevented by the DC preventing capacitor C2. In this embodiment, as shown in Fig. 14, the DC power source voltage Vdc is given from a node 6c side by using a circuit through which DC can flow as the second connection unit 2o.
  • More specifically, as shown in Fig. 14, the high output amplifier cell block 1a' of this embodiment has a structure in which the signals entered from the first connection unit 2i are entered into the bipolar transistors Q1H and Q2H in parallel through the DC preventing capacitor C1H while the control voltage Vcnt1 is entered into the bipolar transistors Q1H and Q2H in parallel through the stabilizing resistor R1H and the RF choke L1H. Vdc is entered into the bipolar transistors Q1H and Q2H in parallel from the second connection unit 2o side through L2.
  • On the other hand, the low output amplifier cell block 1b' of this embodiment has a structure in which the signals entered from the first connection unit 2i are entered into the bipolar transistors Q1L and Q2L in parallel through the DC preventing capacitor C1L while the control voltage Vcnt2 is entered into the bipolar transistors Q1L and Q2L in parallel through the stabilizing resistor R1L and the RF choke L1L.
  • In this low output amplifier cell block 1b', Vdc is entered into the bipolar transistors Q1L and Q2L in series DC-wise from the second connection unit 2o side through L2. Namely, using the DC preventing capacitor C3 and the RF choke L4, only DC is allowed to flow from the bipolar transistor Q1L to the bipolar transistor Q2L. Also, the grounding of AC is realized by the decoupling capacitor C4.
  • Then, as shown in Fig. 14, C2 and L2 are removed from the high output amplifier cell block 1a shown in Fig. 11A and the low output amplifier cell block 1b shown in Fig. 11B, and the DC power source voltage is applied at a common power source voltage terminal Vdc through L2 from the node 6c of the second connection unit 2o. Note that C2 shown in Fig. 14 is a DC cut for the output matching circuit 3o.
  • According to this third embodiment, the DC power source voltage Vdc is supplied from the node 6c side so that L2 and C2 shown in Figs. 11A and 11B in the first embodiment described above become unnecessary, and it is possible to reduce the circuit area.
  • Note that, as a modification of this embodiment, it is also possible to supply the DC power source voltage from an open stab within the output matching circuit 3o, for example, instead of placing L2 and C2 at positions as shown in Fig. 14.
    • [Fourth Embodiment]
  • Next, the fourth embodiment of the present invention will be described in detail.
  • In the power amplifier of the first to third embodiments described above, there can be a problem that the number of control signals Vcnt increases when the number of amplifier cell blocks is increased. This problem can be resolved in this embodiment as follows.
  • Using a method similar to the third embodiment described above, two control lines Vcnt1 and Vcnt2 can be commonly supplied from the first connection unit 2i side. Fig. 15 shows an exemplary configuration in this case.
  • More specifically, as shown in Fig. 15, the high output amplifier cell block 1a" of this embodiment has a structure in which the signals entered from the first connection unit 2i are entered into the bipolar transistors Q1H and Q2H in parallel through the DC preventing capacitor C5H while the control voltage Vcnt is entered into a bias circuit BCH also from the first connection unit 2i side. This bias circuit BCH generates the control signal Vcnt1 according to the control voltage Vcnt, and Vcnt1 generated by this bias circuit BCH is entered into the bipolar transistors Q1H and Q2H in parallel. Vdc is entered into the bipolar transistors Q1H and Q2H in parallel from the second connection unit 2o side by the configuration similar to that of the third embodiment.
  • On the other hand, the low output amplifier cell block 1b" of this embodiment has a structure in which the signals entered from the first connection unit 2i are entered into the bipolar transistors Q1L and Q2L in parallel through the DC preventing capacitor C5L while the control voltage Vcnt is entered into a bias circuit BCL also from the first connection unit 2i side. This bias circuit BCL generates the control signal Vcnt2 according to the control voltage Vcnt, and Vcnt2 generated by this bias circuit BCL is entered into the bipolar transistors Q1L and Q2L in parallel.
  • In this low output amplifier cell block 1b", Vdc is entered into the bipolar transistors Q1L and Q2L in series DC-wise from the second connection unit 2o side. Namely, using the DC preventing capacitor C3 and the RF choke L4, only DC is allowed to flow from the bipolar transistor Q1L to the bipolar transistor Q2L. Also, the grounding of AC is realized by the decoupling capacitor C4.
  • Then, in the power amplifier of this embodiment, control signals Vcnt1 and Vcnt2 are generated according to the common control voltage Vcnt by the bias circuits BCH and BCL respectively. The control signal Vcnt1 generated by the bias circuit BCH is supplied to the transistors Q1H and Q2H through a high frequency choke inductor L6H, and the control signal Vcnt2 generated by the bias circuit BCL is supplied to the transistors Q1L and Q2L through a high frequency choke inductor L6L.
  • According to the power amplifier of this embodiment, the common control voltage Vcnt is used for the amplifier cell blocks so that even when the number of the amplifier cell blocks is increased, the amount of wirings for the control signals can be reduced and it is possible to reduce the circuit size.
  • Note that it is also possible to reduce the number of control lines by binarizing or n-arizing a plurality of control signals and generate the control signals by decoding the binarized or n-arized control signals at a bias circuit of each amplifier cell block.
    • [Fifth Embodiment]
  • Next, the fifth embodiment of the present invention will be described in detail. Figs. 16A, 16B, 17A, 17B, 17C, 18A and 18B show various configuration s of the power amplifier according to the fifth embodiment.
  • In the power amplifier of the firth to fourth embodiments described above, the amplifier cell blocks can be mounted on separate semiconductor chips as shown in Fig. 16A. Namely, the high output amplifier cell block 1a and the low output amplifier cell block 1b can be formed by independent semiconductor chips and mounted on a substrate GND. In this case, the amplifier cell blocks are connected with the first and second connection units 2i and 2o by bonding wires, and the control voltages Vcnt1 and Vcnt2 are also entered from an external of the substrate GND by bonding wires.
  • It is also possible to mount a plurality of amplifier cell blocks on an identical semiconductor chip as shown in Fig. 16B. Namely, the high output amplifier cell block 1a and the low output amplifier cell block 1b are formed by an identical semiconductor chip and mounted on the substrate GND. In this case, the amplifier cell blocks are connected with the first and second connection units 2i and 2o by bonding wires, and the control voltages Vcnt1 and Vcnt2 are also entered from an external of the substrate GND by bonding wires. In this case of mounting on an identical chip, a ground electrode can be formed wide so that the ground inductance can be reduced.
  • In addition, in the case of mounting a plurality of amplifier cell blocks on an identical semiconductor chip, it is also possible to incorporate a part of the T splitting of the first and second connection units 2i and 2o into the chip.
  • It is also possible to arrange the amplifier cells of different amplifier cell blocks in various ways. Namely, the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged as upper and lower halves of the amplifier cells as shown in Fig. 17A, or the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged alternately as shown in Fig. 17B.
  • It is also possible to arrange the amplifier cells in more than one rows as shown in Figs. 17C, 18A and 18B, depending on the chip shape. In the case of arranging the amplifier cells in two rows, the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged in different rows as shown in Fig. 17C, or the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged as upper and lower halves of the amplifier cells in both rows as shown in Fig. 18A, or the amplifier cells of the high output amplifier cell blocks 1a and the low output amplifier cell blocks 1b can be arranged in a zigzag pattern as shown in Fig. 18B.
  • In the case of using two amplifier cell blocks, only one of the high output amplifier cell block 1a and the low output amplifier cell block 1b is operated at any given moment, so that by arranging the heat generating amplifier cells of each amplifier cell block in a distributed form, it becomes possible to distribute the heat generation sources even when different amplifier cell blocks are arranged together, so that there is no need to thin the amplifier cell elements in order to deal with the heat generation or the ground inductance, and it becomes possible to minimize the increase of the chip area.
    • [Sixth Embodiment]
  • Next, the sixth embodiment of the present invention will be described in detail. Figs. 19A, 19B and 19C show various configuration s of the power amplifier according to the sixth embodiment.
  • In the first to fifth embodiments described above, the the transistors of each amplifier cell block have the uniform size and the same impedance, and the input and output connection units are provided symmetrically, because the operation principle of the power amplifier of the present invention is based on the parallel shift of the load line using the bias voltage as shown in Fig. 6B.
  • However, in practice, the load line is not necessarily a straight line and the parallel shift of the load line with the fixed source and load impedances may not necessarily be optimal because of the influence of the knee voltage. In such cases, there is a need for the fine tuning of the source and load impedances in each amplifier cell block, which can be done as follows.
  • First, as shown in Fig. 19A, the input and output connection units 2i and 2o can be formed asymmetrically along a vertical direction (i.e., with respect to the high output amplifier cell block 1a and the low output amplifier cell block 1b). The fine tuning of the impedances can then be realized by changing widths or lengths of a pattern of a distributed constant lines of the input and output connection units 2i and 2o, changing lengths, numbers or intervals of the bonding wires, or by mounting chip parts.
  • Second, different transistor sizes can be used for different amplifier cell blocks. For example, as shown in Fig. 19B, the fine tuning of the impedances can be realized by setting the number of amplifier cells for the high output amplifier cell block 1a greater than that for the low output amplifier cell block 1b such that the transistor size of the high output amplifier cell block 1a becomes larger than that of the low output amplifier cell block 1b.
  • Third, the fine tuning of the impedances can be realized by devising the cell arrangement positions on the chip such that different amplifier cell blocks have different distances with respect to the matching circuits. For example, as shown in Fig. 19C, the arrangement of the high output amplifier cell block 1a can be biased toward the first connection unit 2i side, while the arrangement of the low output amplifier cell block 1b can be biased toward the second connection unit 2o side.
    • [Seventh Embodiment]
  • Next, the seventh embodiment of the present invention will be described in detail. This embodiment is directed to an application of the power amplifier according to the present invention to transmit and receive amplifiers used in a communication device of a radio system.
  • Namely, as shown in Fig. 20A, the communication device according to the present invention has a radio unit 100 which comprises antennas 101 and 102 for transmitting and receiving radio signals, an antenna duplexer/switch 103 for switching connection of the antennas 101 and 102, a transmit amplifier 104 and a receive amplifier 105 with the power amplifier of any of the above embodiments incorporated therein, a modulator 106 for modulating signals to be inputted into the transmit amplifier 104, a demodulator 108 for demodulating signals outputted from the receive amplifier 105, and a synthesizer 107 for carrying out a synchronization processing with a baseband signal processing unit 109.
  • The communication device of this embodiment also has the baseband signal processing unit 109 for carrying out a signal processing with respect to input/output signals of the radio unit 100, an input/output unit 110 for inputting/outputting input/output signals of the baseband signal processing unit 109 with respect to an external, a control unit 111 for controlling operations of the radio unit 100, the baseband signal processing unit 109 and the input/output unit 110, and a power source 112 for supplying power source voltages to the radio unit 100, the baseband signal processing unit 109 and the input/output unit 110. Note that the input/output unit 110 has a microphone 110a and keys 110d as input interface for receiving input speeches or operations from the external, and a speaker 110b, a display 110c and a vibrator 110e as output interface with respect to the external.
  • In this communication device, the input speeches or operation signals entered from the microphone 110a or keys 110d of the input/output unit 110 are applied with the signal processing at the baseband signal processing unit 109 under the control of the control unit 111, and entered into the transmit amplifier 104 through the modulator 106. These signals are amplified by the amplification processing as described above at the transmit amplifier 104 and transmitted from the antenna 101 or 102 through the antenna duplexer/switch 103.
  • On the other hand, radio signals received by the antenna 101 or 102 are amplified by the receive amplifier 105 through the antenna duplexer/switch 103 under the control of the control unit 111, and converted into control signals at the baseband signal processing unit 109 through the demodulator 108, to control the operations of the speaker 110b, the display 110c and the vibrator 110e of the input/output unit 110.
  • It is also possible to apply the power amplifier according to the present invention to a base station of a mobile communication system as shown in Fig. 20B.
  • Namely, as shown in Fig. 20B, the base station of the mobile communication system according to this embodiment has at least one radio unit 200 which comprises antennas 201 and 202 for transmitting and receiving radio signals, an antenna duplexer/switch 203 for switching connection of the antennas 201 and 202, a transmit amplifier 204 and a receive amplifier 205 with the power amplifier of any of the above embodiments incorporated therein, and a modem 206 for modulating signals to be inputted into the transmit amplifier 204 and demodulating signals outputted from the receive amplifier 205.
  • The base station of this embodiment also has a baseband signal processing unit 207 for carrying out a signal processing with respect to input/output signals of the radio unit 200, a transmission path connection unit 208 for inputting/outputting input/output signals of the baseband signal processing unit 207 with respect to an external, a control unit 209 for controlling operations of the radio unit 200, the baseband signal processing unit 207 and the transmission path connection unit 208, and a power source 210 for supplying power source voltages to the radio unit 200, the baseband signal processing unit 207 and the transmission path connection unit 208.
  • In this base station, the signals entered from the external are entered into the baseband signal processing unit 207 through the transmission path connection unit 208, applied with the signal processing at the baseband signal processing unit 207, and entered into the transmit amplifier 204 through the modem 206. These signals are amplified by the amplification processing as described above at the transmit amplifier 204 and transmitted from the antenna 201 or 202 through the antenna duplexer/switch 203.
  • On the other hand, radio signals received by the antenna 201 or 202 are amplified by the receive amplifier 205 through the antenna duplexer/switch 203, and converted into control signals at the baseband signal processing unit 207 through the modem 206 and outputted to the external through the transmission path connection unit 208.
  • The power amplifier of the present invention is suitable for a system that requires the power amplifier with a wide output power range. For example, it is effective for communications with a mobile station as described above or even for communications between fixed stations where the radio propagation environment can be easily changed. It is also effective in a mobile communication system such as a portable telephone system, especially a mobile communication system using the CDMA scheme that requires a wide dynamic range.
  • As described, according to the present invention, it is possible to realize a power amplifier capable of realizing a high efficiency operation over a wide output power range, without using variable voltage sources such as switches, variable matching circuits, DC-DC converters, etc. The high frequency circuit of the present invention can be mounted on MMIC (Monolithic Microwave Integrated Circuit) so that it can be utilized in the power amplifier for the portable telephone or the like which has a severe power consumption requirement, and it is possible to extend the continuous operation time of the portable telephone or the like considerably.
  • According to the present invention, the high output amplifier cell block is operated at a time of the high output and the low output amplifier cell block is operated at a time of the low output where the low output amplifier cell block has the maximum efficiency, so that it is possible to eliminate the wasteful power consumption by the high output amplifier cell block. Also, in the high output amplifier cell block, the amplifier cell blocks are connected in parallel AC-wise, and the voltage nearly equal to the input voltage is applied to the amplifier cells at nearly the same phase, so that it is possible to realize the high output amplification without causing a phase displacement among the amplifier cells. On the other hand, in the low output amplifier cell block, the amplifier cells are connected in series AC-wise, and a divided low voltage is applied to the amplifier cells at nearly the same phase, so that it is possible to realize the low output amplification without causing a phase displacement among the amplifier cells.
  • In addition, according to the present invention, only one of the amplifier blocks is put in the amplification operation state according to the output power while the other amplifier cell blocks are put in the high impedance non-operation state, so that the non-operating amplifier cell blocks can be regarded by the connection units as open capacitances with high impedances which do not affect the amplifier cell block in the operation state.
  • In particular, by increasing the number of steps of the amplifier cells to be connected in series with respect to the power source voltage, the output power with the maximum efficiency can be lowered by about 6 dB per one step. Moreover, the power amplifier in a compact size can be realized because the variable voltage sources such as switches, variable matching circuits, DC-DC converters, etc. are not required for the purpose of switching signal paths.
  • It is also to be noted that, besides those already mentioned above, many modifications and variations of the above embodiments may be made without departing from the novel and advantageous features of the present invention. Accordingly, all such modifications and variations are intended to be included to the extent that they fall within the scope of the appended claims.

Claims (14)

  1. A high frequency circuit, comprising:
    a high output amplifier cell block (1a) configured to amplify input signals at a time of high output power, in which a DC power source voltage (Vdc) is supplied in parallel to first amplifier cells (4a, 4b) that are connected in parallel AC-wise with respect to input/output signals;
    a low output amplifier cell block (1b) configured to amplify the input signals at a time of low output power, in which the DC power source voltage (Vdc) is supplied in series to second amplifier cells (4c, 4d) that are connected in parallel AC-wise with respect to the input/output signals;
    a first connection unit (2i) configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and
    a second connection unit (2o) configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted.
  2. The high frequency circuit of claim 1, wherein the high output amplifier cell block and the low output amplifier cell block are controlled by control voltages to put either one of the high output amplifier cell block and the low output amplifier cell block in an amplification operation state and another one of the high output amplifier cell block and the low output amplifier cell block in a high impedance state.
  3. The high frequency circuit of claim 2, wherein the first and second connection units are formed by passive elements alone and configured to maintain a matching state with respect to the low output amplifier cell block when the high output amplifier cell block is in the high impedance state or a matching state with respect to the high output amplifier cell block when the low output amplifier cell block is in the high impedance state.
  4. The high frequency circuit according to any one of claims 1-3 comprising:
    at least one middle output amplifier cell block configured to amplify the input signals at a time of middle output power, in which the DC power source voltage is supplied in parallel to third amplifier cells and in series to fourth amplifier cells that are connected in parallel AC-wise with respect to the input/output signals.
  5. The high frequency circuit according to any one of the preceding claims, wherein the DC power source voltage is supplied from an output port side of the second connection unit.
  6. The high frequency circuit according to any one of the preceding claims, wherein a common control voltage for controlling the high output amplifier cell block and the low output amplifier cell block is supplied from an input port side of the first connection unit.
  7. The high frequency circuit according to any one of the preceding claims, wherein the high output amplifier cell block and the low output amplifier cell block are mounted on separate semiconductor chips.
  8. The high frequency circuit according to any one of claims 1-6, wherein the high output amplifier cell block and the low output amplifier cell block are mounted on a single semiconductor chip.
  9. The high frequency circuit of claim 8, wherein the first amplifier cells and the second amplifier cells are arranged in a distributed pattern over the single semiconductor chip.
  10. The high frequency circuit according to any one of the preceding claims, wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by forming the first and second connection units asymmetrically with respect to the high output amplifier cell block and the low output amplifier cell block.
  11. The high frequency circuit according to any one of claims 1-9, wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by using different transistor sizes for the high output amplifier cell block and the low output amplifier cell block.
  12. The high frequency circuit according to any one of claims 1-9, wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by arranging the first amplifier cells and the second amplifier cells at different distances from matching circuits to be connected at an input side of the first connection unit and an output side of the second connection unit.
  13. A communication device, comprising:
    at least one antenna configured to transmit or receive radio signals;
    at least one power amplifier configured to amplify the radio signals to be transmitted or received by the at least one antenna, including a high frequency circuit according to claim 1; and
    a control unit configured to control the high output amplifier cell block and the low output amplifier cell block by putting either one of the high output amplifier cell block and the low output amplifier cell block in an amplification operation state and another one of the high output amplifier cell block and the low output amplifier cell block in a high impedance state.
  14. The communication device of claim 13, wherein the at least one power amplifier includes a first power amplifier configured to amplify the radio signals to be transmitted from the at least one antenna, and a second power amplifier configured to amplify the radio signals received by the at least one antenna.
EP01303251A 2000-04-05 2001-04-05 High frequency circuit using high output amplifier cell block and low output amplifier cell block Expired - Lifetime EP1148633B1 (en)

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JP2000103784A JP3600115B2 (en) 2000-04-05 2000-04-05 High frequency circuit and communication system
JP2000103784 2000-04-05

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EP1148633A1 (en) 2001-10-24
US20050024136A1 (en) 2005-02-03
US6804500B2 (en) 2004-10-12
DE60124448T2 (en) 2007-05-03
KR100602140B1 (en) 2006-07-19
DE60124448D1 (en) 2006-12-28
US20010029168A1 (en) 2001-10-11
JP2001292033A (en) 2001-10-19
JP3600115B2 (en) 2004-12-08
KR20010094998A (en) 2001-11-03
US6927625B2 (en) 2005-08-09

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