Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/115—Via connections; Lands around holes or via connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/111—Pads for surface mounting, e.g. lay-out
  • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09218—Conductive traces
  • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10621—Components characterised by their electrical contacts
  • H05K2201/10734—Ball grid array [BGA]; Bump grid array
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/42—Plated through-holes or plated via connections
  • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
  • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards

Definitions

• the invention relates to printed circuit boards, in particular of high density.
• a multilayer printed circuit board is made of a stack of alternately conductive and insulating layers fixed together.
• Each insulating layer is commonly made of a glass fabric and a resin while each conductive layer is commonly made of a metallic network of copper formed on one side of an insulating layer.
• two neighboring conductive layers are formed on the two respective faces of one insulating layer on two, which then constitutes a laminate (state C of the layer).
• the other insulating layers constitute prepregs (pre-preg in English) corresponding to state B of the insulating layers.
• This stack is heated and pressed so as to make a compact card.
• the card is pierced with connection holes, which are wholly or partly made of holes traversing the entire card.
• Each of these holes crosses superimposed metal areas, formed in the metal layers which are to be connected to the hole.
• certain laminates carry through holes for the connection of the metallic layers which they carry. These holes may exist in interior laminates and are called buried holes. They can also exist in at least one of the exterior laminates and are then called blind holes. At least one of the two main exterior faces of the card can be made of an etched conductive layer to form connection pads for components, including integrated circuit packages. The pads are therefore distributed in more or less large zones intended for the connection of respective components.
• the very high integration of current integrated circuits means that they can have a very large number of input-output terminals (more than five hundred) distributed over a small area (only a few square centimeters), therefore according to a high density.
• the current technique consists in using housings of the type with a grid of solder balls also known by the name of BGA (Bail Grid Array).
• the terminals are solder balls arranged on a flat face of the housing according to a grid. Their number can be more than five hundred and the grid can have a side of 3 cm.
• some components can also be interconnection modules for integrated circuits. These modules are plates similar to the previous boxes, the surface of which can be much larger and have a very large number of terminals. The terminals of these boxes and modules are fixed to the card by soldering on corresponding conductive pads.
• the cards must therefore have a very dense number of plots.
• a current card of the order of 250 mm x 250 mm can receive up to components having more than 1600 terminals.
• the card therefore has connection zones provided with studs corresponding to the terminals of the boxes and modules described above. In these areas, the pads are therefore arranged in a regular manner according to a corresponding grid.
• Each of these zones must also have a large number of connections between the studs of the zone and the other studs.
• the connections include connection wires all inside the card and extending along the conductive planes of the card, as well as conductive connection holes. Each hole passes through corresponding conductive pads having a diameter slightly larger than that of the holes and placed at each conductive level through which the hole passes.
• the blind holes being made in an outer insulating layer of the card, their diameter can be small, of the order of 0.2 mm.
• the holes through the card have a diameter depending on the thickness of the card. For a number of the order of 15 to 20 layers their diameter is of the order of 0.3 mm.
• each pad is a patch of the order of 0.5 mm in diameter, placed next to the patch of a hole and connected to the patch by a very short wire.
• connection between two studs arranged in the central parts of two zones provided for the connection of two integrated circuit boxes requires the passage of wires between the holes.
• each wire must pass a minimum distance from another wire or the patch of a hole to ensure sufficient electrical insulation between neighboring conductors.
• the minimum distance is currently of the order of 85 to 135 ⁇ m and the width of a wire is of the order of 50 to 100 ⁇ m depending on its function.
• the connection pads are staggered so that a group of five neighboring pads is made of four pads placed in the corners of a square and a fifth pad in the center.
• the distance between axes of the studs is of the order of 1 mm to satisfy the density desired for the connection of an integrated circuit box.
• the corresponding holes are through holes, no wire can pass between these five holes over the entire thickness of the card.
• the solution usually employed is therefore to mix the blind holes and the through holes.
• a reliability constraint requires a maximum thickness of the card, for example 2.4 mm.
• Another constraint requires a maximum ratio between the thickness of the card and the diameter of the holes, for example a maximum ratio of
• An object of the present invention is to optimize the number of layers of a printed circuit board provided with very high density connection pads, in order to be able to manufacture the card under industrial conditions.
• Another object of the present invention is to allow this optimization without adding additional costs to the manufacture of the card.
• the subject of the invention is a printed circuit board having at least one zone provided with holes which are substantially regularly arranged and attached to wires passing through at least part of the zone boundary for connection outside the zone, characterized in that the majority of the neighboring holes of said zone boundary part, and preferably all, are blind holes.
• FIG. 1 is a sectional view of part of a printed circuit board according to the invention.
• FIG. 1 is a partial top view of an outer conductive face of the card shown in Figure 1.
• the printed circuit board 10 is made of a stack of conductive 11 and insulating layers 12, 13.
• the insulating layers 12 a distinction is made between the laminates 12a represented by the hatched layers and the prepregs 12b represented by the layers covered with dots.
• the two exterior laminates are referenced at 13 and in the illustrated example have blind holes 14.
• the insulating layers 12 exist in two thicknesses, 100 ⁇ m and 200 ⁇ m
• the exterior laminates 13 have a thickness of l 'order of 100 microns
• the conductive layers 11, usually copper have a thickness of the order of 15 to 35 microns.
• the holes 14, 14 'are metallized and the conductive layers 1 1 are formed uniformly on the two sides of each laminate and etched.
• the card also incorporates through holes 15.
• the holes 14, 14 'and 15 are provided with pads 16 at the conductive layers 1 1 inside the card.
• Plugs 17 are provided in the outer conductive layers 11 to serve for connection to a component external to the card and not shown, such as an integrated circuit box of the BGA type.
• the pads 17 illustrated are similar to the pads 16 and are arranged on both sides of the card.
• the interior conductive layers comprise connecting wires 18 which can be attached to pads 16 or which can pass between neighboring pads 16.
• the internal conductive layers are staged according to successive levels or stages SI, S2, ... starting from the outermost level. It will be considered that the face used in the example described is the upper face.
• the levels of a card are usually assigned to one of the two functions that a wire in the card can have, either to be used for the power supply of the components, or to be used for the routing of logic signals . In the example illustrated, we will only consider the logic levels, since the power levels are conductive planes crossed by holes directly bringing the energy to the power pads. We will assume that the logical levels are the odd order levels.
• FIG. 2 illustrates a partial top view of a face of the card shown in FIG. 1. More specifically, FIG. 2 illustrates the holes 14 and 15 of the card 10 and, by supposed transparency of the insulating layers and of the levels d 'power supply, the logic wires 18 attached thereto.
• the blind holes 14 are shown in the form of gray circles.
• the wires 18 which leave from these holes are at the level SI.
• the other holes are represented according to the logical level from which a wire attached to this hole leaves.
• the rectangles are representative of the holes from which wires of level S3 leave
• the triangles are representative of the holes from which wires of level S5 leave
• the crossed circles are representative of the holes from which wires of level S7 depart
• the inverted A's are representative of the holes from which S9 level son.
• five logical levels are occupied.
• the crosses represent holes used for energy distribution. Since the illustrated card can be equipped with components on its two faces, the other face is also provided in the same way in logical levels, the last level being able to be common. In the example carried out under the conditions described, the card had ten logic levels and eight power levels.
• the holes illustrated are regularly arranged according to a matrix grid in an area 19 intended to receive a component such as a BGA box.
• the illustrated grid has sixteen columns referenced A-P and fifteen rows referenced 1-15.
• the holes are lmm.
• the wires 18 extend along lines parallel to the columns and rows of the grid to be brought out of the area to at least one external stud or an input-output terminal of the card.
• the row corresponding to the row or column is referenced a.
• two parallel intermediate lines referenced b and c are available for the passage of the wires between the holes, line c being the furthest from line a.
• the zone 19 is delimited by a peripheral line 20, represented by a broken line, slightly outside the peripheral holes.
• the illustrated area being substantially square, its four sides are designated successively by 20a, 20b, 20C and 20d.
• the area 19 illustrated as an example is placed in a corner of the card, so that two of its adjacent sides 20c and 20d correspond substantially to the sides of the card.
• the lines a, b and c intended to make the connection of the holes towards the outside of the zone 19 therefore cut only the sides 20a and 20b, as appears from FIG. 2.
• the logical holes adjacent to the sides 20a and 20b are preferably all blind holes 14 represented in the form of shaded circles.
• One of the advantages of a blind hole is that it does not obstruct the passage of wires below the hole.
• the blind holes follow one another in a row or a column. In the zone 19 illustrated, they follow one another on three rows and columns adjacent to the sides 20a and 20b, as well as in part on the fourth rows and columns.
• the coordinate holes N2, 02 and P2 have three respective wires extending along the three respective lines 2a, le and lb.
• the coordinate holes Ml, M2 and M3 have three respective wires extending along the respective lines Ma, Mb and Me.
• the through hole K4 has a level wire S3 extending along the line Ka and therefore passes under the three blind holes Kl, K2 and K3, as well as under the first level wire connected to the blind hole Kl.
• This configuration is also found for example for the blind holes E1-E3 and the through hole E4 with wire of lower level S3, as for the blind holes N8, 08 and P8 and the hole M8.
• the number of blind holes may be higher depending on a row or a column.
• the four blind holes C1-C4 have four respective wires extending along the lines Ca, Cb, Ce and Bc, and the through hole C5 has a lower level wire S3 extending along the line Ca and passing under the four blind holes and under the first level wire attached to the blind hole Cl.
• the five blind holes L4, M4, N4, 04 and P4 the last three are connected to three respective wires extending along the three Respective lines 4a, 3c, 3b, the blind hole M4 is connected to a wire extending first along line 4a, then successively following lines Me, 2c, Na and 2b, and blind hole L4 is attached to a wire extending first along line 4a, then along line Le.
• the lower level wire S3 attached to the hole K5 extends first along line 5a, then along line Kb and finally along line 4a where it passes under the five blind holes L4-P4 and under the upper level wire attached to blind hole P4.
• the wire was of lower level. More generally, successive blind holes may not be in a straight line, but form a broken line leaving a passage for a lower level wire.
• the arrangement of blind holes therefore makes it possible to add possible Hgnes for the passage of wires through the area. It also appears from FIG. 2 that in the zone 19 illustrated, the lower the wires, the further the holes to which they are attached are from the sides 20a and 20b. In zone 19, the level wires S3 are attached to holes arranged partially on row 4, then uniformly on the two rows 5 and 6 and partly on row 7. They are also partly arranged on column M, uniformly on the three columns J, K and L. The lower level wires S5,
• S7 and S9 are attached to holes successively further from the sides 20a and 20b, the three level holes S9 being arranged in the corner opposite the corner formed by the sides 20a and 20b.
• This arrangement makes it possible to better manage the layout of the wires and to optimize their density.
• eighteen layers were sufficient to form the card 10 which satisfies the desired high density, while it was more than double using the prior art.
• the invention relates to a printed circuit board 10 having at least one zone 19 provided with holes 14, 15 substantially regularly arranged and attached to wires 18 passing through at least one part 20a , 20b of the boundary 20 of the area 19 for an external connection to the area, said holes adjacent to said portion of the boundary of the area being mostly, and preferably all, blind holes 14.
• This configuration makes it possible to optimize the density of holes and wires.
• the logic and supply holes are in the area 19 illustrated regularly arranged in a uniform grid, while the logic holes here concerned by the invention are not regularly arranged.
• the holes of at least row 1 and / or the column P adjacent to the boundary part 20a, 20b are in majority, and preferably all, blind holes 14
• the blind holes (C1-C4; L4, M4, N4, 04, P4) follow one another to leave under them a passage for at least one wire of lower level.
• the wires attached to the through holes are substantially hierarchical as a function of the distance of the holes from said part of H ite from the zone. In the example illustrated, the majority of the through holes are all the more distant from said limit portion (20a, 20b) from the area (19) as their wires have a low level (S3-S9).

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)

Applications Claiming Priority (3)

Publications (1)

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ID=9529492

Family Applications (1)

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Family Cites Families (2)

• 1998
  • 1998-08-06 FR FR9810151A patent/FR2782230B1/fr not_active Expired - Fee Related
• 1999
  • 1999-08-05 EP EP99936698A patent/EP1103169A1/de not_active Ceased
  • 1999-08-05 WO PCT/FR1999/001943 patent/WO2000008900A1/fr not_active Application Discontinuation

Non-Patent Citations (1)

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