FR2782230B1 - Carte de circuits imprimes - Google Patents
Carte de circuits imprimesInfo
- Publication number
- FR2782230B1 FR2782230B1 FR9810151A FR9810151A FR2782230B1 FR 2782230 B1 FR2782230 B1 FR 2782230B1 FR 9810151 A FR9810151 A FR 9810151A FR 9810151 A FR9810151 A FR 9810151A FR 2782230 B1 FR2782230 B1 FR 2782230B1
- Authority
- FR
- France
- Prior art keywords
- printed circuits
- circuits card
- card
- printed
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9810151A FR2782230B1 (fr) | 1998-08-06 | 1998-08-06 | Carte de circuits imprimes |
EP99936698A EP1103169A1 (fr) | 1998-08-06 | 1999-08-05 | Carte de circuits imprimes |
PCT/FR1999/001943 WO2000008900A1 (fr) | 1998-08-06 | 1999-08-05 | Carte de circuits imprimes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9810151A FR2782230B1 (fr) | 1998-08-06 | 1998-08-06 | Carte de circuits imprimes |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2782230A1 FR2782230A1 (fr) | 2000-02-11 |
FR2782230B1 true FR2782230B1 (fr) | 2000-09-08 |
Family
ID=9529492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9810151A Expired - Fee Related FR2782230B1 (fr) | 1998-08-06 | 1998-08-06 | Carte de circuits imprimes |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1103169A1 (fr) |
FR (1) | FR2782230B1 (fr) |
WO (1) | WO2000008900A1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7069646B2 (en) | 2000-06-19 | 2006-07-04 | Nortel Networks Limited | Techniques for reducing the number of layers in a multilayer signal routing device |
US7281326B1 (en) | 2000-06-19 | 2007-10-16 | Nortel Network Limited | Technique for routing conductive traces between a plurality of electronic components of a multilayer signal routing device |
US7256354B2 (en) | 2000-06-19 | 2007-08-14 | Wyrzykowska Aneta O | Technique for reducing the number of layers in a multilayer circuit board |
US7069650B2 (en) * | 2000-06-19 | 2006-07-04 | Nortel Networks Limited | Method for reducing the number of layers in a multilayer signal routing device |
US7259336B2 (en) | 2000-06-19 | 2007-08-21 | Nortel Networks Limited | Technique for improving power and ground flooding |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5784262A (en) * | 1995-11-06 | 1998-07-21 | Symbios, Inc. | Arrangement of pads and through-holes for semiconductor packages |
JP3050807B2 (ja) * | 1996-06-19 | 2000-06-12 | イビデン株式会社 | 多層プリント配線板 |
-
1998
- 1998-08-06 FR FR9810151A patent/FR2782230B1/fr not_active Expired - Fee Related
-
1999
- 1999-08-05 EP EP99936698A patent/EP1103169A1/fr not_active Ceased
- 1999-08-05 WO PCT/FR1999/001943 patent/WO2000008900A1/fr not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
EP1103169A1 (fr) | 2001-05-30 |
FR2782230A1 (fr) | 2000-02-11 |
WO2000008900A1 (fr) | 2000-02-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |