EP1095456A1 - Diviseur de frequence statique avec rapport de division modifiable - Google Patents

Diviseur de frequence statique avec rapport de division modifiable

Info

Publication number
EP1095456A1
EP1095456A1 EP99938174A EP99938174A EP1095456A1 EP 1095456 A1 EP1095456 A1 EP 1095456A1 EP 99938174 A EP99938174 A EP 99938174A EP 99938174 A EP99938174 A EP 99938174A EP 1095456 A1 EP1095456 A1 EP 1095456A1
Authority
EP
European Patent Office
Prior art keywords
divider
static frequency
flip
input
frequency divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99938174A
Other languages
German (de)
English (en)
Inventor
Michael Pierschel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1095456A1 publication Critical patent/EP1095456A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle

Definitions

  • the invention relates to a static frequency divider which contains at least two synchronously clocked holding elements or two flip-flop circuits, which alternately switch on and off.
  • the holding elements usually have a preparatory stage and a stage that holds the signal (master and slave).
  • the individual stages are usually designed as differential stages, since, due to the parasitic capacitances, relatively low signal levels occur at high and very high frequencies, and due to the differential stages there is a significantly greater interference immunity.
  • the working point current is between the preparatory one
  • Stage (master) and the stage holding the signal (slave) are switched, with a pair of transistors of each stage always carrying the usually constant operating point current and thus the operating point current of the holding elements is uniform during both clock phases. At least two such holding elements or D flip-flops are required for a static frequency divider.
  • the operating point current must be large enough to generate a corresponding signal voltage swing on the load elements and to reload the parasitic capacitances which are always present and are connected to ground with the required signal voltage swing.
  • a 2: 1 frequency divider can be interconnected in a manner known per se from two such holding elements in the form of a master-slave flip-flop, the clock control being designed such that either the master holding element or the slave holding element is activated and the outputs of the master holding element are connected to the inputs of the slave holding element.
  • a U-switching flip-flop or a so-called T-flip-flop is produced by feedback of the outputs of the master-slave flip-flop in phase opposition to the inputs of the master-slave flip-flop.
  • a binary static frequency divider with a divider ratio greater than 2: 1, for example, has a series connection of several ter flip-flops.
  • the object on which the invention is based is to provide a static frequency divider with switchable divider ratios, in which no additional level drivers or logic circuits with a correspondingly high power loss are required.
  • FIG. 1 shows a block diagram of a 2: 1/3: 1 divider according to the invention
  • Figure 2 is a circuit diagram of the modified master-slave flip-flops of Figures 1 and
  • FIGS. 1 and 2 shows a timing diagram to explain the mode of operation of the circuits shown in FIGS. 1 and 2.
  • modified D-flip-flops are present through additional input transistor pairs and switching transistors and a switchover takes place between two, so to speak, interlocking divider rings, the two part sets only being exchanged by a direct and a crosswise connection between the respective ones Distinguish the outputs of a first D flip-flop with the inputs of the second D flip-flop.
  • This switchover between the two divider rings suppresses an input clock period or extends the output clock period. Since the switchover time is typically much shorter than the period of the input clock with which both holding elements are clocked synchronously, the switchover from one divider ring to the other suppresses exactly one period of the input clock.
  • the static frequency divider Since the additional transistors in the modified master-slave flip-flop require the same operating currents, the static frequency divider, despite a switchable divider ratio, requires the same power loss as a static frequency divider with a correspondingly large fixed divider ratio.
  • a critical path does not exist, since no logic in the speed-determining divider ring can lead to time delays.
  • Such a circuit according to the invention can in principle be operated up to the highest frequencies that can be achieved with the respective technology. To do this, however, the individual edges on the control inputs must be as steep as possible in order to achieve the very short changeover time required for the operating current.
  • a second part is realized in that the output Q of the flip-flop 1 with the inverting input D2N and the output QN of the flip-flop are connected via a signal crossing X3 1 is connected to the regular input D2 of the flip-flop 2 and that the output Q of the flip-flop 2 via the signal crossings XI and X2 provided here with the input D2 of the flip-flop 1 and the output QN2 of the flip-flop 2 also are directly connected to input D2N via signal crossings XI and X2.
  • a direct connection means that a non-inverted output is connected to a corresponding non-inverted input and an inverted output is connected to a corresponding inverted input.
  • a crosswise connection here means that a non-inverted output is connected to an inverted input and an inverted output is connected to a corresponding non-inverted input.
  • both flip-flops 1 and 2 are switched on at their clock outputs CLK and CLKN
  • the flip-flops 1 and 2 each have a regular and an inverted control input ST and STN, which are each connected to a control unit 3.
  • the control unit 3 generates changeover signals for the inputs ST and STN depending on a selection signal M for the divider ratio, as a result of which the inputs are selected for a respective divider ring.
  • M for the divider ratio
  • the control unit 3 can be supplied with the input clock T and also output signals E and F from these further stages.
  • FIG 2 a detailed circuit diagram for the modified D flip-flops 1 and 2 is shown, the modification consisting primarily in that in addition to a first pair of input transistors T3 and T4, a second pair of input transistors T9 and T10 is provided, with a common connection of the Transistors T3 and T4 can be connected to a node Kl via a switching transistor T7, the gate of which is connected to the input ST, and first connections of the transistors T9 and T10 can be connected via a further switching transistor T8, the gate of which is connected to the input STN, are also connectable to the node Kl.
  • the gate of transistor T3 is connected to the first inverting input DIN, the gate of transistor T4 to input D1, the gate of transistor T9 to input D2N and the gate of transistor T10 to input D2.
  • the second connections of the transistors T3 and T9 are with the output Q and the second connections of the transistors T4 and T10 with the inverted one
  • a transistor T5 is connected with a first connection to a node K2 and with a second connection via a load resistor RL1 to VDD.
  • a transistor T6, which forms a pair of transistors with transistor T5 is connected at a first connection to node K2 and via a load resistor RL2 to VDD.
  • the connection point between the transistor T5 and the resistor RL1 represents the output Q, which is fed back to the gate of the transistor T6.
  • the connection point between the transistor T6 and the load resistor RL2 represents the inverting output QN, which is fed back to the gate of the transistor T5. Coupled crosswise by the two Transistors T5 and T6 result in a bistable multivibrator.
  • the node K1 can be connected via a switching transistor T1 and the node K2 can be connected via a switching transistor T1 via a common resistor R1 with reference potential GND, the gate of the transistor T1 being connected to the regular clock input CLK and the gate of the transistor T2 being connected to the inverted clock input CLKN is.
  • FIG. 3 shows the signals T, A ... D in the upper part of this figure for the case without a signal change at the control inputs ST and STN and in the lower part of the figure for the case of a signal change at the control inputs ST and STN .
  • Drawn arrows show the takeover of signals C and D as signals A and B and the dotted characters show the takeover of signals A and B as signals C and D.
  • P2 (n + m) * P0
  • n : l / (n + m): 1-frequency divider arises.
  • k switches or m switches take place during n periods PO, k of course not equal to m. In a corresponding manner, this leads to an (n + k): l / (n + m): 1 frequency divider.

Landscapes

  • Electronic Switches (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un diviseur de fréquence statique avec rapport de division modifiable, pour les fréquences les plus élevées et pour une absorption de puissance totale minimale. A cet effet, un premier étage de diviseur comporte une bascule T pourvue de bascules D qui présentent une paire de transistors d'entrée supplémentaire. Si à un moment quelconque se produit une commutation du courant de service de la paire de transistors d'entrée, exactement une période d'horloge d'entrée est atténuée et le rapport de division modifié. Grâce à d'autres bascules de diviseur et à d'autres processus de commutation, on obtient des rapports de division pouvant être modifiés pratiquement à volonté.
EP99938174A 1998-06-29 1999-06-11 Diviseur de frequence statique avec rapport de division modifiable Withdrawn EP1095456A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19828925 1998-06-29
DE19828925 1998-06-29
PCT/DE1999/001714 WO2000001071A1 (fr) 1998-06-29 1999-06-11 Diviseur de frequence statique avec rapport de division modifiable

Publications (1)

Publication Number Publication Date
EP1095456A1 true EP1095456A1 (fr) 2001-05-02

Family

ID=7872357

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99938174A Withdrawn EP1095456A1 (fr) 1998-06-29 1999-06-11 Diviseur de frequence statique avec rapport de division modifiable

Country Status (3)

Country Link
EP (1) EP1095456A1 (fr)
JP (1) JP2002519923A (fr)
WO (1) WO2000001071A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10013633A1 (de) 2000-03-18 2001-09-20 Inst Halbleiterphysik Gmbh Statischer Frequenzteiler mit umschaltbarem Teilerverhältnis
US6760397B2 (en) 2001-11-16 2004-07-06 Koninklijke Philips Electronics N.V. High-speed programmable frequency-divider with synchronous reload

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244931A (ja) * 1987-03-30 1988-10-12 Nec Corp 分周器
JP3349170B2 (ja) * 1992-06-15 2002-11-20 日本電信電話株式会社 Ｃｍｏｓ可変分周回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0001071A1 *

Also Published As

Publication number Publication date
WO2000001071A1 (fr) 2000-01-06
JP2002519923A (ja) 2002-07-02

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