EP1062700A1 - Power semiconductor structural part with a mesa edge - Google Patents

Power semiconductor structural part with a mesa edge

Info

Publication number
EP1062700A1
EP1062700A1 EP00903516A EP00903516A EP1062700A1 EP 1062700 A1 EP1062700 A1 EP 1062700A1 EP 00903516 A EP00903516 A EP 00903516A EP 00903516 A EP00903516 A EP 00903516A EP 1062700 A1 EP1062700 A1 EP 1062700A1
Authority
EP
European Patent Office
Prior art keywords
zone
power semiconductor
field stop
semiconductor component
component according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00903516A
Other languages
German (de)
French (fr)
Inventor
Reiner Barthelmess
Gerhard Schmidt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
EUPEC GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EUPEC GmbH filed Critical EUPEC GmbH
Publication of EP1062700A1 publication Critical patent/EP1062700A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the invention relates to an asymmetrically blocking power semiconductor component with a mesa edge termination.
  • the present invention relates in particular to asymmetrically blocking (ie blocking on one side), high-voltage-resistant power semiconductor components with so-called mesa edge termination, ie. H. with a bevel on the side walls.
  • the invention relates in particular to such power semiconductor components with so-called punch-through dimensioning, i. H. with a field stop zone to reduce the electrical field.
  • Such power semiconductor components can be designed, for example, as pin diodes, GTOs, IGBTs or the like.
  • the emitter zone In order to achieve the highest possible emitter efficiency, the emitter zone must be doped as high as possible. At the same time, however, it is necessary for the space charge zone to run over the longest possible distance on the surface of the window in blocking operation. For the purpose of enlarging the path available for the space charge zone on the wafer surface, the lateral edge of the semiconductor body typically has a positive bevel.
  • a common method for building up additional charges in the edge region or for reducing the field peaks mentioned is the use of electroactive passivation layers made of typically amorphous, hydrogen-containing carbon layers or of amorphous, hydrogen-containing silicon carbide layers.
  • EP 0 400 178 B1 describes a method for electroactive passivation. The advantage of this method is that charges can be actively built up in the amorphous layer mentioned there, which to a certain extent can weaken field strength peaks in a self-adjusting manner.
  • Ins pecial b takes the charge density of surface charges with temperature, so that a sufficient blocking ability can not be ensured, in particular at very low temperatures.
  • field stop zones of the same conductivity type as in the inner zone are provided in the edge area below the areas (etched shoulders) etched out of the semiconductor body.
  • These field stop zones which are typically connected to the inner zone and to the emitter zone, adjoin the polished, damageless surface of the etched-out shoulders.
  • the doping concentration of these field stop zones, which lies between that of the emitter zone and that of the inner zone, is set in such a way that there is a decreasing gradient in the concentration profile of the doping from the surface of the etching shoulders into the depth of the semiconductor body. In this way it can be ensured, even under extreme conditions, that the semiconductor component does not accidentally break down before the predetermined volume breakdown voltage is reached.
  • the course of the doping concentration is set in the edge region in such a way that the breakdown charge results after etching off a minimum thickness which is required to produce a polish-etched, damagefree surface.
  • One is almost independent of the depth or the thickness of the emitter zone.
  • the doping concentration in the field stop zone The depth of the charge carrier measured from the field stop zone and the inner zone below it is approximately equal to the breakthrough charge density, based on the vertical direction.
  • the doping concentration or the amount of charge carriers introduced in the field stop zone can be specifically set or controlled by ion implantation.
  • the etched-out areas on the pane surface do not run ideally horizontally, but fall outward at a flat angle of a few degrees. In this case, a gradient in the doping concentration falling towards the edge can also be generated.
  • the concentration profile of the field stop zone has a flat gradient in the lateral direction towards the edge of the power semiconductor component.
  • corresponding calculations must also be made for the laterally averaged surface charge densities.
  • the invention is particularly suitable for power diodes (pin diodes) with a mesa edge termination, which are used, for example, as free-wheeling diodes of IGBTs and GTOs.
  • the invention is also very advantageous with other, asymmetrical Trically blocking power semiconductor components with mesa edge termination, such as IGBTs, GTOs and the like, applicable.
  • FIG. 1 shows schematically in a partial section a first exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode;
  • FIG. 2 shows schematically in a partial section a second exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode;
  • FIG. 3 schematically, in a partial section, an exemplary embodiment of a power semiconductor component according to the invention designed as a GTO;
  • FIG. 4 schematically, in a partial section, an exemplary embodiment of a power semiconductor component according to the invention designed as an IGBT.
  • FIG. 1 shows schematically in a partial section a first exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode.
  • 1 denotes the semiconductor body of the pin diode.
  • the pin diode has an anode connection A and a cathode connection K, which are arranged on opposite sides of the semiconductor body 1.
  • the semiconductor body 1 which consists for example of silicon substrate, has an inner zone 2 which is weakly n-doped in the present exemplary embodiment.
  • a p-doped anode zone 3 adjoins the inner zone 2 over a large area on the anode side.
  • the anode zone 3 adjoins the anode zone 3 on the rear surface 5 of the semiconductor body 1.
  • the anode zone 3 is here connected to the anode connection A via a large-area anode metallization or anode electrode 6 applied to the surface 5.
  • cathode zone 8 On the cathode side, at least one, in the present case heavily n-doped, cathode zone 8 is embedded in the front surface 7 of the semiconductor body 1.
  • the cathode zone 8 has the same conductivity type, but a much higher doping concentration than the inner zone 2 and thus serves as a field stop zone for the field breakdown of the electric field on the front surface 7.
  • the cathode zone 8 is embedded in the inner zone 2 at this location and trough-shaped may have been introduced into the semiconductor body 1, for example, by ion implantation with an optionally subsequent temperature step or by diffusion.
  • the cathode zone 8 is connected to the cathode connection K on the surface 7 via a cathode metallization or a cathode electrode 9.
  • the region of the pin diode, which is defined by the cathode zone 8, is also referred to as the active region AB of the pin diode.
  • the edge region RB defines essentially the regions of the semiconductor body 1 located outside the active region AB is provided, the area 10 etched out of the semiconductor body 1.
  • an etching shoulder 13 is defined between the cathode zone 8 and the edge area RB.
  • these etching shoulders 12 or the surfaces 7 ′ that are produced as a result of polishing run essentially horizontally. It would of course also be conceivable that these etching shoulders 12 take a slightly inclined course towards the edge.
  • An n-doped field stop zone 11 is provided in the areas below the etching shoulders 12.
  • This field stop zone 11 here has the same conductivity type as the inner zone 2 and the cathode zone 8.
  • the field stop zone 11 is connected to the cathode zone 8 and is arranged between the polished-etched surfaces 7 ′ and the inner zone 2. It is particularly advantageous if the doping concentration of the field stop zone 11 is lower than that of the cathode zone 8 and higher than that of the inner zone 2. In this way it can be ensured that a flatter gradient of the doping concentration of in the edge region RB of the pin diode the surface 7 ! to the inner zone.
  • the field stop zone 11 has a homogeneous n-doping. In a further development, it would also be very advantageous if the field stop zone 11 has a slowly decreasing doping concentration towards the edge.
  • the pin diode in FIG. 1 is constructed in a so-called mesa structure.
  • mesa structures have a typically positive beveling of the side walls 13 of the semiconductor body 1.
  • this taper angle of the side wall 13 is designated by ⁇ .
  • Typical values of the bevel angle ⁇ for a brass structure are between 20 and 45 °.
  • the field stop zones 11 are only provided in the edge region RB of the semiconductor component. It would of course also be conceivable if the field stop zone 11 is arranged as a continuous layer over the entire width of the semiconductor body 1. This case is shown in the exemplary embodiment in FIG. 2.
  • the field stop zone 11 is arranged both in the edge region RB and in the active region AB of the pin diode. In particular in the active region AB of the pin diode, the field stop zone 11 thus spaces the cathode zone 8 and the inner zone 2 from one another.
  • the field stop zone 11 can advantageously be introduced into the semiconductor body 1 by means of the cathode electrode 9, which acts as a mask, after the areas 10 have been etched off.
  • a field stop zone 11 is provided, which has been introduced over a large area into the semiconductor body 1.
  • the cathode zone 8 is then applied over a large area to the field stop zone 11, for example by means of a deposition process.
  • the corresponding regions 10 are etched out of the semiconductor body 1.
  • electroactive passivation layers for example made of an amorphous carbon compound, can be applied to the surfaces 7 '.
  • the function of the field stop zone 11 according to the invention in the case of the pin diode according to FIG. 3 or 4 is described in more detail below:
  • measures for reducing the electric field at the surface 7, 7 ⁇ must be taken.
  • the space charge zone hits a field stop zone in blocking operation.
  • this field stop zone is typically formed by the emitter zone 8.
  • the space charge zone is captured by this field stop zone designed as an emitter zone 8.
  • the electric field rises in this emitter zone 8 and a trapezoidal field profile of the electric field is created in the volume of the semiconductor body 1. Due to this trapezoidal field profile, the electric field is reduced towards the surface 7 of the semiconductor body 1.
  • the field profile is no longer trapezoidal due to the lack of emitter zone 8 there and thus the required field stop zone; Rather, the division of the electric field sometimes leads to extreme field peaks on the etching shoulders 12.
  • the field stop zones 11 are introduced into the semiconductor body 1 in the areas below the etching shoulders 12. It is important to ensure that these field stop zones 11 are not interrupted, i.e. they must be connected directly to the emitter zone 8, which is also designed as a field stop zone, and to the inner zone 2. In this way it is ensured that a trapezoidal field profile is generated across the entire width of the semiconductor body 1 from the pn junction to the surface 7, 7 and thus field peaks in the edge region RB are avoided.
  • the present invention is not limited exclusively to power semiconductor components designed as pin diodes, but can also be very advantageous with other cables. semiconductor devices are used. Figures 3 and 4 show two further advantageous embodiments.
  • FIG. 3 schematically shows a partial section of an exemplary embodiment of a power semiconductor component designed as a GTO with an edge termination according to the invention.
  • the GTO gate turn-off thyristor
  • the GTO which is designed here as an asymmetrically blocking thyristor, has an anode connection A and a cathode connection K on opposite sides of the semiconductor body 1.
  • the semiconductor body 1 consists of an n-doped n-base zone 20.
  • a p-doped p-base zone 22 connects to the n-base zone 20 via a large-area pn junction 21.
  • a heavily n-doped n-emitter zone 23 is connected to the p-base zone 22.
  • the n-emitter zone 23 is connected to the cathode terminal K via a cathode metallization or cathode electrode 24 on the rear surface 25.
  • a p-doped p-emitter zone 26 is embedded in the front surface 27 of the semiconductor body 1 in the active region AB of the thyristor on the anode side.
  • the p-emitter zone 26 is connected to the anode connection A via a large-area anode metallization or anode electrode 28. Furthermore, in FIG. 3 the p-emitter zone 26 is over a buffer layer
  • the p-emitter zone 26 and thus the anode electrode 28 can be connected to the n-base zone 20 via at least one via 30.
  • This buffer zone 29 in the region of the semiconductor component on the anode side thus serves as a field stop zone in blocking operation. In principle, a continuous emitter without anode short circuits is also conceivable.
  • the thyristor has a so-called transparent emitter, i.e. an anode side
  • Buffer layer 29 with anode short circuits 30 With such transparent emitters, the p-emitter zones 26 are after the Ion implantation did not heal completely to ensure a low charge carrier injection. These measures are carried out with generic thyristors or GTOs in order to be able to switch them on and off in a defined manner. Instead of such a transparent emitter, it would alternatively also be conceivable to irradiate the areas below the anode-side p-emitter zone 26 with helium in order to thereby generate a recombination sink.
  • Areas 31 etched out of the semiconductor body 1 are provided in the edge area RB, ie outside the active area AB of the thyristor, equivalent to the diode structures of FIGS. 1 and 2. These are arranged under the polished-etched surfaces 27 x of the etching shoulders 33 resulting from the etched-out regions 31.
  • the field stop zones 32 are here connected to the p-emitter zone 26.
  • the field stop zones 32 are n-doped and have a higher doping concentration than the n-base zone 20.
  • the thyristor is shown as an asymmetrical thyristor with a field stop zone or buffer layer 29. So that the anode-side gain ⁇ pn p does not disappear, the amount of charge in the field stop zone 29 must not be greater than the breakthrough charge in the case of structures short-circuited on the anode.
  • the mode of operation of this field stop zone 32 according to the invention in the edge region of the semiconductor component is equivalent to the mode of operation of the field stop zone 11 of the pin diodes according to FIGS. 1 and 2.
  • the doped can be any doped
  • Field stop zones 32 in a thyristor or GTO, equivalent to a pin diode, ensure complete volume blocking capability also in the edge region RB of the semiconductor component.
  • the exemplary embodiment of a thyristor shown in FIG. 3 shows only one possible advantageous embodiment.
  • the edge structure according to the invention can of course also be used very advantageously with all other vertically designed thyristors with edge termination, in particular GTOs and monolithically integrated systems such as, for example, reverse-conducting thyristors.
  • FIG. 4 schematically shows in a partial section an exemplary embodiment of a power semiconductor component according to the invention designed as an IGBT, in which the edge structure according to the invention is also used.
  • the IGBT in Figure 4 is constructed in a known manner. Since the four-layer structure of the IGBT (insulated gate bipolar transistor) shown in FIG. 4 is constructed similarly to the four-layer structure of the thyristor shown in FIG. 3, only the features that differ from the thyristor in FIG. 3 are discussed in more detail below.
  • the heavily n-doped n-emitter zones 23 are embedded in the shape of a trough in these p-base zones 22.
  • the p-base zone 22 and the n-emitter zones 23 are connected to one another on the surface 25 in a known manner via a cathode electrode 35 designed as a shunt.
  • a MOS structure is provided here.
  • the MOS structure comprises a gate electrode 36 and a gate oxide 37, which are each arranged over the regions of the n-base zone 20, p-base zone 21 and n-emitter zone 22 which come to the surface 25.
  • the p-emitter zone 26 arranged on the surface 27 is designed as a collector in the IGBT.
  • the IGBT in FIG. 4 has no plated-through holes 30 between p-collector zone 26 and n-base zone 20.
  • the buffer zone 29 serves as a field stop zone for the reduction of the electric field on the surface of the pane, equivalent to the thyristor in FIG.
  • the function of the field stop zone 32 according to the invention is here equivalent to the aforementioned examples of a pin diode according to FIGS. 1 or 2 or of the GTO according to FIG. 3.
  • the edge regions RB thereof are formed in a mesa structure.
  • the present invention is also very advantageously applicable to power semiconductor components with edge closures of whatever type.
  • FIGS. 1 to 4 how possible other exemplary embodiments of the semiconductor components according to the invention can look; these are generally any asymmetrically blocking semiconductor components, such as diodes, thyristors, transistors, IGBTs and the like.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

The invention relates to an asymmetrically-locking power semiconductor structural part. Field stop zones of the same conducting type as in the inner zone are provided in the border area underneath the areas which are etched out (etching shoulders) from the semiconductor body. Said field stop zones are typically connected to the inner zone and to the emitter zone and are adjacent the polish-etched, damage-free surface of the etched-out etching shoulders. The doping concentration of said field stop zones is adjusted in such a way that a decreasing gradient results in the concentration gradient of the doping. Said decreasing gradient extends from the surface of the etching shoulders to the depth of the semiconductor body. According to the invention, the volume breakdown voltage can be secured under extreme conditions even in the bordering area of the power semiconductor structural part. The present invention is especially useful for power semiconductor structural parts which are embodied in a mesa structure, especially in pin diodes, asymmetric thyristors as for example GTOs, IGBTs and the like.

Description

Beschreibungdescription
Leistungshalbleiterbauelement mit Mesa-RandabschlußPower semiconductor component with mesa edge termination
Die Erfindung betrifft ein asymmetrisch sperrendes Leistungshalbleiterbauelement mit einem Mesa-Randabschluß.The invention relates to an asymmetrically blocking power semiconductor component with a mesa edge termination.
Die vorliegende Erfindung bezieht sich insbesondere auf asymmetrisch sperrende (also einseitig sperrende) , hochspannungs- feste Leistungshalbleiterbauelemente mit sogenanntem Mesa- Randabschluß, d. h. mit einer Anschrägung der seitlichen Wände. Die Erfindung bezieht sich insbesondere auch auf solche Leistungshalbleiterbauelemente mit sogenannter Punch-Through- Dimensionierung, d. h. mit einer Feldstopzone zum Abbau des elektrischen Feldes. Derartige Leistungshalbleiterbauelemente können beispielsweise als pin-Dioden, GTOs, IGBTs oder dergleichen ausgebildet sein.The present invention relates in particular to asymmetrically blocking (ie blocking on one side), high-voltage-resistant power semiconductor components with so-called mesa edge termination, ie. H. with a bevel on the side walls. The invention relates in particular to such power semiconductor components with so-called punch-through dimensioning, i. H. with a field stop zone to reduce the electrical field. Such power semiconductor components can be designed, for example, as pin diodes, GTOs, IGBTs or the like.
Ein wesentliches Kriterium für die Qualität bei solchen Lei- stungshalbleiterbauelementen ist deren Emitterwirkungsgrad.An important criterion for the quality of such power semiconductor components is their emitter efficiency.
Um einen möglichst hohen Emitterwirkungsgrad zu erzielen, muß die Emitterzone möglichst hoch dotiert sein. Gleichzeitig ist es jedoch erforderlich, daß die Raumladungszone im Sperrbetrieb über eine möglichst lange Wegstrecke an der Schei- benoberflache verläuft. Zum Zwecke der Vergrößerung der für die Raumladungszone auf der Scheibenoberfläche zur Verfügung stehende Wegstrecke, weist der seitliche Rand des Halbleiterkörpers typischerweise eine positive Anschrägung auf.In order to achieve the highest possible emitter efficiency, the emitter zone must be doped as high as possible. At the same time, however, it is necessary for the space charge zone to run over the longest possible distance on the surface of the window in blocking operation. For the purpose of enlarging the path available for the space charge zone on the wafer surface, the lateral edge of the semiconductor body typically has a positive bevel.
Diese Maßnahme ist bei sehr hochsperrenden Leistungshalbleiterbauelementen in aller Regel jedoch nicht ausreichend. Aus diesem Grunde sind im Randbereich der Leistungshalbleiterbauelemente, d. h. außerhalb deren aktiven Bereiche, typischerweise weite Teile an der Halbleiteroberfläche herausgeätzt. Durch die dadurch entstehenden Ätzschultern wird zwar die zur Verfügung stehende freie Wegstrecke für die Raumladungszone weiter vergrößert, aufgrund der dadurch reduzierten Emitter- zone verringert sich aber gleichzeitig die für einen Spannungsdurchbruch an der Halbleiteroberfläche notwendige Gesamtladungsträgerkonzentration.However, this measure is generally not sufficient for very high-blocking power semiconductor components. For this reason, in the edge region of the power semiconductor components, that is to say outside of their active regions, large parts are typically etched out on the semiconductor surface. Due to the resulting etching shoulders, the available free path for the space charge zone is further increased due to the reduced emitter zone, however, the total charge carrier concentration required for a voltage breakdown on the semiconductor surface is reduced at the same time.
Das vollständige Entfernen der stark dotierten Emitterzone im Randbereich führt bei einer Punch-Through-Dimensionierung zu sehr hohen Feldstärkespitzen an der Scheibenoberfläche im Bereich der Atzschultern, da hier die für das Erreichen der vollen Sperrfähigkeit erforderliche Durchbruchsladung - bei Silizium beträgt diese etwa 10***-2 cm-2 - nicht mehr vorhanden ist. Übersteigt diese Feldstärke die kritische Durchbruch- feldstärke, die bei Silizium typischerweise zwischen 170 und 220 kV cm--**- liegt, kommt es im Randbereich zum unerwünschten, d.h. verfrühten Durchbruch der Halbleiterstruktur schon bei niedrigen Spannungen.The complete removal of the heavily doped emitter zone in the edge area leads to very high field strength peaks on the pane surface in the area of the etching shoulders in the case of punch-through dimensioning, since here the breakthrough charge required to achieve full blocking capacity - for silicon this is approximately 10 * ** - 2 cm -2 - is no longer available. If this field strength exceeds the critical breakdown field strength, which is typically between 170 and 220 kV cm - ** - for silicon, undesirable, ie premature, breakdown of the semiconductor structure occurs even at low voltages.
Um zu verhindern, daß es bei gattungsgemäßen Leistungshalbleiterbauelementen zu einem solchen unerwünschten Durchbruch im Randbereich kommt, muß dafür gesorgt werden, daß dort an der Oberfläche das Integral der Ionisierung immer kleiner ist, als im Volumen, d. h. es müssen dort die unerwünschten Feldspitzen des elektrischen Feldes abgebaut werden.In order to prevent such undesirable breakthrough in the edge region from occurring in the case of generic power semiconductor components, care must be taken that the integral of the ionization there is always smaller on the surface than in the volume, ie. H. the undesired field peaks of the electrical field must be reduced there.
Ein gängiges Verfahren zum Aufbau von zusätzlichen Ladungen im Randbereich bzw. zum Abbau der genannten Feldspitzen ist der Einsatz von elektroaktiven Passivierungsschichten aus typischerweise amorphen, wasserstoffhaltigen Kohlenstoffschichten oder aus amorphen, wasserstoffhaltigen Siliziumkarbidschichten. In der EP 0 400 178 Bl ist ein Verfahren zur elek- troaktiven Passivierung beschrieben. Der Vorteil dieses Verfahrens besteht darin, daß in der genannten amorphen Schicht aktiv Ladungen selbstjustierend genau dort aufgebaut werden können, die gewissermaßen selbstjustierend Feldstärkespitzen abschwächen können.A common method for building up additional charges in the edge region or for reducing the field peaks mentioned is the use of electroactive passivation layers made of typically amorphous, hydrogen-containing carbon layers or of amorphous, hydrogen-containing silicon carbide layers. EP 0 400 178 B1 describes a method for electroactive passivation. The advantage of this method is that charges can be actively built up in the amorphous layer mentioned there, which to a certain extent can weaken field strength peaks in a self-adjusting manner.
Bei der Entwicklung sehr verlustarmer Leistungshalbleiterbauelemente reicht diese Maßnahme jedoch alleine nicht mehr aus. Insbesondere nimmt die Ladungsdichte der Oberflächenladungen mit der Temperatur ab, so daß eine ausreichende Sperrfähigkeit insbesondere bei sehr tiefen Temperaturen nicht mehr gewährleistet werden kann.However, this measure alone is no longer sufficient in the development of very low-loss power semiconductor components. Ins pecial b takes the charge density of surface charges with temperature, so that a sufficient blocking ability can not be ensured, in particular at very low temperatures.
Ausgehend von diesem Stand der Technik ist es daher die Aufgabe der vorliegenden Erfindung, ein weiteres gattungsgemäßes Leistungshalbleiterbauelement anzugeben, dessen Randbereich auch unter extremen Bedingungen funktionsfähig bleibt und die volle Sperrfähigkeit des Halbleiterbauelements gewährleistet.Based on this prior art, it is therefore the object of the present invention to provide a further generic power semiconductor component, the edge region of which remains functional even under extreme conditions and ensures the full blocking capability of the semiconductor component.
Erfindungsgemäß wird diese Aufgabe durch ein Leistungshalbleiterbauelement mit den Merkmalen des Patentanspruchs 1 gelöst .According to the invention, this object is achieved by a power semiconductor component having the features of patent claim 1.
Erfindungsgemäß sind im Randbereich unterhalb der aus dem Halbleiterkörper herausgeätzten Bereiche (Ätzschultern) Feldstopzonen vom selben Leitungstyp wie in der Innenzone vorgesehen sind. Diese Feldstopzonen, die typischerweise an die Innenzone sowie an die Emitterzone angeschlossen sind, grenzen an die poliergeätze, damagefreie Oberfläche der herausgeätzten Ätzschultern an. Die Dotierungskonzentration dieser Feldstopzonen, die zwischen der der Emitterzone und der der Innenzone liegt, ist dabei derart eingestellt, daß sich von der Oberfläche der Ätzschultern in die Tiefe des Halbleiterkörpers hinein ein abnehmender Gradient im Konzentrationsverlauf der Dotierung ergibt. Auf diese Weise kann selbst unter Extrembedingungen sichergestellt werden, daß das Halbleiterbauelement nicht unbeabsichtigter Weise vor Erreichen der vorgegebenen Volumen-Durchbruchsspannung durchbricht.According to the invention, field stop zones of the same conductivity type as in the inner zone are provided in the edge area below the areas (etched shoulders) etched out of the semiconductor body. These field stop zones, which are typically connected to the inner zone and to the emitter zone, adjoin the polished, damageless surface of the etched-out shoulders. The doping concentration of these field stop zones, which lies between that of the emitter zone and that of the inner zone, is set in such a way that there is a decreasing gradient in the concentration profile of the doping from the surface of the etching shoulders into the depth of the semiconductor body. In this way it can be ensured, even under extreme conditions, that the semiconductor component does not accidentally break down before the predetermined volume breakdown voltage is reached.
Der Verlauf der Dotierungskonzentration ist im Randbereich derart eingestellt, daß nach dem Abätzen einer Mindestdicke, die zur Erzeugung einer poliergeätzten, damagefreien Oberflä- ehe erforderlich ist, die Durchsbruchladung resultiert. Dabei ist man nahzu unabhängig von der Tiefe bzw. der Dicke der Emitterzone. Die Dotierungskonzentration in der Feldstopzone bzw. auch deren Tiefe muß dabei derart eingestellt werden, daß bezogen auf die vertikale Richtung die flächenbezogene Ladungsträgerdichte gemessen aus Feldstopzone und darunter liegender Innenzone etwa gleich der Durchbruchsladungsdichte beträgt. Die Dotierungskonzentration bzw. die eingebrachte Ladungsträgermenge in der Feldstopzone kann dabei durch Ionenimplantation gezielt eingestellt bzw. kontrolliert werden.The course of the doping concentration is set in the edge region in such a way that the breakdown charge results after etching off a minimum thickness which is required to produce a polish-etched, damagefree surface. One is almost independent of the depth or the thickness of the emitter zone. The doping concentration in the field stop zone The depth of the charge carrier measured from the field stop zone and the inner zone below it is approximately equal to the breakthrough charge density, based on the vertical direction. The doping concentration or the amount of charge carriers introduced in the field stop zone can be specifically set or controlled by ion implantation.
Alternativ wäre es auch denkbar, die Feldstopzone nicht nur im Randbereich vorzusehen, sondern großflächig jeweils unter der Emitterzone als auch unmittelbar unter den herausgeätzten Bereichen im Randbereich anzuordnen.Alternatively, it would also be conceivable not only to provide the field stop zone in the edge region, but also to arrange it extensively under the emitter zone as well as directly under the etched-out regions in the edge region.
Grundsätzlich ist es auch denkbar, wenn die herausgeätzten Bereiche an der Scheibenoberfläche nicht ideal horizontal verlaufen, sondern in einem flachen Winkel von einigen Grad nach außen hin abfallen. In diesem Fall kann ebenfalls ein zum Rand hin abfallender Gradient in der Dotierungskonzentration erzeugt werden.In principle, it is also conceivable if the etched-out areas on the pane surface do not run ideally horizontally, but fall outward at a flat angle of a few degrees. In this case, a gradient in the doping concentration falling towards the edge can also be generated.
Äquivalent ist es auch denkbar, wenn der Konzentrationsver- lauf der Feldstopzone in lateraler Richtung einen flach verlaufenden Gradienten zum Rand des Leistungshalbleiterbauelementes hin aufweist. In diesem Fall müssen zusätzlich ent- sprechende Berechnungen für die lateral gemittelten Flächenladungsdichten vorgenommen werden.Equivalently, it is also conceivable if the concentration profile of the field stop zone has a flat gradient in the lateral direction towards the edge of the power semiconductor component. In this case, corresponding calculations must also be made for the laterally averaged surface charge densities.
Ferner ist es auch denkbar, zusätzlich zu der Bereitstellung der genannten Feldstopzone eine elektroaktive Passivierungs- Schicht im Randbereich, wie sie in der EP 0 400 178 Bl beschrieben ist, vorzusehen.Furthermore, it is also conceivable to provide an electroactive passivation layer in the edge area, as described in EP 0 400 178 B1, in addition to the provision of the field stop zone mentioned.
Die Erfindung eignet sich insbesondere für Leistungsdioden (pin-Dioden) mit Mesa-Randabschluß, die beispielsweise als Freilaufdioden von IGBTs und GTOs verwendet werden. Die Erfindung ist aber auch sehr vorteilhaft bei anderen, asymme- trisch sperrenden Leistungshalbleiterbauelementen mit Mesa- Randabschluß, wie IGBTs, GTOs und dergleichen, anwendbar.The invention is particularly suitable for power diodes (pin diodes) with a mesa edge termination, which are used, for example, as free-wheeling diodes of IGBTs and GTOs. However, the invention is also very advantageous with other, asymmetrical Trically blocking power semiconductor components with mesa edge termination, such as IGBTs, GTOs and the like, applicable.
Vorteilhafte Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche.Advantageous developments of the invention are the subject of the dependent claims.
Die Erfindung wird nachfolgend anhand der in den Figuren derThe invention is based on the in the figures of the
Zeichnung angegebenen Ausführungsbeispiele näher erläutert.Exemplary embodiments illustrated in the drawing.
Es zeigt dabei:It shows:
Figur 1 schematisch in einem Teilschnitt ein erstes Ausführungsbeispiel eines als pin-Diode ausgebildeten, erfindungsgemäßen Leistungshalbleiterbauelements ;FIG. 1 shows schematically in a partial section a first exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode;
Figur 2 schematisch in einem Teilschnitt ein zweites Ausführungsbeispiel eines als pin-Diode ausgebildeten, erfindungsgemäßen Leistungshalbleiterbauelements;FIG. 2 shows schematically in a partial section a second exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode;
Figur 3 schematisch in einem Teilschnitt ein Ausführungs- beispiel eines als GTO ausgebildeten, erfindungsgemäßen Leistungshalbleiterbauelements;FIG. 3 schematically, in a partial section, an exemplary embodiment of a power semiconductor component according to the invention designed as a GTO;
Figur 4 schematisch in einem Teilschnitt ein Ausführungsbeispiel eines als IGBT ausgebildeten, erfindungsge- mäßen Leistungshalbleiterbauelements .FIG. 4 schematically, in a partial section, an exemplary embodiment of a power semiconductor component according to the invention designed as an IGBT.
In allen Figuren der Zeichnung sind gleiche oder funktionsgleiche Elemente - sofern nichts anderes angegeben ist - mit gleichen Bezugszeichen versehen. Zu allen Figuren der Zeich- nung sei vorab angemerkt, daß dort - obgleich es sich umIn all the figures of the drawing, identical or functionally identical elements are provided with the same reference numerals, unless stated otherwise. For all figures in the drawing, it should be noted in advance that there - although it is
Schnittdarstellungen handelt - aus Gründen der Übersichtlichkeit keine Schraffuren eingezeichnet sind.Sectional representations - for the sake of clarity, no hatching is shown.
Figur 1 zeigt schematisch in einem Teilschnitt ein erstes Ausführungsbeispiel eines als pin-Diode ausgebildeten, erfindungsgemäßen Leistungshalbleiterbauelements . In Figur 1 ist mit 1 der Halbleiterkörper der pin-Diode bezeichnet. Die pin-Diode weist einen Anodenanschluß A und einen Kathodenanschluß K auf, die an gegenüberliegenden Seiten des Halbleiterkörpers 1 angeordnet sind.FIG. 1 shows schematically in a partial section a first exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode. In Figure 1, 1 denotes the semiconductor body of the pin diode. The pin diode has an anode connection A and a cathode connection K, which are arranged on opposite sides of the semiconductor body 1.
Der Halbleiterkörper 1, der beispielsweise aus Siliziumsubstrat besteht, weist eine im vorliegenden Ausführungsbeispiel schwach n-dotierte Innenzone 2 auf. Anodenseitig grenzt großflächig eine p-dotierte Anodenzone 3 an die Innenzone 2 an. Die Grenzfläche 4, die bei einer pin-Diode typischerweise lateral über die gesamte Breite des Halbleiterkörpers 1 verläuft, definiert deren pn-Übergang 4. Anodenseitig grenzt die Anodenzone 3 an die rückseitige Oberfläche 5 des Halbleiterkörpers 1 an. Die Anodenzone 3 ist hier über eine großflächi- ge auf die Oberfläche 5 aufgebrachte Anodenmetallisierung bzw. Anodenelektrode 6 mit dem Anodenanschluß A verbunden.The semiconductor body 1, which consists for example of silicon substrate, has an inner zone 2 which is weakly n-doped in the present exemplary embodiment. A p-doped anode zone 3 adjoins the inner zone 2 over a large area on the anode side. The interface 4, which typically extends laterally across the entire width of the semiconductor body 1 in the case of a pin diode, defines its pn junction 4. The anode zone 3 adjoins the anode zone 3 on the rear surface 5 of the semiconductor body 1. The anode zone 3 is here connected to the anode connection A via a large-area anode metallization or anode electrode 6 applied to the surface 5.
Kathodenseitig ist mindestens eine, im vorliegenden Fall stark n-dotierte Kathodenzone 8 in die vorderseitige Oberflä- ehe 7 des Halbleiterkörpers 1 eingebettet. Die Kathodenzone 8 weist denselben Leitungstyp, jedoch eine sehr viel höhere Do- tierungskonzentration als die Innenzone 2 auf und dient somit als Feldstopzone dem Feldabbau des elektrischen Feldes an der vorderseitigen Oberfläche 7. Die Kathodenzone 8 ist an diesem Ort wannenförmig in die Innenzone 2 eingebettet und kann beispielsweise durch Ionenimplantation mit fakultativ sich anschließendem Temperaturschritt bzw. durch Diffusion in den Halbleiterkörper 1 eingebracht worden sein. Die Kathodenzone 8 ist an der Oberfläche 7 über eine Katodenmetallisierung bzw. eine Kathodenelektrode 9 mit dem Kathodenanschluß K verbunden. Der Bereich der pin-Diode, der durch die Kathodenzone 8 definiert ist, wird auch als aktiver Bereich AB der pin- Diode bezeichnet.On the cathode side, at least one, in the present case heavily n-doped, cathode zone 8 is embedded in the front surface 7 of the semiconductor body 1. The cathode zone 8 has the same conductivity type, but a much higher doping concentration than the inner zone 2 and thus serves as a field stop zone for the field breakdown of the electric field on the front surface 7. The cathode zone 8 is embedded in the inner zone 2 at this location and trough-shaped may have been introduced into the semiconductor body 1, for example, by ion implantation with an optionally subsequent temperature step or by diffusion. The cathode zone 8 is connected to the cathode connection K on the surface 7 via a cathode metallization or a cathode electrode 9. The region of the pin diode, which is defined by the cathode zone 8, is also referred to as the active region AB of the pin diode.
Im vorliegenden Ausführungsbeispiel sind im Randbereich RB, der im wesentlichen durch die außerhalb des aktiven Bereichs AB befindlichen Bereiche des Halbleiterkörpers 1 definiert wird, aus dem Halbleiterkörper 1 herausgeätzte Bereich 10 vorgesehen. Durch das Herausätzen der Bereiche 10 im Randbereich RB wird eine Ätzschulter 13 zwischen Kathodenzone 8 und Randbereich RB definiert. Diese Ätzschultern 12 bzw. die da- durch erzeugten poliergeätzten Oberflächen 7' verlaufen im Beispiel der Figur 1 im wesentlichen horizontal. Es wäre selbstverständlich auch denkbar, daß diese Ätzschultern 12 einen zum Rand hin leicht geneigten Verlauf nehmen.In the present exemplary embodiment, the edge region RB defines essentially the regions of the semiconductor body 1 located outside the active region AB is provided, the area 10 etched out of the semiconductor body 1. By etching out the areas 10 in the edge area RB, an etching shoulder 13 is defined between the cathode zone 8 and the edge area RB. In the example of FIG. 1, these etching shoulders 12 or the surfaces 7 ′ that are produced as a result of polishing run essentially horizontally. It would of course also be conceivable that these etching shoulders 12 take a slightly inclined course towards the edge.
In die unterhalb der Ätzschultern 12 liegenden Bereiche ist eine n-dotierte Feldstopzone 11 vorgesehen. Diese Feldstopzone 11 weist hier denselben Leitungstyp wie die Innenzone 2 und die Kathodenzone 8 auf. Die Feldstopzone 11 ist an die Kathodenzone 8 angeschlossen und zwischen den poliergeätzten Oberflächen 7' und der Innenzone 2 angeordnet. Besonders vorteilhaft ist es, wenn die Dotierungskonzentration der Feldstopzone 11 niedriger ist als die der Kathodenzone 8 und höher ist als die der Innenzone 2. Auf diese Weise kann gewährleistet werden, daß im Randbereich RB der pin-Diode ein fla- eher Gradient der Dotierungskonzentration von der Oberfläche 7! zur Innenzone erzeugt wird.An n-doped field stop zone 11 is provided in the areas below the etching shoulders 12. This field stop zone 11 here has the same conductivity type as the inner zone 2 and the cathode zone 8. The field stop zone 11 is connected to the cathode zone 8 and is arranged between the polished-etched surfaces 7 ′ and the inner zone 2. It is particularly advantageous if the doping concentration of the field stop zone 11 is lower than that of the cathode zone 8 and higher than that of the inner zone 2. In this way it can be ensured that a flatter gradient of the doping concentration of in the edge region RB of the pin diode the surface 7 ! to the inner zone.
Im vorliegenden Ausführungsbeispiel weist die Feldstopzone 11 eine homogene n-Dotierung auf. In einer Weiterbildung wäre es auch sehr vorteilhaft, wenn die Feldstopzone 11 zum Rand hin eine sich langsam verringernde Dotierungskonzentration aufweist.In the present exemplary embodiment, the field stop zone 11 has a homogeneous n-doping. In a further development, it would also be very advantageous if the field stop zone 11 has a slowly decreasing doping concentration towards the edge.
Die pin-Diode in Figur 1 ist in einer sogenannter Mesa- Struktur aufgebaut. Derartige Mesa-Strukturen weisen eine typischerweise positive Anschrägung der seitlichen Wände 13 des Halbleiterkörpers 1 auf. Im vorliegenden Ausführungsbeispiel ist dieser Anschrägewinkel der seitlichen Wand 13 mit α bezeichnet. Typische Werte des Anschrägewinkels α bei einer Me- sa-Struktur liegen zwischen 20 und 45°. Im Ausführungsbeispiel in Figur 1 sind die Feldstopzonen 11 lediglich im Randbereich RB des Halbleiterbauelementes vorgesehen. Es wäre selbstverständlich auch denkbar, wenn die Feldstopzone 11 als durchgehende Schicht über die gesamte Breite des Halbleiterkörpers 1 angeordnet ist. Dieser Fall ist im Ausführungsbeispiel in Figur 2 dargestellt. Hier ist die Feldstopzone 11 sowohl im Randbereich RB als auch im aktiven Bereich AB der pin-Diode angeordnet. Insbesondere im aktiven Bereich AB der pin-Diode beabstandet die Feldstopzone 11 somit die Kathodenzone 8 und die Innenzone 2 voneinander.The pin diode in FIG. 1 is constructed in a so-called mesa structure. Such mesa structures have a typically positive beveling of the side walls 13 of the semiconductor body 1. In the present exemplary embodiment, this taper angle of the side wall 13 is designated by α. Typical values of the bevel angle α for a brass structure are between 20 and 45 °. In the exemplary embodiment in FIG. 1, the field stop zones 11 are only provided in the edge region RB of the semiconductor component. It would of course also be conceivable if the field stop zone 11 is arranged as a continuous layer over the entire width of the semiconductor body 1. This case is shown in the exemplary embodiment in FIG. 2. Here, the field stop zone 11 is arranged both in the edge region RB and in the active region AB of the pin diode. In particular in the active region AB of the pin diode, the field stop zone 11 thus spaces the cathode zone 8 and the inner zone 2 from one another.
Bei der in Figur 1 dargestellten Ausführungsform der pin-Diode kann die Feldstopzone 11 vorteilhafterweise nach dem Abätzen der Bereiche 10 selbstjustierend mittels der als Mas- ke fungierenden Kathodenelektrode 9 in den Halbleiterkörper 1 eingebracht werden.In the embodiment of the pin diode shown in FIG. 1, the field stop zone 11 can advantageously be introduced into the semiconductor body 1 by means of the cathode electrode 9, which acts as a mask, after the areas 10 have been etched off.
Bei der in Figur 2 dargestellten Ausführungsform einer pin- Diode ist eine Feldstopzone 11 vorgesehen, die großflächig in den Halbleiterkörper 1 eingebracht worden ist. Anschließend wird großflächig auf die Feldstopzone 11 die Kathodenzone 8 beispielsweise über einen Abscheideprozeß aufgebracht. Schließlich werden, um polierte, damagefreie Oberflächen 7' im Randbereich RB der pin-Diode zu erlangen, die entsprechen- den Bereiche 10 aus dem Halbleiterkörper 1 herausgeätzt.In the embodiment of a pin diode shown in FIG. 2, a field stop zone 11 is provided, which has been introduced over a large area into the semiconductor body 1. The cathode zone 8 is then applied over a large area to the field stop zone 11, for example by means of a deposition process. Finally, in order to obtain polished, damagefree surfaces 7 ′ in the edge region RB of the pin diode, the corresponding regions 10 are etched out of the semiconductor body 1.
Zusätzlich zu den in den Figuren 1 und 2 vorgesehenen Feldstopzone 11 im Randbereich RB können, wie bereits eingangs erwähnt, auf die Oberflächen 7' elektroaktive Passivierungs- schichten, beispielsweise aus einer amorphen Kohlenstoffverbindung, aufgebracht werden.In addition to the field stop zones 11 provided in FIGS. 1 and 2 in the edge region RB, as already mentioned at the beginning, electroactive passivation layers, for example made of an amorphous carbon compound, can be applied to the surfaces 7 '.
Nachfolgend wird die Funktion der erfindungsgemäßen Feldstopzone 11 bei der pin-Diode gemäß Figur 3 oder 4 näher be- schrieben: Bei Halbleiterbauelementen mit sehr hochsperrenden pn- Übergängen 4 müssen Maßnahmen zum Feldabbau des elektrischen Feldes an der Oberfläche 7, 7λ getroffen werden. Bei einer auf Punch-Through dimensionierten pin-Diodenstruktur stößt die Raumladungszone im Sperrbetrieb an eine Feldstopzone an. Diese Feldstopzone wird bei einer gattungsgemäßen pin-Diode typischerweise durch die Emitterzone 8 gebildet. Die Raumladungszone wird durch diese, als Emitterzone 8 ausgebildete Feldstopzone aufgefangen. Das elektrische Feld steilt sich in dieser Emitterzone 8 auf und es entsteht im Volumen des Halbleiterkörpers 1 ein trapezförmiger Feldverlauf des elektrischen Feldes. Durch diesen trapezförmigen Feldverlauf wird das elektrische Feld zur Oberfläche 7 des Halbleiterkörpers 1 hin abgebaut.The function of the field stop zone 11 according to the invention in the case of the pin diode according to FIG. 3 or 4 is described in more detail below: In the case of semiconductor components with very high-blocking pn junctions 4, measures for reducing the electric field at the surface 7, 7 λ must be taken. In the case of a pin diode structure dimensioned for punch-through, the space charge zone hits a field stop zone in blocking operation. In the case of a generic pin diode, this field stop zone is typically formed by the emitter zone 8. The space charge zone is captured by this field stop zone designed as an emitter zone 8. The electric field rises in this emitter zone 8 and a trapezoidal field profile of the electric field is created in the volume of the semiconductor body 1. Due to this trapezoidal field profile, the electric field is reduced towards the surface 7 of the semiconductor body 1.
Im Randbereich RB des Leistungshalbleiterbauelementes ist jedoch der Feldverlauf aufgrund der dort fehlenden Emitterzone 8 und somit der erforderlichen Feldstopzone nicht mehr trapezförmig; durch das Aufsteilen des elektrischen Feldes kommt es hier vielmehr zu mitunter extremen Feldspitzen an den Ätzschultern 12. Um zu verhindern, daß es im Randbereich RB zu einem unerwünschten, d.h. verfrühten Spannungsdurchbruch schon bei geringen Sperrspannungen kommt, werden hier die erfindungsgemäßen Feldstopzonen 11 in den Bereichen unterhalb der Ätzschultern 12 in den Halbleiterkörper 1 eingebracht. Es ist dabei darauf zu achten, daß diese Feldstopzonen 11 nicht unterbrochen sind, d.h. sie müssen direkt an die ebenfalls als Feldstopzone ausgebildete Emitterzone 8 sowie an die Innenzone 2 angeschlossen sein. Auf diese Weise wird gewährlei- stet, daß über die gesamte Breite des Halbleiterkörpers 1 ein trapezförmiger Feldverlauf vom pn-Übergang zur Oberfläche 7, 7 hin erzeugt wird und damit Feldspitzen im Randbereich RB vermieden werden.In the edge area RB of the power semiconductor component, however, the field profile is no longer trapezoidal due to the lack of emitter zone 8 there and thus the required field stop zone; Rather, the division of the electric field sometimes leads to extreme field peaks on the etching shoulders 12. In order to prevent undesired, i.e. If there is premature voltage breakdown even at low reverse voltages, the field stop zones 11 according to the invention are introduced into the semiconductor body 1 in the areas below the etching shoulders 12. It is important to ensure that these field stop zones 11 are not interrupted, i.e. they must be connected directly to the emitter zone 8, which is also designed as a field stop zone, and to the inner zone 2. In this way it is ensured that a trapezoidal field profile is generated across the entire width of the semiconductor body 1 from the pn junction to the surface 7, 7 and thus field peaks in the edge region RB are avoided.
Die vorliegende Erfindung ist nicht ausschließlich auf als pin-Dioden ausgebildete Leistungshalbleiterbauelemente beschränkt, sondern kann auch sehr vorteilhaft bei anderen Lei- stungshalbleiterbauele enten angewendet werden. Die Figuren 3 und 4 zeigen zwei weitere vorteilhafte Ausführungsbeispiele.The present invention is not limited exclusively to power semiconductor components designed as pin diodes, but can also be very advantageous with other cables. semiconductor devices are used. Figures 3 and 4 show two further advantageous embodiments.
Figur 3 zeigt schematisch in einem Teilschnitt ein Ausfüh- rungsbeispiel eines als GTO ausgebildeten Leistungshalbleiterbauelements mit erfindungsgemäßem Randabschluß .FIG. 3 schematically shows a partial section of an exemplary embodiment of a power semiconductor component designed as a GTO with an edge termination according to the invention.
Der GTO (Gate-Turn-Off-Thyristor) , der hier als asymmetrisch sperrender Thyristor ausgebildet ist, weist einen Anodenan- schluß A und einen Kathodenanschluß K an gegenüberliegenden Seiten des Halbleiterkörpers 1 auf. Der Halbleiterkörper 1 besteht aus einer n-dotierten n-Basiszone 20. Kathodenseitig schließt sich über einen großflächigen pn-Übergang 21 eine p- dotierte p-Basiszone 22 an die n-Basiszone 20 an. An die p- Basiszone 22 ist eine stark n-dotierte n-Emitterzone 23 angeschlossen. Die n-Emitterzone 23 ist über eine Kathodenmetallisierung bzw. Kathodenelektrode 24 an der rückseitigen Oberfläche 25 mit dem Kathodenanschluß K verbunden.The GTO (gate turn-off thyristor), which is designed here as an asymmetrically blocking thyristor, has an anode connection A and a cathode connection K on opposite sides of the semiconductor body 1. The semiconductor body 1 consists of an n-doped n-base zone 20. On the cathode side, a p-doped p-base zone 22 connects to the n-base zone 20 via a large-area pn junction 21. A heavily n-doped n-emitter zone 23 is connected to the p-base zone 22. The n-emitter zone 23 is connected to the cathode terminal K via a cathode metallization or cathode electrode 24 on the rear surface 25.
Anodenseitig ist im aktiven Bereich AB des Thyristors eine p- dotierte p-Emitterzone 26 in die vorderseitige Oberfläche 27 des Halbleiterkörpers 1 eingebettet. Die p-Emitterzone 26 ist dabei über eine großflächige Anodenmetallisierung bzw. Anodenelektrode 28 mit dem Anodenanschluß A verbunden. Ferner ist in Figur 3 die p-Emitterzone 26 über eine PufferschichtA p-doped p-emitter zone 26 is embedded in the front surface 27 of the semiconductor body 1 in the active region AB of the thyristor on the anode side. The p-emitter zone 26 is connected to the anode connection A via a large-area anode metallization or anode electrode 28. Furthermore, in FIG. 3 the p-emitter zone 26 is over a buffer layer
29 gegen die n-Basiszone 20 beabstandet. Über mindestens eine Durchkontaktierung 30 kann die p-Emitterzone 26 und damit die Anodenelektrode 28 an die n-Basiszone 20 angeschlossen sein. Diese Pufferzone 29 im anodenseitigen Bereich des Halbleiter- bauelementes dient somit im Sperrbetrieb als Feldstopzone. Prinzipiell ist auch ein durchgehender Emitter ohne Anodenkurzschlüsse denkbar.29 spaced from the n-base zone 20. The p-emitter zone 26 and thus the anode electrode 28 can be connected to the n-base zone 20 via at least one via 30. This buffer zone 29 in the region of the semiconductor component on the anode side thus serves as a field stop zone in blocking operation. In principle, a continuous emitter without anode short circuits is also conceivable.
Im vorliegenden Ausführungsbeispiel weist der Thyristor einen sogenannten transparenten Emitter, d.h. eine anodenseitigeIn the present embodiment, the thyristor has a so-called transparent emitter, i.e. an anode side
Pufferschicht 29 mit Anodenkurzschlüssen 30, auf. Bei solchen transparenten Emittern sind die p-Emitterzonen 26 nach der Ionenimplantation nicht vollständig ausgeheilt, um dadurch eine geringe Ladungsträgerinjektion zu gewährleisten. Diese Maßnahmen werden bei gattungsgemäßen Thyristoren bzw. GTOs durchgeführt, um diese definiert ein- bzw. ausschalten zu können. Anstelle eines solchen transparenten Emitters wäre alternativ auch denkbar, die Bereiche unterhalb der anoden- seitigen p-Emitterzone 26 mit Helium zu bestrahlen, um damit eine Reko binationssenke zu erzeugen.Buffer layer 29 with anode short circuits 30. With such transparent emitters, the p-emitter zones 26 are after the Ion implantation did not heal completely to ensure a low charge carrier injection. These measures are carried out with generic thyristors or GTOs in order to be able to switch them on and off in a defined manner. Instead of such a transparent emitter, it would alternatively also be conceivable to irradiate the areas below the anode-side p-emitter zone 26 with helium in order to thereby generate a recombination sink.
Im Randbereich RB, d. h. außerhalb des aktiven Bereiches AB des Thyristors, sind äquivalent wie bei den Diodenstrukturen der Figuren 1 und 2 aus dem Halbleiterkörper 1 herausgeätzte Bereiche 31 vorgesehen. Diese sind unter den poliergeätzten Oberflächen 27 x der sich aus den herausgeätzten Bereichen 31 ergebenden Ätzschultern 33 angeordnet. Die Feldstopzonen 32 sind hier an die p-Emitterzone 26 angeschlossen. Die Feldstopzonen 32 sind n-dotiert und weisen eine höhere Dotierungskonzentration als die n-Basiszone 20 auf.Areas 31 etched out of the semiconductor body 1 are provided in the edge area RB, ie outside the active area AB of the thyristor, equivalent to the diode structures of FIGS. 1 and 2. These are arranged under the polished-etched surfaces 27 x of the etching shoulders 33 resulting from the etched-out regions 31. The field stop zones 32 are here connected to the p-emitter zone 26. The field stop zones 32 are n-doped and have a higher doping concentration than the n-base zone 20.
Im vorliegenden Ausführungsbeispiel ist der Thyristor als asymmetrischer Thyristor mit Feldstoppzone bzw. Pufferschicht 29 dargestellt. Damit die anodenseitige Verstärkung αpnp nicht verschwindet, darf bei anodenseitig kurzgeschlossenen Strukturen die Ladungsmenge in der Feldstopzone 29 nicht grö- ßer sein als die Durchbruchsladung.In the present exemplary embodiment, the thyristor is shown as an asymmetrical thyristor with a field stop zone or buffer layer 29. So that the anode-side gain α pn p does not disappear, the amount of charge in the field stop zone 29 must not be greater than the breakthrough charge in the case of structures short-circuited on the anode.
Die Funktionsweise dieser erfindungsgemäßen Feldstopzone 32 im Randbereich des Halbleiterbauelementes ist äquivalent zu der Funktionsweise der Feldstopzone 11 der pin-Dioden gemäß den Figuren 1 und 2. Insbesondere kann über die dotiertenThe mode of operation of this field stop zone 32 according to the invention in the edge region of the semiconductor component is equivalent to the mode of operation of the field stop zone 11 of the pin diodes according to FIGS. 1 and 2. In particular, the doped can
Feldstopzonen 32 bei einem Thyristor bzw. GTO äquivalent wie bei einer pin-Diode die vollständige Volumensperrfähigkeit auch im Randbereich RB des Halbleiterbauelementes gewährleistet werden.Field stop zones 32 in a thyristor or GTO, equivalent to a pin diode, ensure complete volume blocking capability also in the edge region RB of the semiconductor component.
Das in Figur 3 dargestellte Ausführungsbeispiel eines Thyristors zeigt lediglich eine mögliche vorteilhafte Ausführungs- form. Selbstverständlich läßt sich die erfindungsgemäße Randstruktur auch sehr vorteilhaft bei allen anderen, vertikal ausgebildeten Thyristoren mit Randabschluß, insbesondere GTOs sowie monolithisch integrierte Systeme wie z.B. rückwärtslei- tende Thyristoren, einsetzen.The exemplary embodiment of a thyristor shown in FIG. 3 shows only one possible advantageous embodiment. The edge structure according to the invention can of course also be used very advantageously with all other vertically designed thyristors with edge termination, in particular GTOs and monolithically integrated systems such as, for example, reverse-conducting thyristors.
Figur 4 zeigt schematisch in einem Teilschnitt ein Ausführungsbeispiel eines als IGBT ausgebildeten, erfindungsgemäßen Leistungshalbleiterbauelements, bei dem ebenfalls die erfin- dungsgemäße Randstruktur zur Anwendung kommt.FIG. 4 schematically shows in a partial section an exemplary embodiment of a power semiconductor component according to the invention designed as an IGBT, in which the edge structure according to the invention is also used.
Der IGBT in Figur 4 ist in bekannter Art und Weise aufgebaut. Da die Vierschichtstruktur des in Figur 4 gezeigten IGBTs (Insulated-Gate-Bipolar-Transistor) ähnlich wie die Vier- schichtstruktur des in Figur 3 dargestellten Thyristors aufgebaut ist, wird nachfolgend nur auf die sich vom Thyristor in Figur 3 unterschiedlichen Merkmale näher eingegangen.The IGBT in Figure 4 is constructed in a known manner. Since the four-layer structure of the IGBT (insulated gate bipolar transistor) shown in FIG. 4 is constructed similarly to the four-layer structure of the thyristor shown in FIG. 3, only the features that differ from the thyristor in FIG. 3 are discussed in more detail below.
An der Oberfläche 25 des Halbleiterkörpers 1 sind in bekann- ter Weise die p-Basiszonen 22, die bei einem IGBT typischer wannenförmig ausgebildet sind, in den Halbleiterkörper 1 eingebettet. In diese p-Basiszonen 22 sind die stark n-dotierten n-Emitterzonen 23 wannenförmig eingebettet. Die p-Basiszone 22 und die n-Emitterzonen 23 sind an der Oberfläche 25 in be- kannter Weise über eine als Nebenschluß ausgebildete Kathodenelektrode 35 miteinander verbunden. Zusätzlich ist hier eine MOS-Struktur vorgesehen. Die MOS-Struktur umfaßt eine Gateelektrode 36 und ein Gateoxid 37, die jeweils über die an die Oberfläche 25 tretende Bereiche der n-Basiszone 20, p- Basiszone 21 und n-Emitterzone 22 angeordnet sind.On the surface 25 of the semiconductor body 1, the p-base zones 22, which are typically trough-shaped in an IGBT, are embedded in the semiconductor body 1 in a known manner. The heavily n-doped n-emitter zones 23 are embedded in the shape of a trough in these p-base zones 22. The p-base zone 22 and the n-emitter zones 23 are connected to one another on the surface 25 in a known manner via a cathode electrode 35 designed as a shunt. In addition, a MOS structure is provided here. The MOS structure comprises a gate electrode 36 and a gate oxide 37, which are each arranged over the regions of the n-base zone 20, p-base zone 21 and n-emitter zone 22 which come to the surface 25.
Die an der Oberfläche 27 angeordnete p-Emitterzone 26 ist bei dem IGBT als Kollektor ausgebildet. Im Unterschied zu dem GTO in Figur 3 weist der IGBT in Figur 4 keine Durchkontaktierun- gen 30 zwischen p-Kollektorzone 26 und n-Basiszone 20 auf.The p-emitter zone 26 arranged on the surface 27 is designed as a collector in the IGBT. In contrast to the GTO in FIG. 3, the IGBT in FIG. 4 has no plated-through holes 30 between p-collector zone 26 and n-base zone 20.
Prinzipiell wäre selbstverständlich auch ein IGBT mit durchgehendem transparenten Emitter mit Anodenkurzschluß denkbar. 00/42662In principle, an IGBT with a continuous transparent emitter with anode short circuit would of course also be conceivable. 00/42662
1313
Bei dem IGBT gemäß Figur 4 dient äquivalent wie bei dem Thyristor in Figur 3 die Pufferzone 29 als Feldstopzone zum Abbau des elektrischen Feldes an der Scheibenoberfläche. Die Funktion der erfindungsgemäßen Feldstopzone 32 ist hier äquivalent zu den vorgenannten Beispielen einer pin-Dioden gemäß den Figuren 1 oder 2 bzw. des GTO' s gemäß Figur 3.In the IGBT according to FIG. 4, the buffer zone 29 serves as a field stop zone for the reduction of the electric field on the surface of the pane, equivalent to the thyristor in FIG. The function of the field stop zone 32 according to the invention is here equivalent to the aforementioned examples of a pin diode according to FIGS. 1 or 2 or of the GTO according to FIG. 3.
Bei den in den Figuren 1 bis 4 dargestellten hochspannungsfe- sten Leistungshalbleiterbauelementen sind die Randbereiche RB derselben in Mesa-Struktur ausgebildet. Selbstverständlich ist die vorliegende Erfindung auch sehr vorteilhaft auf Leistungshalbleiterbauelementen mit auf welche Art auch immer ausgebildeten Randabschlüssen anwendbar.In the high-voltage-resistant power semiconductor components shown in FIGS. 1 to 4, the edge regions RB thereof are formed in a mesa structure. Of course, the present invention is also very advantageously applicable to power semiconductor components with edge closures of whatever type.
Die vorstehend genannten Ausführungsbeispiele sollen als die wesentlichen der Erfindung angesehen werden. Es ist jedoch anhand der Figuren 1 bis 4 leicht erkennbar, wie mögliche andere Ausführungsbeispiele der erfindungsgemäßen Halbleiter- bauelemente aussehen können; dies sind allgemein beliebige asymmetrisch sperrende Halbleiterbauelemente, wie Dioden, Thyristoren, Transistoren, IGBTs und dergleichen. The above-mentioned exemplary embodiments are to be regarded as the essentials of the invention. However, it can easily be seen from FIGS. 1 to 4 how possible other exemplary embodiments of the semiconductor components according to the invention can look; these are generally any asymmetrically blocking semiconductor components, such as diodes, thyristors, transistors, IGBTs and the like.

Claims

Patentansprüche claims
1. Leistungshalbleiterbauelement mit einem Mesa-Randabschluß,1. power semiconductor component with a mesa edge termination,
- mit mindestens einer in dem Halbleiterkörper (1) angeord- neten Innenzone (2, 20) des ersten Leitungstyps,- With at least one inner zone (2, 20) of the first conductivity type arranged in the semiconductor body (1),
- mit mindestens einer mit der Innenzone (2, 20) verbundenen und an die erste Oberfläche (7, 7'; 27, 27') des Halbleiterkörpers (1) angrenzenden ersten Zone (8, 26),with at least one first zone (8, 26) connected to the inner zone (2, 20) and adjoining the first surface (7, 7 '; 27, 27') of the semiconductor body (1),
- mit einem Randbereich (RB) außerhalb der ersten Zone (8, 26) , wobei im Randbereich (RB) zumindest teilweise aus der ersten Oberfläche (7, 1 ' ; 27, 27') herausgeätzte Bereiche (10, 31) vorgesehen sind,with an edge area (RB) outside the first zone (8, 26), areas (10, 31) etched out of the first surface (7, 1 '; 27, 27') being provided in the edge area (RB),
- mit mindestens einer zweiten Zone (3, 22) des zweiten Leitungstyps, die großflächig über einen pn-Übergang (4) an die Innenzone (2, 20) angeschlossen ist, und- With at least one second zone (3, 22) of the second conduction type, which is connected over a large area via a pn junction (4) to the inner zone (2, 20), and
- mit mindestens einer im Randbereich (RB) an die erste Oberfläche (7', 27') angrenzende Feldstopzone (11, 32) des ersten Leitungstyps, die in den Halbleiterkörper (1) eingebettet ist und die zumindest teilweise an die erste Zone (8, 26) und an die Innenzone (2, 20) angeschlossen ist.- With at least one field stop zone (11, 32) of the first conduction type adjacent to the first surface (7 ', 27') in the edge region (RB), which is embedded in the semiconductor body (1) and which is at least partially adjacent to the first zone (8 , 26) and is connected to the inner zone (2, 20).
2. Leistungshalbleiterbauelement nach Anspruch 1, dadurch gekennzeichnet, daß die Feldstopzone (11, 32) die erste Zone (8, 26) und die Innenzone (2, 20) voneinander derart beabstandet, daß die erste Zone (8, 26) und die Innenzone (2, 20) potentialmäßig getrennt sind.2. Power semiconductor component according to claim 1, characterized in that the field stop zone (11, 32), the first zone (8, 26) and the inner zone (2, 20) spaced from each other such that the first zone (8, 26) and the inner zone (2, 20) are electrically isolated.
3. Leistungshalbleiterbauelement nach einem der vorstehenden Ansprüchen, dadurch gekennzeichnet, daß die Feldstopzone (11, 32) eine höhere Dotierungskonzen- tration als die Innenzone (2, 20) aufweist und/oder daß die Feldstopzone (11, 32) eine niedrigere Dotierungskonzentration als die erste Zone (8, 26) aufweist. 3. Power semiconductor component according to one of the preceding claims, characterized in that the field stop zone (11, 32) has a higher doping concentration than the inner zone (2, 20) and / or that the field stop zone (11, 32) has a lower doping concentration than that has first zone (8, 26).
4. Leistungshalbleiterbauelement nach einem oder mehreren der vorstehenden Ansprüchen, dadurch gekennzeichnet, daß die Dotierungskonzentration der Innenzone (2, 20) und der Feldstopzone (11, 32) im Randbereich (RB) derart eingestellt sind, daß die flächenbezogene Ladung im Sperrbetrieb der Durchbruchsladung des Leistungshalbleiterbauelements entspricht .4. Power semiconductor component according to one or more of the preceding claims, characterized in that the doping concentration of the inner zone (2, 20) and the field stop zone (11, 32) in the edge region (RB) are set such that the area-related charge in the blocking operation of the breakthrough charge Power semiconductor device corresponds.
5. Leistungshalbleiterbauelement nach einem oder mehreren der vorstehenden Ansprüchen, dadurch gekennzeichnet, daß die Dotierungskonzentration der Ladungsträger des ersten5. Power semiconductor component according to one or more of the preceding claims, characterized in that the doping concentration of the charge carriers of the first
Leitungstyp im Randbereich (RB) von der ersten Oberfläche (7', 27') in vertikaler Richtung in den Halbleiterkörper (1) hinein einen abnehmenden Gradienten aufweist.Conduction type in the edge region (RB) from the first surface (7 ', 27') in the vertical direction into the semiconductor body (1) has a decreasing gradient.
6. Leistungshalbleiterbauelement nach einem oder mehreren der vorstehenden Ansprüchen, dadurch gekennzeichnet, daß die Dotierungskonzentration der Ladungsträger des ersten Leitungstyps im Randbereich (RB) in der Feldstopzone (11, 32) in lateraler Richtung zum Rand des Halbleiterkörpers (1) hin einen abnehmenden Gradienten aufweist.6. Power semiconductor component according to one or more of the preceding claims, characterized in that the doping concentration of the charge carriers of the first conductivity type in the edge region (RB) in the field stop zone (11, 32) has a decreasing gradient in the lateral direction towards the edge of the semiconductor body (1) .
7. Leistungshalbleiterbauelement nach einem oder mehreren der vorstehenden Ansprüchen, dadurch gekennzeichnet, daß die erste Zone (8) als zusätzliche Feldstopzone ausgebil- det ist, Ladungsträger des ersten Leitungstyps aufweist und an der ersten Oberfläche (7, 7 ) an eine erste Elektrode (9) angeschlossen ist und daß die zweite Zone (3) an der zweiten Oberfläche (5) an eine zweite Elektrode (6) angeschlossen ist.7. Power semiconductor component according to one or more of the preceding claims, characterized in that the first zone (8) is designed as an additional field stop zone, has charge carriers of the first conductivity type and on the first surface (7, 7) to a first electrode (9 ) is connected and that the second zone (3) on the second surface (5) is connected to a second electrode (6).
8. Leistungshalbleiterbauelement nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß die erste Zone (26) Ladungsträger des zweiten Leitungstyps aufweist und an der ersten Oberfläche (27, 27 ) an eine erste Elektrode (28) angeschlossen ist und daß die zweite Zo- ne (22) über eine dritte Zone (23) des ersten Leitungstyps an der zweiten Oberfläche (25) an eine zweite Elektrode (24) angeschlossen ist.8. Power semiconductor component according to one of claims 1 to 6, characterized in that the first zone (26) has charge carriers of the second conductivity type and is connected to a first electrode (28) on the first surface (27, 27) and in that the second zone (22) via a third zone (23 ) of the first conductivity type is connected to a second electrode (24) on the second surface (25).
9. Leistungshalbleiterbauelement nach Anspruch 8, dadurch gekennzeichnet, daß eine als zusätzlich Feldstopzone ausgebildete Pufferschicht (29) vorgesehen ist, die die Innenzone (20) und die erste Zone (26) voneinander beabstandet.9. Power semiconductor component according to claim 8, characterized in that a buffer layer (29) formed as an additional field stop zone is provided, which spaces the inner zone (20) and the first zone (26) from one another.
10. Leistungshalbleiterbauelement nach einem oder mehreren der vorstehenden Ansprüchen, dadurch gekennzeichnet, daß zumindest auf den im Randbereich (RB) vorgesehenen Bereichen der ersten Oberfläche (7', 27') eine elektroaktive Pas- sivierungsschicht vorgesehen ist.10. Power semiconductor component according to one or more of the preceding claims, characterized in that an electroactive passivation layer is provided at least on the regions of the first surface (7 ', 27') provided in the edge region (RB).
11. Als pin-Diode ausgebildetes Leistungshalbleiterbauelement nach einem oder mehreren der vorstehenden Ansprüchen.11. A power semiconductor component designed as a pin diode according to one or more of the preceding claims.
12. Als GTO oder IGBT ausgebildetes Leistungshalbleiterbauelement nach einem oder mehreren der vorstehenden Ansprüchen. 12. Power semiconductor component designed as a GTO or IGBT according to one or more of the preceding claims.
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