DE102005029263B4 - Semiconductor device with improved dynamic load capacity - Google Patents

Abstract

Semiconductor component having a semiconductor body (100) with a pn junction (PN1), having a first side (S1) and an opposing second side (S2), a first contact (K1) on the first side and a second contact ( K2) on the second side, wherein the semiconductor component is formed as a diode and has the following features:
an edge termination (RA) disposed at a first region (B1) of the first side (S1) extending from an edge (RS) of the first side (S1) at least to a pn junction (PN1), and wherein a second area (B2) comprises a remaining area of the first side (S1);
a first semiconductor region (110) of a first conductivity type disposed on and electrically connected to the second contact (K2);
a second semiconductor region (120) of the first conductivity type disposed on the first semiconductor region (110) and forming a field stop;
a plurality of semiconductor islands (125) that are used as semiconductor regions of a ...

Description

The present invention relates to a semiconductor device, such as. B. for freewheeling diodes.

In the field of power semiconductor technology, efforts are being made to provide semiconductor components with protective mechanisms so that destruction of the semiconductor components can be prevented even under extreme conditions.

Such extreme conditions can occur, inter alia, in the commutation of power semiconductor diodes. During the commutation process, for example, high electric fields are present at the n ^- n junction of a pn ^- n semiconductor diode, which leads to an avalanche-like charge carrier generation at the n ^-to- n junction. At the same time occur at a pn ^- n on semiconductor diode high electrical field strengths to avalanche-like carrier generation at the pn ^{- -} junction of the pn junction lead. The abrupt, avalanche-like generation of charge carriers, the so-called avalanche effect or avalanche effect, has the effect that a high electric field necessary for the blocking capability of the semiconductor diode can no longer be maintained in an n ^- doped middle region of the semiconductor diode. The semiconductor diode thus loses its blocking capability and is destroyed unless external measures have been taken to limit the current and power.

In order to avoid destruction of the semiconductor diode, the Abkommutiervorgang the diode must be done so far sufficiently slow. If such semiconductor diodes were used within IGBT semiconductor modules, however, an increase in the turn-on losses of the IGBTs had to be accepted.

Another way to prevent the destruction of the semiconductor diode, is to increase the chip thickness of the semiconductor diode or to reduce the amount of flooding charge at the anode and at the same time to increase the flood charge at the cathode. Such measures, however, entail increased forward losses or switching losses.

In the case of IGBT semiconductor components, in particular field-stop IGBT and PT-IGBT (PT = punch through), extreme conditions occur, in particular, when switching off high currents and in the event of short circuits. When switching off high currents, care must be taken to ensure that corresponding current drops within the IGBT are not too steep, which is the case in particular when there is no or insufficient flooding charge in the back of the IGBT for a required blocking voltage and, as a result, the load current breaks off. Due to the strong electron flow through the IGBT-induced channel, the state of the short circuit causes the highest electric field strength within the IGBT not at the pn junctions near the front but at a nn ⁺ backside to the field stop layer, which also acts as a buffer layer is called out occurs. This can in turn lead to an avalanche-like generation of charge carriers at the nn ⁺ junction, which leads to a reduction of the electric field strength within the IGBT and thus to a loss of the blocking capability of the component. In both cases, the IGBT can be destroyed.

In the case of IGBTs with a "leaking" field stop, the electric field extends, for example, in an n-mid region until shortly before the n-field stop. The barrier properties and in particular the dynamic properties of such an IGBT are very much dependent on an exact adjustment of the basic doping or a matching of the doping of the individual layers and their layer thicknesses to one another. This is difficult because typically the base material doping can vary by as much as +/- 15%.

In principle, the problems described above can not occur in the case of NPT-IGBT (NPT = non-punchthrough) since a sufficiently thick neutral zone or no field stop layer is present in these semiconductor components. Since the electric field within the NPT-IGBT hardly ever forms in the entire semiconductor volume due to the increased thickness of the semiconductor device, a sufficient amount of charge carriers is always available for a current transport during a power-down process, so that the load current can not break off. In the event of short circuits, a higher electron current density leads to a flatter gradient of the electric field and thus to an approximation of the space charge zone to the p-doped rear side emitter, for example, which injects more holes into the semiconductor component. This additional positive charge in turn leads to a splitting of the electric field and thus to the stabilization of the same. Thus, the blocking capability of the IGBT can be maintained.

However, a disadvantage of NPT-IGBT is its increased chip thickness compared to field stop or PT-IGBT, which correspondingly increases switching and forward losses. It has therefore been attempted to interrupt the field stop layer or to design island-shaped and / or low doping. This in turn has the disadvantage that a compromise between the static blocking capability of the semiconductor device and the softness or short circuit resistance must be found. Although it is possible by increasing the doping of the back emitter, the softness or short circuit resistance of Semiconductor device to improve. However, this leads to a strong carrier flooding even under normal conditions, which is undesirable, as this results in increased switching losses.

The non-prepublished patent application DE 103 61 136.3 describes an approach in which p-islands are inserted in an active region of a power transistor or an IGBT on the rear side in a mid-field area or a field stop, which emit charge carriers in certain operating states and thus counteract the effects described above, in particular the avalanche effects.

3 , the the 1 the unpublished patent application DE 103 61 136.3 corresponds, shows a semiconductor diode 1 that is an anode 2 , a cathode 3 , a first semiconductor layer 4 , a second semiconductor layer 5 and a third semiconductor layer 6 wherein the first semiconductor layer 4 n ⁺ -doped, the second semiconductor layer n ^- doped and the third semiconductor layer 6 p-doped, and the associated electrical equivalent circuit diagram. The first, second and third semiconductor layers 4 . 5 and 6 together form a semiconductor volume 7 that between the anode 2 and the cathode 3 is provided. Within the second semiconductor layer 5 are several p-doped semiconductor zones 81 to 84 provided, which have a rectangular cross section and are equidistant from each other. The semiconductor zones 81 to 84 are arranged at the same vertical height, wherein the respective lower sides directly to the first semiconductor layer 4 adjoin. The transition between the semiconductor layer 4 and the semiconductor zones 81 to 84 or with the semiconductor layer 5 is with J3, the transition between the semiconductor zones 81 to 84 and the second semiconductor layer 5 is with J2 and the junction between the second and the third semiconductor layer 5 . 6 denoted by J1.

When the semiconductor diode is switched to the blocking state, J2 in the forward direction, J1 and J3 in the reverse direction are poled. If there is a dynamic avalanche at the main transition J1, then J3 is also in the state of the avalanche. During this state, there is still a charge carrier mountain in the middle zone of the diode. J2 now injects the holes created in the avalanche of J3 into the charge carrier mountain. This prevents the charge carrier mountain from detaching from the junction J3. The injected holes compensate for the electrons coming from junction J1 through dynamic avalanche. Thus, it is not possible for a space charge zone carried by the free electrons between the charge carrier mountain and the n ⁺ region, ie the first semiconductor layer 4 , build up.

The through the semiconductor zones 81 to 84 formed p-zone is interrupted, which can be described by a resistor R. For a continuous p-zone, junction J2 would be off if the diode were to be forward biased. The resistor R small currents in the forward direction of a shunt. At typical operating currents, the PNPN structure is turned on, that is, turned on and flooded with charge carriers. The resistance R should not be too small: When commutating a voltage must be built up at the junction J3, which leads to an avalanche.

An essential aspect of the approach described is to improve the commutation resistance in a high-voltage diode structure by a stabilizing dynamic avalanche at a pn junction at the cathode during switching. The illustrated semiconductor diode effects a stabilization of the electric field by means of the dynamic avalanche and thus makes it possible to avoid destructive electric fields at an nn ⁺ junction, without the semiconductor diode having such a large central zone thickness that a dynamic avalanche is present at a pn junction of the semiconductor diode is terminated before an electric field can form at the nn ⁺ junction.

A disadvantage of the approach described above is the significant reduction of the static blocking voltage and thus the resulting blocking capability of the component associated with the p-type conductor zones or p-islands. Furthermore, the p-islands generate high carrier densities even in the edge of the semiconductor device. However, high carrier densities in the edge are undesirable because typically necessary edge terminations of semiconductor components are dimensioned on the static dopants and the additional carriers lead to higher loads, in particular in the edge regions of the semiconductor component. The high carrier densities or high current densities in the edge can lead to premature destruction of the semiconductor device.

The US Pat. No. 6,239,466 B1 describes an IGBT (Insulated Gate Bipolar Transistor) optimized for zero voltage switching (ZVS). The IGBT operates as a MOSFET with a very small bipolar transistor component. Circuit losses are reduced by reducing the number of minority carriers injected into the device during the conduction phase. For this purpose, the IGBT, for example, buried p ⁺ layers (diverter) in a buffer layer (buffer layer) on.

The DE 697 21 366 T2 describes a diode having a front-side anode electrode and a rear-side cathode electrode, wherein an n ⁺ -doped semiconductor layer is arranged on the cathode electrode, on which in turn an n ^- drift zone is arranged. In an active region, a p ⁺ -doped semiconductor layer is arranged below the anode electrode above the drift zone, and in a connection region arranged adjacent to the active region a p ⁺ -doped semiconductor layer which is arranged under a further electrode. The n ⁺ -doped semiconductor layer arranged on the cathode electrode has p ⁺ -doped semiconductor layers in the active region, which extend from the cathode electrode through the n ⁺ -doped semiconductor layer into the drift zone.

The object of the present invention is to provide a semiconductor device with improved dynamic load capacity, which simultaneously has the highest possible static blocking capability.

This object is achieved by a semiconductor device according to claim 1.

The present invention is based on the finding that a dynamic loading of an edge region or an edge termination of a semiconductor component can be reduced in that the current flow takes place by means of appropriate measures substantially in an inner region of the semiconductor component. This is achieved by the fact that the spatial arrangement of the semiconductor islands and the dimensioning of the semiconductor islands, that is, substantially their doping, width and depth, is selected such that the breakdown voltage is lowered in an inner region of the component or under the second region in that the breakdown during operation of the semiconductor component takes place securely in an inner region and not in an edge region of the component or under the first region. This allows a so-called "self-clamping" function or self-limiting function, which leads to a higher dynamic load capacity of the semiconductor device. The essential feature of the present invention is therefore that the semiconductor islands are arranged only under the second region or in the inner region, but not under the first region or in an edge region of the component. This reduces the current flow under a first region, but in particular at the edges or saw edges themselves, and thus also considerably reduces the risk of premature destruction of the semiconductor component. At the same time thereby the static reverse voltage of the semiconductor device compared to a semiconductor device according to the not previously published DE 103 61 136.3 elevated.

A further advantage of the present invention is that the lowering of the breakdown voltage below the second region is effected by measures which only affect the depth of the semiconductor device and not in the vicinity of a surface, so that also a sufficient long-term stability of this function is given ,

In contrast to "leaky" field stops in IGBT, which also do not require loading on surfaces of the semiconductor device, the present invention is not strongly dependent on base material doping, which typically can vary as shown above by as much as +/- 15% and the influence of a thickness of, for example, an n ^- region or an n ^- middle region is likewise greatly reduced.

Semiconductor components according to the invention can have both n-type doping and p-type doping as the first conductivity type, with the p-type doping or n-type doping accordingly corresponding to the second conductivity type. In a preferred embodiment according to the invention, the first conductivity type has an n-type doping and the second conductivity type has a p-type doping.

In preferred embodiments of the invention, the edge termination has a field plate structure. This Feldplattenrandabschluss consists of at least one structured insulator layer and at least one structured field plate, wherein the insulator layer or layers on the first region of the first side and the field plate or field plates are electrically conductive and disposed on the insulator layer or the insulator layers. Frequently, field plates are guided stepwise over a plurality of insulator layers, so that one side of the field plate is significantly further away from the surface of the semiconductor.

An embodiment of the present invention is formed as a diode, wherein the diode has a first semiconductor region of the first conductivity type disposed on and electrically connected to the second contact, a second semiconductor region of the first conductivity type disposed on the first semiconductor region forming the field stop and the semiconductor islands comprises a third semiconductor region of the first conductivity type arranged on the second semiconductor region, wherein the second semiconductor region is more heavily doped than the third semiconductor region and the first semiconductor region is more heavily doped than the second semiconductor region, a fourth semiconductor region of the second conductive type, which is adjacent to the third semiconductor region and is electrically connected to the first contact.

The semiconductor islands are preferably island-shaped, that is, configured as a plurality of smaller regions, rectangular, round or in any other desired shapes and, in order to achieve a regular electric field strength structure, advantageously arranged equidistant from each other. The semiconductor islands are preferably configured identically in their dimensions. However, the invention is not limited to these embodiments.

Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. Show it:

1 a schematic cross section of an exemplary diode according to the invention;

2 a schematic cross section of an exemplary IGBT; and

3 a schematic cross section of a possible diode.

1 shows a schematic cross section of a diode according to an embodiment of the present invention, with reference to 1 the principle of the present invention will be explained.

The semiconductor component has a semiconductor body 100 with a pn junction PN1, with a first side S1, a second side S2 arranged opposite, a first contact K1 on the first side and a second contact K2 on the second side S2, and an edge termination RA on a first region B1 of the first side S1 and extending from an edge RS1 of the first side S1 at least to a pn junction PN1 of the semiconductor device, wherein a second region B2 comprises a remaining region of the first side S1. Thus, an edge region is defined by the first region B1, which defines the volume of the semiconductor body 100 relative to the orientation of the 1 below the first region B1 or perpendicularly between the first region B1 and the second side S2, and furthermore, an inner region, which defines the volume of the semiconductor body, is defined by the second region B2 100 relative to the orientation of the 1 below the second region B2 or perpendicular between the second region B2 and the second side S2. The edge region and the inner region together comprise the entire semiconductor body. The edge termination RA is defined by a field plate RAF and an insulator RAI, for example an insulator RAI arranged between the first side S1 and the field plate RAF. As an oxide formed.

The semiconductor body 100 has a plurality of semiconductor regions of a first conductivity type or a second conductivity type, wherein a first semiconductor region 110 of the first conductivity type is arranged on the second contact K2 and is electrically connected to the same, a second semiconductor region 120 of the first conductivity type on the first semiconductor region 110 is arranged, wherein the second semiconductor region 120 the field stop forms and semiconductor islands 125 of the second conductivity type, a third semiconductor region 130 of the first conductivity type on the second semiconductor region 120 is arranged, wherein the second semiconductor region 120 is more heavily doped than the third semiconductor region 130 and the first semiconductor region 110 is more heavily doped than the second semiconductor region 120 , and a fourth semiconductor region 140 of the second conductivity type is electrically connected to the first contact K1, wherein the fourth semiconductor region 140 to the third semiconductor region 130 borders. Accordingly, the semiconductor body 100 a first junction I1 between the fourth semiconductor region 140 and the third semiconductor region 130 , which forms in this embodiment, the PN junction PN1, a second junction I2 between the third semiconductor region 130 and the second semiconductor region 120 and a third junction I3 between the second semiconductor region 120 and the first semiconductor region 110 on. The fourth semiconductor area 140 is, for example, trough-shaped in the third semiconductor region 130 brought in. The semiconductor islands 125 are arranged at the same vertical height, wherein the undersides of the semiconductor islands 125 directly to the first semiconductor region 110 adjoin. Side surfaces SF connect the first side S1 to the second side S2. Since the side surfaces SF usually arise through dicing in the singling of the individual semiconductor components, these side surfaces SF or "sawing edges" have massive crystal defects.

In general, the rule of thumb is that 1/10 of the blocking voltage of a semiconductor diode (calculated in volts) should correspond to a thickness of the semiconductor diode (calculated in μm). In the in 1 described embodiment, the semiconductor body consists of four semiconductor regions, is analogous to the distance w between the semiconductor islands 125 and the fourth semiconductor region 140 for example, for a semiconductor device having a reverse voltage greater than 2 kV, preferably greater than 200 microns.

In a diode according to the invention according to 1 is a thickness b of the first semiconductor region 110 for example, 0.2 to 12 microns, the thickness a of the semiconductor islands 125 3 to 20 microns, the width d of the semiconductor islands 125 each 2 to 200 microns, the distance c between the semiconductor islands 125 and the second junction I2 10 to 25 microns, the distance e between the individual semiconductor islands 125 5 to 200 μμm and the distance w between the semiconductor islands 125 and the fourth semiconductor region 140 more than 200 microns, preferably between 200 microns and 800 microns.

In a preferred embodiment according to 1 the first conductivity type has one n-doping and the second conductivity type on a p-type doping, so that the first contact K1 forms the anode contact and the second contact K2 the cathode contact. Furthermore, then, for example, the first semiconductor region 110 n ⁺ doped, the second semiconductor region 120 n-doped, the third semiconductor region 130 n ^- doped and the fourth semiconductor region 140 as well as the semiconductor islands 125 p-doped, wherein the p-type doping of the semiconductor islands 125 is in a maximum range of 1E15 to 5E15 cm ^-3 and the n-type doping of the second semiconductor region 120 or the field stop is in a range of 5E14 to 5E15 cm ^-3 .

The exemplary diode is thus, as previously described by the rule of thumb, designed for a voltage of 2,000 volts to 8,000 volts. However, the invention is not limited to these ranges of values. The above-mentioned values depend on the desired voltage class of the semiconductor component, as is already explained above, see rule of thumb, and are therefore not to be understood as a limitation, but merely as an example.

With suitable dimensioning of the proportion of the surfaces of the semiconductor islands 125 , hereinafter referred to as the semiconductor island area, the size of the individual semiconductor islands 125 and their distances from each other and from the second contact K2, a flooding of the semiconductor device with charge carriers can also be spatially differently modulated. The larger the proportion of semiconductor island area, the lower the charge carrier density of the flooding charge in the upstream third semiconductor region. As a result, the breakdown or forward voltage and the switching losses can be selectively reduced.

The second semiconductor area 120 serves as a field stop or buffer for the expansion of the space charge zone through which the stage can be moved in the reverse current waveform to higher voltages. Furthermore, the second semiconductor region or the field stop also reduces the blocking capability of the second junction I2, so that the switching on of the diode is facilitated. According to the invention, they extend into the second semiconductor region 120 integrated semiconductor islands 125 not up to the second contact K2. Such a design would result in a very late and abrupt onset of injection of, for example, holes in p-doped semiconductor islands. A dimensioning of the doping regions in order to effect equally soft switching behavior or the prevention of high field strengths at the third junction I3 would not be possible. The required dynamic properties with respect to the different occurring in practical Vorstromdichten and DC link voltages could not be met, because either has the diode at low current densities and / or high voltages no longer sufficient blocking capability, or at high current densities and / or low voltage is no injection from holes more.

2 shows an exemplary, schematic cross section of an IGBT, wherein the IGBT a semiconductor body 200 with a pn junction PN1 ', with a first side S1' and an opposing second side S2 ', a first contact K1' on the first side S1 'and a second contact K2' on the second side S2 ', an edge termination RA ', which is arranged on a first region B1' of the first side S1 ', which extends from an edge RS1' of the first side S1 'at least to the pn junction PN1', wherein a second region B2 'a remaining region of first side S1 'includes. Thus, an edge region is defined by the first region B1 ', which defines the volume of the semiconductor body 200 relative to the orientation of the 2 below the first region B1 'or perpendicularly between the first region B1' and the second side S2 ', and furthermore, an inner region, which defines the volume of the semiconductor body, is defined by the second region B2' 200 relative to the orientation of the 2 under the second region B2 'or perpendicularly between the second region B2' and the second side S2 '. The edge region and the inner region together comprise the entire semiconductor body. The edge termination RA 'is defined by a field plate RAF' and an insulator RAI ', for example an insulator RAI' arranged between the first side S1 'and the field plate RAF'. As an oxide formed.

The semiconductor body 200 has a plurality of semiconductor regions of a first conductivity type or a second conductivity type, wherein the first semiconductor region 210 of the second conductivity type is arranged on the second contact K2 'and is electrically connected thereto, a second semiconductor region 220 of the first conductivity type, on the first semiconductor region 210 is arranged, wherein the second semiconductor region 220 the field stop forms and semiconductor islands 225 of the second conductivity type, a third semiconductor region 230 of the first conductivity type, on the second semiconductor region 220 is arranged, a fourth semiconductor region 240 of the second conductivity type to the third semiconductor region 230 adjoins and over an isolation area 260 with a third contact K3 'on the first side S1' of the semiconductor body 200 is arranged, a fifth semiconductor region is coupled 250 of the first conductivity type to the fourth semiconductor region 240 adjacent and electrically connected to the first contact K1 '. These are the semiconductor islands 225 completely in the second semiconductor region 220 , so the field stop, embedded and the second semiconductor region 220 is more heavily doped than the third Semiconductor region 230 and the fifth semiconductor region 250 is more heavily doped than the second semiconductor region 220 , Furthermore, the IGBT has a first junction I1 'between the fourth semiconductor region 240 and the third semiconductor region 230 on, a second junction I2 'between the third semiconductor region 230 and the second semiconductor region 220 , a third junction I3 'between the second semiconductor region 220 and the first semiconductor region 210 and a fourth junction I4 'between the fifth semiconductor region 250 and the fourth semiconductor region 240 , wherein the first junction I1 'forms the PN junction PN1'. Side surfaces SF 'connect the first side S1' to the second side S2 '. Since the side surfaces SF 'arise mostly by dicing the individual semiconductor components, these side surfaces SF or "saw edges" have massive crystal defects. The isolation area 260 has, for example, an oxide.

In examples, the thickness a 'of the semiconductor islands is 225 in a range of 0.5 to 20 μm, the width d 'of the semiconductor islands 225 in a range of 2 to 200 μm, the distance e 'of the individual semiconductor islands 225 to each other in a range of 5 to 200 microns, the distance c 'between the third semiconductor region 230 and the semiconductor islands 225 in a range of 10 to 25 μm and the distance w 'between the fourth semiconductor region 240 and the semiconductor islands 225 in a range over 200 microns.

In the case of an IGBT, the first conductivity type can have both an n-doping and a p-doping, in which case the second conductivity type accordingly has a p-type doping or n-type doping. By way of example, the first conductivity type has an n-type doping and the second conductivity type has a p-type doping. Thus, the first contact K1 'forms the emitter, the second contact K2' forms the collector, the third contact K3 forms the gate and the first semiconductor region 210 the p-back emitter, in which case, for example, the first semiconductor region 210 a p-type doping, the second semiconductor region 220 or the field stop an n-doping, the semiconductor islands 225 a p-type doping, the third semiconductor region 230 an n ^- doping, the fourth semiconductor region 240 a p-type doping and the fifth semiconductor region 250 have an n ⁺ doping. This is a p-doping of the semiconductor islands 225 at most in a range of 1E15 to 1E18 cm ^-3 , for example in a range of 1E16 to 5E16 cm ^-3 , while n-doping of the field stop and the second semiconductor region 220 in the vertical direction has an integral dopant dose in a range of 2E11 to 2E12 cm ^-2 . Furthermore, a portion of the fourth semiconductor region 240 which is associated with the first contact, and in 2 between two perpendicular to the side S1 'related electrodes 270 of the third contact K3 'is arranged in a first partial area 241 , a second subarea 242 and a third subarea 243 be divided, with the first subarea 241 which is directly connected to the first contact K1 ', has a higher doping than the second portion 242 , The third section 243 can without direct electrical connection to the contact K1 'or to the subregions 241 and 242 be executed. In the previously described p-doping of the fourth semiconductor region 240 indicates the first subarea 241 thus, for example, a p ⁺ doping, the second subarea 242 a p-type doping and the third subrange 243 a p or p ⁺ doping on.

Even though 2 1 shows an IGBT in trench structure, a semiconductor component can also be embodied in a planar structure, that is to say as a planar IGBT.

By way of example, a semiconductor component can be technologically constructed in such a way that an active region is introduced in a trough shape into another or into a semiconductor substrate, as shown by way of example in FIG 1 is shown, in which the fourth semiconductor region 140 trough-shaped in the third semiconductor region 130 is arranged. Depending on reverse voltage occur at the transitions of the active areas, in 1 For example, transition I1, high field strengths, which can lead to an undesirable breakdown of the device even at low voltages. This results in the edges and bends particularly high field strengths, as is known from the high voltage technology as edge or peak effect. Furthermore, the charge carriers (holes) flowing during a switching operation can considerably influence the field distribution since they act as an effective increase of the basic doping. The blocking capability in the silicon can then be lower than in the stationary case for a short time, ie the virtually currentless case, so that the robustness of the semiconductor element is limited by the edge structure or its limit load capacity is determined thereby. Inside and outside the silicon, significantly higher field strengths than in the stationary case can occur (dynamic effects), so that breakthroughs or long-term damage of oxide or passivation layers such as imide are possible.

The structures which are arranged on the first side S1 in order to achieve the highest possible breakdown voltage in static blocking operation are termed edge terminations in semiconductor components. An important optimization criterion for edge seals is a robust behavior in the case of high dynamic load during switching operations.

One possibility of implementation is the use of field plates, as they were based on the previous embodiments. These are based, for example, on 1 above of the semiconductor body or the first side S1 on an oxide layer and are electrically connected to the active region, for example the contact K1. The edge effect of the blocking pn junction I1 is effectively reduced by the field plate and the places of highest electric field strength from the semiconductor region shifted into the oxide layer, which withstands a much higher field load. For example, the field plate may be electrically connected to the gate, source, or emitter. In this case, edge seals are not only used in well structures of active areas, but also on saw edges, which are formed for example by dicing, to avoid that space charge zones reach to these saw edges, or to eliminate parasitic effects. It is important that the edge terminations have a high breakdown voltage that is as close to or higher than the breakdown voltage in the cell field or interior, and have a low sensitivity to surface charges, so that a long-term stability is ensured.

Although it has been assumed in the exemplary embodiments of an edge termination with field plate structure, semiconductor components according to the invention may also have other edge termination structures, some of which will be briefly explained below by way of example. In the so-called "metal ring structure", similarly to the field plate structure, a conductor is disposed above the first region, and an insulator electrically separates the metal ring from the first region. However, unlike the field plate structure, the metal ring of the metal ring structure is not electrically connected to an active region. The approach of the structure with "resistance layer" is based on being transferred to 1 , the fourth semiconductor area 140 via a resistive layer disposed over and electrically separated from the first region B1 by an insulator having an additional semiconductor region disposed at the edge RS1 and the same conductivity type as the third semiconductor region 130 has, but is heavily doped, is connected. The "field ring structure" has additional semiconductor regions at the first region that have the same conductivity type as the fourth semiconductor region 140 and also have a comparable doping strength. The Junction Termination Extension (JTE) structure has an additional semiconductor region at a first region B1, which has the same conductivity type as the fourth semiconductor region 140 but with a weaker doping, this additional semiconductor region extending beyond the first pn junction. The "RESURF structure" has two additional semiconductor regions, wherein the first additional semiconductor region is arranged on the side edge RS1, the same conductor carrier type as the third semiconductor region 130 but having a stronger doping, and wherein the second additional semiconductor region in the first region B1 adjoins the first additional semiconductor region, the fourth semiconductor region 140 surrounds the same conductivity type as the fourth semiconductor region 140 but is less heavily doped. All of the mentioned edge termination structures cause the space charge zone to expand, thereby preventing break-through at the termination of the junction at the surface of the semiconductor. In addition, combinations of field plates with field rings are known and possible.

As can be seen from the exemplified alternative edge termination structures, the edge termination RA can therefore be designed such that it is arranged, for example, in the first area B1. But he does not have to cover the entire first area B1. Furthermore, it may have interruptions and / or extend over a pn junction. In any case, however, the edge termination (RA, RA ') is also located at a region extending from the edge (RS1, RS1') to the first pn junction (PN1, PN1 ') adjacent to the side the edge termination (RA, RA ') is formed, see 1 and 2 ,

In summary, therefore, it can be said that when switching off IGBTs or the commutation of diodes, the voltage across the semiconductor device increases more than the DC link voltage due to the always present leakage inductances. In semiconductor devices whose first conductivity type has, for example, an n-type doping, the flowing holes in the space charge zone simultaneously reduce the dynamic blocking capability of the component. As a result, the maximum electric field strength in the semiconductor component increases and avalanche occurs more frequently. If the semiconductor device is driven without current flow in the avalanche, the effects described below also become apparent. With strong avalanche generation, however, the maximum voltage that can be blocked by the component decreases. The reason for this is the proportion of the electrons in the avalanche generation in the high-field regions close to the blocking pn junction. The field bending caused by the charge carriers generated here reduces the integral Edx (integral of the field strength E across the thickness) and thus the blocking capability of the semiconductor device. Now also a back nn ⁺ transition, z. B. at a field stop of a first conductivity type, which has an n-type doping, exposed because the flooding charge is sufficiently eliminated, so a high electron current density in this area also leads to a field peak.

These nn ⁺ transitions do not have edge termination, which is why an occurrence of the field can extend to the saw edge of the chip with its massive crystal defects. Moreover, if the field peak reaches a height such that avalanche also occurs at this nn ⁺ junction, then the component is destroyed with high probability because the field strength distribution and thus the blocking capability collapse.

So far, these operating cases could only be avoided by the DC link voltage or leakage inductance or the switching speeds and thus the avalanche load reduced or, in the case of diodes, the commutation were more limited. These measures in each case reduced the exploitation of the components and were therefore disadvantageous. For example, typically in a semiconductor device having a nominal blocking voltage of 1200 volts, the intermediate circuit voltage is limited to 600 to 800 V to maintain a 400 to 600 volt reserve for overvoltage spikes in switching due to the problem described above.

A diode according to the invention or an exemplary IGBT therefore provides, in an active region on the rear side or the second side S2, S2 ', however, spaced from the second contact K2, K2', in a n-doped field stop, for example, p-doped semiconductor islands 125 . 225 which emit charge carriers in certain operating states and thus counteract the effects described above. Unlike the unpublished patent application DE 10361136.3 stay the semiconductor islands 125 under the edge termination RA, RA 'and the region of the gate connection contact in IGBTs, which is also referred to as gate pad, recessed as the semiconductor islands 125 . 225 associated with a reduction of the static blocking voltage. The gate connection contacts or according to 2 more generally, the terminal contacts of the electrodes formulate 270 which are electrically connected to the third contact K3 'are in 2 not shown. As a result, the resulting blocking capability of the component is less influenced or less reduced. In addition, it is undesirable, as described above, to find high carrier densities in the edge of a semiconductor component, because the edge terminations are dimensioned to the static dopants and the additional carrier would lead to higher loads. Therefore, the spatial arrangement and the dimensioning of the semiconductor islands 125 . 225 , that is, their doping, width and depth, chosen so that the breakdown voltage in the inner region of the device or under the second region B2, B2 'is lowered so that the breakthrough in the operation of the semiconductor device safely in this large-scale interior or takes place under the second region B2, B2 'and not in an edge region of the semiconductor component or under the first region B1, B1'. This allows a so-called "self-clamping" function, that is, the semiconductor device limits the voltage automatically to allowable values, which in turn leads to a higher dynamic load capacity of the device. Furthermore, the use of the diodes according to the invention is thus considerably facilitated since the expense for corresponding protective circuits, as required in the prior art, can be considerably reduced.

An advantage of the invention is thus a lowering of the dynamic blocking capability or blocking voltage in a central region or under the second region B2 of the semiconductor component, whereby in combination with the measures described in the above-mentioned invention disclosure by means of a design measure a so-called "self-clamping". Function is enabled.

LIST OF REFERENCE NUMBERS

1

Semiconductor diode

2

anode

3

cathode

4

first semiconductor layer

5

second semiconductor layer

6

third semiconductor layer

7

Semiconductor volume

8 ₁ to 8 ₄

Semiconductor zones

J1

crossing

J2

crossing

J3

crossing

100

Semiconductor body

PN1

pn junction

S1

first page

S2

second page

K1

first contact

K2

second contact

RA

edge termination

B1

first area

B2

second area

110

first semiconductor area

120

second semiconductor region

130

third semiconductor region

140

fourth semiconductor region

RS1

Edge of the first page

RAF

field plate

RAI

Isolator of the edge termination

I1

first transition between the fourth semiconductor region and the third semiconductor region

I2

second junction between the third semiconductor region and the second semiconductor region

I3

third junction between the second semiconductor region and the first semiconductor region

SF

side surface

a

Thickness of the semiconductor islands

b

Thickness of the first semiconductor region

c

Distance of the semiconductor islands to 2.tem transition

d

Width of the semiconductor islands

e

Distance between the semiconductor islands

w

Distance between the semiconductor islands and the fourth semiconductor region

200

Semiconductor body

PN1 '

pn junction

S1 '

first page

S2 '

second page

K1 '

first contact

K2 '

second contact

RA

edge termination

RS1 '

Edge of the first page

B1 '

first area

B2 '

second area

B3 '

third area

B4 '

fourth area

210

first semiconductor area

220

second semiconductor region

230

third semiconductor region

240

fourth semiconductor region

250

fifth semiconductor area

260

Quarantine

SF '

side surface

241

first subarea

242

second subarea

243

third subarea

RAF '

field plate

RAI '

Isolator of the edge termination

270

electrode

a '

Thickness of the semiconductor islands

c '

Distance of the semiconductor islands to the second transition

d '

Width of the semiconductor islands

e '

Distance between the semiconductor islands

w '

Distance between the semiconductor islands and the fourth semiconductor region

I1 '

first transition between the fourth semiconductor region and the third semiconductor region

I2 '

second junction between the third semiconductor region and the second semiconductor region

I3 '

third junction between the second semiconductor region and the first semiconductor region

I4 '

fourth transition between the fifth semiconductor region and the fourth semiconductor region

Claims (12)

Semiconductor device comprising a semiconductor body ( 100 ) having a pn junction (PN1), having a first side (S1) and an opposing second side (S2), a first contact (K1) on the first side, and a second contact (K2) on the second side, wherein the semiconductor device is formed as a diode and has the following features: an edge termination (RA), which is arranged on a first region (B1) of the first side (S1) extending from an edge (RS) of the first side (S1) at least extending to a pn junction (PN1), and wherein a second region (B2) comprises a remaining region of the first side (S1); a first semiconductor region ( 110 ) of a first conductivity type disposed on and electrically connected to the second contact (K2); a second semiconductor region ( 120 ) of the first conductivity type, which on the first semiconductor region ( 110 ) is arranged and forms a field stop; a plurality of semiconductor islands ( 125 ) disposed as semiconductor regions of a second conductivity type inverse to the first conductivity type in the second semiconductor region such that they are disposed only below the second region (B2, B2 ') and not semiconductor islands ( 125 ) are arranged below the first region (B1), wherein a lower side of the plurality of semiconductor islands ( 125 ) directly to the first semiconductor region ( 110 ) adjoins; a third semiconductor region ( 130 ) of the first conductivity type, which on the second semiconductor region ( 120 ) is arranged; wherein the second semiconductor region ( 120 ) is more heavily doped than the third semiconductor region ( 130 ) and the first semiconductor region ( 110 ) stronger than the second semiconductor region ( 120 ) is doped; and a fourth semiconductor region ( 140 ) of the second conductivity type, which is connected to the third semiconductor region ( 130 ) and is electrically connected to the first contact (K1). Semiconductor element according to claim 1, wherein the first conductivity type has an n-type doping and the second conductivity type has a p-type doping. Semiconductor component according to one of Claims 1 or 2, in which the edge termination (RA) has at least one patterned insulator layer (RAI) and at least one patterned field plate (RAF), the insulator layer (RAI) or the insulator layers on the first area (B1). arranged on the first side (S1) and the field plate (RAF) or field plates are electrically conductive and are arranged on the insulator layer (RAI) or the insulator layers. Semiconductor component according to one of Claims 1 to 3, in which the first semiconductor region ( 110 ) n ⁺ doped, the second semiconductor region ( 120 ) n-doped, the third semiconductor region ( 130 ) n ^- doped, and the fourth semiconductor region ( 140 ) and the semiconductor islands ( 125 ) are p-doped. A semiconductor device according to any one of claims 1 to 4, wherein a thickness a of the semiconductor islands 125 in a range of 3 microns to 20 microns. Semiconductor component according to one of Claims 1 to 5, in which a thickness b of the first semiconductor region ( 110 ) is in a range of 0.2 μm to 12 μm. Semiconductor component according to one of Claims 1 to 6, in which a p-doping of the semiconductor islands ( 125 ) is in a maximum range of 1E15 to 5E15 cm ^-3 . Semiconductor device according to one of claims 1 to 7, wherein an n-doping of the field stop in a range of 5E14 to 5E15 cm ^-3 . Semiconductor component according to one of Claims 1 to 8, in which a distance c between the semiconductor islands ( 125 ) and a junction (I2) between the second semiconductor region ( 120 ) and the third semiconductor region ( 130 ) is in a range of 10 μm to 25 μm. Semiconductor component according to one of Claims 1 to 9, in which a spacing w between the semiconductor islands ( 125 ) and the fourth semiconductor region ( 140 ) is greater than 200 microns. Semiconductor component according to one of claims 1 to 10, wherein a width d of the semiconductor islands ( 125 ) is in a range of 2 μm to 200 μm. Semiconductor component according to one of Claims 1 to 11, in which a distance e between the semiconductor islands ( 125 ) is in a range of 5 μm to 200 μm.

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