EP1062700A1 - Composant a semi-conducteur de puissance a bord mesa - Google Patents

Composant a semi-conducteur de puissance a bord mesa

Info

Publication number
EP1062700A1
EP1062700A1 EP00903516A EP00903516A EP1062700A1 EP 1062700 A1 EP1062700 A1 EP 1062700A1 EP 00903516 A EP00903516 A EP 00903516A EP 00903516 A EP00903516 A EP 00903516A EP 1062700 A1 EP1062700 A1 EP 1062700A1
Authority
EP
European Patent Office
Prior art keywords
zone
power semiconductor
field stop
semiconductor component
component according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00903516A
Other languages
German (de)
English (en)
Inventor
Reiner Barthelmess
Gerhard Schmidt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
EUPEC GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EUPEC GmbH filed Critical EUPEC GmbH
Publication of EP1062700A1 publication Critical patent/EP1062700A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the invention relates to an asymmetrically blocking power semiconductor component with a mesa edge termination.
  • the present invention relates in particular to asymmetrically blocking (ie blocking on one side), high-voltage-resistant power semiconductor components with so-called mesa edge termination, ie. H. with a bevel on the side walls.
  • the invention relates in particular to such power semiconductor components with so-called punch-through dimensioning, i. H. with a field stop zone to reduce the electrical field.
  • Such power semiconductor components can be designed, for example, as pin diodes, GTOs, IGBTs or the like.
  • the emitter zone In order to achieve the highest possible emitter efficiency, the emitter zone must be doped as high as possible. At the same time, however, it is necessary for the space charge zone to run over the longest possible distance on the surface of the window in blocking operation. For the purpose of enlarging the path available for the space charge zone on the wafer surface, the lateral edge of the semiconductor body typically has a positive bevel.
  • a common method for building up additional charges in the edge region or for reducing the field peaks mentioned is the use of electroactive passivation layers made of typically amorphous, hydrogen-containing carbon layers or of amorphous, hydrogen-containing silicon carbide layers.
  • EP 0 400 178 B1 describes a method for electroactive passivation. The advantage of this method is that charges can be actively built up in the amorphous layer mentioned there, which to a certain extent can weaken field strength peaks in a self-adjusting manner.
  • Ins pecial b takes the charge density of surface charges with temperature, so that a sufficient blocking ability can not be ensured, in particular at very low temperatures.
  • field stop zones of the same conductivity type as in the inner zone are provided in the edge area below the areas (etched shoulders) etched out of the semiconductor body.
  • These field stop zones which are typically connected to the inner zone and to the emitter zone, adjoin the polished, damageless surface of the etched-out shoulders.
  • the doping concentration of these field stop zones, which lies between that of the emitter zone and that of the inner zone, is set in such a way that there is a decreasing gradient in the concentration profile of the doping from the surface of the etching shoulders into the depth of the semiconductor body. In this way it can be ensured, even under extreme conditions, that the semiconductor component does not accidentally break down before the predetermined volume breakdown voltage is reached.
  • the course of the doping concentration is set in the edge region in such a way that the breakdown charge results after etching off a minimum thickness which is required to produce a polish-etched, damagefree surface.
  • One is almost independent of the depth or the thickness of the emitter zone.
  • the doping concentration in the field stop zone The depth of the charge carrier measured from the field stop zone and the inner zone below it is approximately equal to the breakthrough charge density, based on the vertical direction.
  • the doping concentration or the amount of charge carriers introduced in the field stop zone can be specifically set or controlled by ion implantation.
  • the etched-out areas on the pane surface do not run ideally horizontally, but fall outward at a flat angle of a few degrees. In this case, a gradient in the doping concentration falling towards the edge can also be generated.
  • the concentration profile of the field stop zone has a flat gradient in the lateral direction towards the edge of the power semiconductor component.
  • corresponding calculations must also be made for the laterally averaged surface charge densities.
  • the invention is particularly suitable for power diodes (pin diodes) with a mesa edge termination, which are used, for example, as free-wheeling diodes of IGBTs and GTOs.
  • the invention is also very advantageous with other, asymmetrical Trically blocking power semiconductor components with mesa edge termination, such as IGBTs, GTOs and the like, applicable.
  • FIG. 1 shows schematically in a partial section a first exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode;
  • FIG. 2 shows schematically in a partial section a second exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode;
  • FIG. 3 schematically, in a partial section, an exemplary embodiment of a power semiconductor component according to the invention designed as a GTO;
  • FIG. 4 schematically, in a partial section, an exemplary embodiment of a power semiconductor component according to the invention designed as an IGBT.
  • FIG. 1 shows schematically in a partial section a first exemplary embodiment of a power semiconductor component according to the invention designed as a pin diode.
  • 1 denotes the semiconductor body of the pin diode.
  • the pin diode has an anode connection A and a cathode connection K, which are arranged on opposite sides of the semiconductor body 1.
  • the semiconductor body 1 which consists for example of silicon substrate, has an inner zone 2 which is weakly n-doped in the present exemplary embodiment.
  • a p-doped anode zone 3 adjoins the inner zone 2 over a large area on the anode side.
  • the anode zone 3 adjoins the anode zone 3 on the rear surface 5 of the semiconductor body 1.
  • the anode zone 3 is here connected to the anode connection A via a large-area anode metallization or anode electrode 6 applied to the surface 5.
  • cathode zone 8 On the cathode side, at least one, in the present case heavily n-doped, cathode zone 8 is embedded in the front surface 7 of the semiconductor body 1.
  • the cathode zone 8 has the same conductivity type, but a much higher doping concentration than the inner zone 2 and thus serves as a field stop zone for the field breakdown of the electric field on the front surface 7.
  • the cathode zone 8 is embedded in the inner zone 2 at this location and trough-shaped may have been introduced into the semiconductor body 1, for example, by ion implantation with an optionally subsequent temperature step or by diffusion.
  • the cathode zone 8 is connected to the cathode connection K on the surface 7 via a cathode metallization or a cathode electrode 9.
  • the region of the pin diode, which is defined by the cathode zone 8, is also referred to as the active region AB of the pin diode.
  • the edge region RB defines essentially the regions of the semiconductor body 1 located outside the active region AB is provided, the area 10 etched out of the semiconductor body 1.
  • an etching shoulder 13 is defined between the cathode zone 8 and the edge area RB.
  • these etching shoulders 12 or the surfaces 7 ′ that are produced as a result of polishing run essentially horizontally. It would of course also be conceivable that these etching shoulders 12 take a slightly inclined course towards the edge.
  • An n-doped field stop zone 11 is provided in the areas below the etching shoulders 12.
  • This field stop zone 11 here has the same conductivity type as the inner zone 2 and the cathode zone 8.
  • the field stop zone 11 is connected to the cathode zone 8 and is arranged between the polished-etched surfaces 7 ′ and the inner zone 2. It is particularly advantageous if the doping concentration of the field stop zone 11 is lower than that of the cathode zone 8 and higher than that of the inner zone 2. In this way it can be ensured that a flatter gradient of the doping concentration of in the edge region RB of the pin diode the surface 7 ! to the inner zone.
  • the field stop zone 11 has a homogeneous n-doping. In a further development, it would also be very advantageous if the field stop zone 11 has a slowly decreasing doping concentration towards the edge.
  • the pin diode in FIG. 1 is constructed in a so-called mesa structure.
  • mesa structures have a typically positive beveling of the side walls 13 of the semiconductor body 1.
  • this taper angle of the side wall 13 is designated by ⁇ .
  • Typical values of the bevel angle ⁇ for a brass structure are between 20 and 45 °.
  • the field stop zones 11 are only provided in the edge region RB of the semiconductor component. It would of course also be conceivable if the field stop zone 11 is arranged as a continuous layer over the entire width of the semiconductor body 1. This case is shown in the exemplary embodiment in FIG. 2.
  • the field stop zone 11 is arranged both in the edge region RB and in the active region AB of the pin diode. In particular in the active region AB of the pin diode, the field stop zone 11 thus spaces the cathode zone 8 and the inner zone 2 from one another.
  • the field stop zone 11 can advantageously be introduced into the semiconductor body 1 by means of the cathode electrode 9, which acts as a mask, after the areas 10 have been etched off.
  • a field stop zone 11 is provided, which has been introduced over a large area into the semiconductor body 1.
  • the cathode zone 8 is then applied over a large area to the field stop zone 11, for example by means of a deposition process.
  • the corresponding regions 10 are etched out of the semiconductor body 1.
  • electroactive passivation layers for example made of an amorphous carbon compound, can be applied to the surfaces 7 '.
  • the function of the field stop zone 11 according to the invention in the case of the pin diode according to FIG. 3 or 4 is described in more detail below:
  • measures for reducing the electric field at the surface 7, 7 ⁇ must be taken.
  • the space charge zone hits a field stop zone in blocking operation.
  • this field stop zone is typically formed by the emitter zone 8.
  • the space charge zone is captured by this field stop zone designed as an emitter zone 8.
  • the electric field rises in this emitter zone 8 and a trapezoidal field profile of the electric field is created in the volume of the semiconductor body 1. Due to this trapezoidal field profile, the electric field is reduced towards the surface 7 of the semiconductor body 1.
  • the field profile is no longer trapezoidal due to the lack of emitter zone 8 there and thus the required field stop zone; Rather, the division of the electric field sometimes leads to extreme field peaks on the etching shoulders 12.
  • the field stop zones 11 are introduced into the semiconductor body 1 in the areas below the etching shoulders 12. It is important to ensure that these field stop zones 11 are not interrupted, i.e. they must be connected directly to the emitter zone 8, which is also designed as a field stop zone, and to the inner zone 2. In this way it is ensured that a trapezoidal field profile is generated across the entire width of the semiconductor body 1 from the pn junction to the surface 7, 7 and thus field peaks in the edge region RB are avoided.
  • the present invention is not limited exclusively to power semiconductor components designed as pin diodes, but can also be very advantageous with other cables. semiconductor devices are used. Figures 3 and 4 show two further advantageous embodiments.
  • FIG. 3 schematically shows a partial section of an exemplary embodiment of a power semiconductor component designed as a GTO with an edge termination according to the invention.
  • the GTO gate turn-off thyristor
  • the GTO which is designed here as an asymmetrically blocking thyristor, has an anode connection A and a cathode connection K on opposite sides of the semiconductor body 1.
  • the semiconductor body 1 consists of an n-doped n-base zone 20.
  • a p-doped p-base zone 22 connects to the n-base zone 20 via a large-area pn junction 21.
  • a heavily n-doped n-emitter zone 23 is connected to the p-base zone 22.
  • the n-emitter zone 23 is connected to the cathode terminal K via a cathode metallization or cathode electrode 24 on the rear surface 25.
  • a p-doped p-emitter zone 26 is embedded in the front surface 27 of the semiconductor body 1 in the active region AB of the thyristor on the anode side.
  • the p-emitter zone 26 is connected to the anode connection A via a large-area anode metallization or anode electrode 28. Furthermore, in FIG. 3 the p-emitter zone 26 is over a buffer layer
  • the p-emitter zone 26 and thus the anode electrode 28 can be connected to the n-base zone 20 via at least one via 30.
  • This buffer zone 29 in the region of the semiconductor component on the anode side thus serves as a field stop zone in blocking operation. In principle, a continuous emitter without anode short circuits is also conceivable.
  • the thyristor has a so-called transparent emitter, i.e. an anode side
  • Buffer layer 29 with anode short circuits 30 With such transparent emitters, the p-emitter zones 26 are after the Ion implantation did not heal completely to ensure a low charge carrier injection. These measures are carried out with generic thyristors or GTOs in order to be able to switch them on and off in a defined manner. Instead of such a transparent emitter, it would alternatively also be conceivable to irradiate the areas below the anode-side p-emitter zone 26 with helium in order to thereby generate a recombination sink.
  • Areas 31 etched out of the semiconductor body 1 are provided in the edge area RB, ie outside the active area AB of the thyristor, equivalent to the diode structures of FIGS. 1 and 2. These are arranged under the polished-etched surfaces 27 x of the etching shoulders 33 resulting from the etched-out regions 31.
  • the field stop zones 32 are here connected to the p-emitter zone 26.
  • the field stop zones 32 are n-doped and have a higher doping concentration than the n-base zone 20.
  • the thyristor is shown as an asymmetrical thyristor with a field stop zone or buffer layer 29. So that the anode-side gain ⁇ pn p does not disappear, the amount of charge in the field stop zone 29 must not be greater than the breakthrough charge in the case of structures short-circuited on the anode.
  • the mode of operation of this field stop zone 32 according to the invention in the edge region of the semiconductor component is equivalent to the mode of operation of the field stop zone 11 of the pin diodes according to FIGS. 1 and 2.
  • the doped can be any doped
  • Field stop zones 32 in a thyristor or GTO, equivalent to a pin diode, ensure complete volume blocking capability also in the edge region RB of the semiconductor component.
  • the exemplary embodiment of a thyristor shown in FIG. 3 shows only one possible advantageous embodiment.
  • the edge structure according to the invention can of course also be used very advantageously with all other vertically designed thyristors with edge termination, in particular GTOs and monolithically integrated systems such as, for example, reverse-conducting thyristors.
  • FIG. 4 schematically shows in a partial section an exemplary embodiment of a power semiconductor component according to the invention designed as an IGBT, in which the edge structure according to the invention is also used.
  • the IGBT in Figure 4 is constructed in a known manner. Since the four-layer structure of the IGBT (insulated gate bipolar transistor) shown in FIG. 4 is constructed similarly to the four-layer structure of the thyristor shown in FIG. 3, only the features that differ from the thyristor in FIG. 3 are discussed in more detail below.
  • the heavily n-doped n-emitter zones 23 are embedded in the shape of a trough in these p-base zones 22.
  • the p-base zone 22 and the n-emitter zones 23 are connected to one another on the surface 25 in a known manner via a cathode electrode 35 designed as a shunt.
  • a MOS structure is provided here.
  • the MOS structure comprises a gate electrode 36 and a gate oxide 37, which are each arranged over the regions of the n-base zone 20, p-base zone 21 and n-emitter zone 22 which come to the surface 25.
  • the p-emitter zone 26 arranged on the surface 27 is designed as a collector in the IGBT.
  • the IGBT in FIG. 4 has no plated-through holes 30 between p-collector zone 26 and n-base zone 20.
  • the buffer zone 29 serves as a field stop zone for the reduction of the electric field on the surface of the pane, equivalent to the thyristor in FIG.
  • the function of the field stop zone 32 according to the invention is here equivalent to the aforementioned examples of a pin diode according to FIGS. 1 or 2 or of the GTO according to FIG. 3.
  • the edge regions RB thereof are formed in a mesa structure.
  • the present invention is also very advantageously applicable to power semiconductor components with edge closures of whatever type.
  • FIGS. 1 to 4 how possible other exemplary embodiments of the semiconductor components according to the invention can look; these are generally any asymmetrically blocking semiconductor components, such as diodes, thyristors, transistors, IGBTs and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

L'invention concerne un composant à semi-conducteur de puissance à blocage asymétrique, dans lequel il est prévu des zones d'arrêt de champ (11) du même type de puissance que dans la zone intérieure (2), dans la zone marginale en dessous des zones gravées (épaulements de gravure). Ces zones d'arrêt de champ (11) raccordées de manière générale à la zone intérieure et à la zone émettrice, jouxtent la surface toute sécurité gravée par polissage des épaulements de gravure (12). A cet effet, la concentration de dopage de ces zones d'arrêt de champ (11) est ajustée de manière à produire un gradient de la courbe de concentration du dopage, diminuant entre la surface des épaulements de gravure (12) jusque dans l'épaisseur du corps à semi-conducteur. Ce système permet de garantir, même dans des conditions extrêmes, la tension de rupture en volume, y compris dans la zone marginale (RB) du composant à semi-conducteur de puissance. L'invention s'utilise notamment dans des composants à semi-conducteurs de puissance de structure mesa, en particulier dans des diodes pin, des thyristors asymétriques, tels que par ex. des GTO, des IGBT et similaires.
EP00903516A 1999-01-12 2000-01-12 Composant a semi-conducteur de puissance a bord mesa Withdrawn EP1062700A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19900808 1999-01-12
DE19900808 1999-01-12
PCT/DE2000/000086 WO2000042662A1 (fr) 1999-01-12 2000-01-12 Composant a semi-conducteur de puissance a bord mesa

Publications (1)

Publication Number Publication Date
EP1062700A1 true EP1062700A1 (fr) 2000-12-27

Family

ID=7894004

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00903516A Withdrawn EP1062700A1 (fr) 1999-01-12 2000-01-12 Composant a semi-conducteur de puissance a bord mesa

Country Status (4)

Country Link
US (1) US6696705B1 (fr)
EP (1) EP1062700A1 (fr)
JP (1) JP2002535840A (fr)
WO (1) WO2000042662A1 (fr)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100841141B1 (ko) 2000-09-21 2008-06-24 캠브리지 세미컨덕터 리미티드 반도체 장치 및 반도체 장치의 형성 방법
DE102004045768B4 (de) * 2004-09-21 2007-01-04 Infineon Technologies Ag Verfahren zur Herstellung eines Randabschlusses eines Halbleiterbauelements
US7538412B2 (en) * 2006-06-30 2009-05-26 Infineon Technologies Austria Ag Semiconductor device with a field stop zone
US7728402B2 (en) * 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
EP2052414B1 (fr) 2006-08-17 2016-03-30 Cree, Inc. Transistors bipolaires à grille isolée, haute puissance
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
EP2208230B1 (fr) * 2007-11-09 2015-10-21 Cree, Inc. Dispositifs de puissance a semi-conducteurs dotes de structures mesa et de couches tampons comprenant des etages mesa
US9640609B2 (en) * 2008-02-26 2017-05-02 Cree, Inc. Double guard ring edge termination for silicon carbide devices
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8097919B2 (en) * 2008-08-11 2012-01-17 Cree, Inc. Mesa termination structures for power semiconductor devices including mesa step buffers
DE102008049678B4 (de) * 2008-09-30 2020-06-10 Infineon Technologies Bipolar Gmbh & Co. Kg Asymmetrisch sperrender Thyristor und Verfahren zur Herstellung eines asymmetrisch sperrenden Thyristors
US8497552B2 (en) * 2008-12-01 2013-07-30 Cree, Inc. Semiconductor devices with current shifting regions and related methods
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8637386B2 (en) * 2009-05-12 2014-01-28 Cree, Inc. Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8629509B2 (en) * 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8541787B2 (en) * 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US8803277B2 (en) 2011-02-10 2014-08-12 Cree, Inc. Junction termination structures including guard ring extensions and methods of fabricating electronic devices incorporating same
US9318623B2 (en) 2011-04-05 2016-04-19 Cree, Inc. Recessed termination structures and methods of fabricating electronic devices including recessed termination structures
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US8759935B2 (en) 2011-06-03 2014-06-24 Infineon Technologies Austria Ag Power semiconductor device with high blocking voltage capacity
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
EP2754177A1 (fr) 2011-09-11 2014-07-16 Cree, Inc. Module d'alimentation à haute densité de courant comprenant des transistors à topologie améliorée
US8530902B2 (en) * 2011-10-26 2013-09-10 General Electric Company System for transient voltage suppressors
CN103219372B (zh) * 2013-04-10 2015-10-28 株洲南车时代电气股份有限公司 一种晶闸管门阴极结及具有该结构的门极换流晶闸管
CN103227112B (zh) * 2013-04-10 2015-09-02 株洲南车时代电气股份有限公司 晶闸管门阴极结及具有该结构的门极换流晶闸管制备方法
CN104347401B (zh) * 2013-07-29 2017-05-10 无锡华润上华半导体有限公司 一种绝缘栅双极性晶体管的制造方法
US9570542B2 (en) 2014-04-01 2017-02-14 Infineon Technologies Ag Semiconductor device including a vertical edge termination structure and method of manufacturing
CN104009097B (zh) * 2014-06-09 2017-09-05 苏州市职业大学 一种耐高温整流二极管器件
CN104022161B (zh) * 2014-06-09 2018-02-06 苏州市职业大学 一种双向瞬态电压抑制保护器件
WO2017149580A1 (fr) * 2016-02-29 2017-09-08 株式会社日立製作所 Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5526670A (en) * 1978-08-15 1980-02-26 Nec Corp Manufacturing semiconductor device
EP0144876B1 (fr) * 1983-12-07 1988-03-09 BBC Brown Boveri AG Dispositif à semi-conducteurs
DE3422051C2 (de) * 1984-06-14 1986-06-26 Brown, Boveri & Cie Ag, 6800 Mannheim Silizium-Halbleiterbauelement mit ätztechnisch hergestellter Randkontur und Verfahren zur Herstellung dieses Bauelements
DE59009167D1 (de) * 1989-02-01 1995-07-06 Siemens Ag Elektroaktive Passivierschicht.
EP0400178B1 (fr) * 1989-05-31 1994-08-03 Siemens Aktiengesellschaft Dispositif semi-conducteur comprenant une couche de passivation
WO1997012403A1 (fr) * 1995-09-27 1997-04-03 Hitachi, Ltd. Diode

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0042662A1 *

Also Published As

Publication number Publication date
WO2000042662A1 (fr) 2000-07-20
JP2002535840A (ja) 2002-10-22
US6696705B1 (en) 2004-02-24

Similar Documents

Publication Publication Date Title
EP1062700A1 (fr) Composant a semi-conducteur de puissance a bord mesa
DE10330571B4 (de) Vertikales Leistungshalbleiterbauelemente mit Injektionsdämpfungsmittel im Randbereich und Herstellungsverfahren dafür
DE102007024113B4 (de) Halbleitervorrichtung mit isoliertem Gate und Verfahren zur Herstellung derselben
DE102006025958B3 (de) Sanft schaltendes Halbleiterbauelement mit hoher Robustheit und geringen Schaltverlusten
DE102009021021B4 (de) Bauelement mit verringerter freier Ladungsträger-Lebensdauer
DE102007015304B4 (de) Rückwärtsleitender (RC-) IGBT mit senkrecht angeordneter Ladungsträgerlebensdaueranpassung und Verfahren zur Herstellung eines rückwärtsleitenden IGBT
DE19533956C2 (de) Leistungshalbleitervorrichtung
DE102018215731B4 (de) Halbleitervorrichtung und Verfahren zum Herstellen derselben
DE102005049506B4 (de) Vertikales Halbleiterbauelement
WO2000004596A2 (fr) Composant a semi-conducteur de puissance pour tensions de blocage elevees
DE102005056426B4 (de) Halbleiterbauelement und Verfahren zu dessen Herstellung
DE102005039564B4 (de) Verfahren zum Herstellen eines Halbleiterbauteils
EP1131852B1 (fr) Composant semi-conducteur dote de structures de blindage dielectriques ou semi-isolantes
DE102017219159A1 (de) Halbleitervorrichtung und Fertigungsverfahren dafür
DE10240107B4 (de) Randabschluss für Leistungshalbleiterbauelement und für Diode sowie Verfahren zur Herstellung einer n-leitenden Zone für einen solchen Randabschluss
DE112021002169T5 (de) Halbleitervorrichtung
DE102021103703A1 (de) Hochvolt-Randabschluss-Struktur für Leistungshalbleiterbauelemente und Verfahren zum Herstellen derselben
EP0913000A1 (fr) Composant a semiconducteur pouvant etre commande par effet de champ
DE19528998A1 (de) Bidirektionaler Halbleiterschalter und Verfahren zu seiner Steuerung
EP1097482B1 (fr) Ensemble a semi-conducteur, en particulier transistor a effet de champ a jonction
DE4039012C2 (de) Mos-Halbleiterbauelement
DE69937665T2 (de) Halbleiterbauelement mit isoliertem Gate und dessen Betriebsverfahren
DE112020002222T5 (de) Siliziumkarbid-halbleitervorrichtung und verfahren zum herstellen einer siliziumkarbid-halbleitervorrichtung
DE102005029263B4 (de) Halbleiterbauelement mit verbesserter dynamischer Belastbarkeit
DE10245089A1 (de) Dotierverfahren und Halbleiterbauelement

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20001010

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB IT

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

17Q First examination report despatched

Effective date: 20070226

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20081231