Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/01—Details
  • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature

Definitions

• This invention relates generally to integrated circuits which produce clock frequencies.
• the present invention is a precision relaxation oscillator that produces a stable clock frequency over wide variations of ambient temperature, fabrication process and voltage.
• the invention is implemented on a single, monolithic integrated circuit.
• the precision relaxation oscillator is capable of several modes of operation.
• the current state of the art describes RC relaxation oscillators which primarily depend on one of two schemes.
• a single comparator is coupled to a pulse generator to alternately charge and discharge a capacitor to produce a clock for a "D type" flip-flop.
• the resistor and capacitor typically have unpredictable voltage and temperature coefficients.
• the charging current and comparator input slew are a function of the supply voltage which is also subject to drift.
• the pulse generator output may vary with temperature and supply voltage. These factors lead to a clock frequency that varies over temperature.
• an RC circuit provides a common input to each of two comparators . Independent reference voltages are coupled to each of the remaining inputs of the comparators . The outputs of each of the two comparators are coupled to the inputs of a "Set-Reset type" flip-flop. The output of the flip-flop serves to alternately charge and discharge the capacitor.
• a relaxation oscillator which is capable of maintaining a stable clock frequency independent of temperature.
• a stable clock is defined as one which maintains a stable frequency- in an environment which is subject to temperature fluctuations.
• a precision relaxation oscillator that produces a stable clock frequency over wide variations of ambient temperature.
• the precision relaxation oscillator is comprised of an oscillation generator, a first current generator for producing a first output current and a second current generator for producing a second output current.
• the invention is implemented on a single, monolithic integrated circuit.
• an external resistor may be coupled to either the first or second current generators to produce the respective output currents required for determining the clock frequency.
• a plurality of internal resistors within the first and second current generators are provided which are used to select the clock speed of the oscillator.
• a transition detector circuit is provided.
• a clock inhibiter coupled to the output of the oscillation generator is provided.
• Figure 1 is a schematic diagram of the prior art showing a simple RC Relaxation Oscillator with a pulse generator.
• Figure 2 is a schematic diagram of the prior art showing a dual comparator RC Relaxation Oscillator.
• FIG. 3 is a block diagram of the present invention.
• FIG. 4 is a block diagram of the CTAT current generator found in the present invention.
• Figure 5 is a block diagram of the PTAT current generator found in the present invention.
• Figure 6 is a timing diagram of specific parameters of the present invention.
• Figure 7 is a timing diagram of the clock transition between slow mode and fast mode.
• a precision relaxation oscillator 1 that produces a stable clock frequency over wide variations of ambient temperature is shown.
• the precision relaxation oscillator 1 produces a stable clock frequency in the range of approximately 1 KHz to 8 MHz.
• the present invention is not limited to a specific frequency range.
• the precision relaxation oscillator 1 is capable of 3 modes.
• the first mode is the fast mode and is the normal operating mode.
• the second mode is the slow mode and is selected to conserve power, yet to have some functions of the circuit to which the precision relaxation oscillator 1 serves, remain active.
• the third mode is the sleep mode. In this mode, the precision relaxation oscillator 1 is inactive and there is no clock output, nor is there any power consumption.
• the transition between modes may occur "on the fly," i.e. suspension of processing activity by the CPU is not required for transitioning from one mode to another. chorus• However, in the preferred embodiment, the CPU or microcontroller will have completed the current instruction cycle before switching modes.
• the precision relaxation oscillator 1 is comprised of an oscillation generator 100, a first current generator 200 which is typically a Complementary to Absolute Temperature (CTAT) current generator, a second current generator 300 which is typically a Proportional to Absolute Temperature (PTAT) current generator, a transition detector 400 and a clock inhibiter 500.
• CTAT Complementary to Absolute Temperature
• PTAT Proportional to Absolute Temperature
• the precision relaxation oscillator 1 is implemented on a single, monolithic integrated circuit.
• CTAT 200 and PTAT 300 current generators are independently implemented and yield several important functions to the present invention.
• the CTAT 200 and PTAT 300 current generators compensate for the effects that temperature variation has on the internal components of the device such as resistors, capacitors and comparators by providing offsetting currents CTAT current 220 and PTAT current 320, i.e. currents with opposite slopes with respect to temperature.
• the combining, or summing of the CTAT current 290 and PTAT current 390 occurs when introduced to the oscillation generator 100 for charging a first capacitor 110 and a second capacitor 120. Because the CTAT 290 and PTAT 390 currents are approximately linear and ⁇ -of opposite slope with respect to temperature, the result of the summation is an I ccc 190 that is nearly independent of temperature.
• the oscillation generator 100 is comprised of a set-reset flip-flop 160, a comparator circuit 180 further comprised of two comparators 182 & 184, two capacitors 110 & 120, four transistor switches 130, 132, 134 & 136, two inverters 140 & 142 and a bandgap reference voltage circuit 150 for producing a reference voltage 152.
• the transistor switches 130 & 134 provide charging paths for the capacitors 110 & 120, respectively.
• the transistor switches 132 & 136 provide discharging paths for the capacitors 110 & 120, respectively.
• the transistor switches 130, 132, 134 and 136 are MOSFET transistors, however, those skilled in the art will recognize that the invention is not limited to this technology.
• the oscillation generator 100 operates by having one capacitor charge while the other capacitor discharges.
• the discharge path for the capacitor 110 is connected via transistor switch 132 to an input of the comparator 182.
• the discharge path for the capacitor 120 is connected via transistor switch 136 to an input of the comparator 184.
• a stable reference voltage source such as a bandgap reference voltage circuit 150 is used.
• the bandgap reference voltage circuit 150 provides a single reference voltage 152, whic is connected to second inputs of comparators 182 & 184, and is used to set the common mode voltage at each comparator 182 & 184 and at the CTAT current generator 200.
• the P BIA ⁇ input 325 for the bandgap reference voltage circuit 150 is an output of the PTAT bias generator 310 which is described below.
• the bandgap reference voltage circuit 150 has the advantage of stabilizing capacitor charging current and minimizing the error due to variance in comparator input slew and propagation delay.
• the CTAT 200 current generator relies on the same reference voltage 152 as the comparators 182 & 184.
• the CTAT current 290 (figure 4), which is equal to Vpr F /R, also increases. Without compensation elsewhere, this increased CTAT current 290 would result in a faster clock frequency 166, because a greater I ccc 190 is produced, which results in faster charging of the capacitors 110 and 120.
• the capacitors 110 and 120 must charge to a greater level for the comparators 182 and 184 to trip with respect to the increased reference voltage 152.
• the present invention requires a simpler, lest costly reference voltage source to achieve clock frequency stability.
• bandgap reference voltage circuit 150 there are various embodiments of the bandgap reference voltage circuit 150, as well as other reference voltage sources such as voltage dividers, which are well known to those skilled in the art. However, the novel way in which the bandgap reference voltage circuit 150 is implemented in the present invention is not disclosed by the prior art.
• comparator 182 is connected to the set input 162 of the flip-flop 160.
• comparator 184 is connected to the reset input 164 of the flip-flop 160.
• the Q output 166 of the flip-flop 160 provides a stable clock frequency INTCLK that is independent of temperature variation.
• the Q output 166 is also routed to transistor switch 132 and via inverter 140 to transistor switch 130.
• the Q output 166 provides the signal that controls the transistor switches 130 & 132 which in turn open and close the charging and discharging paths for capacitor 110.
• the complementary Q output 168 of flip-flop 160 provides a second stable clock frequency that is also independent of temperature and the complement of Q output 166.
• the complementary Q output 168 is routed to transistor switch 136 and via inverter 142 to transistor switch 134.
• the complementary Q output 168 provides the signal that controls the transistor switches 134 & 136 which in turn open and close the charging and discharging paths for capacitor 120.
• the transition detector 400 performs two primary functions: converting an asynchronous fast/slow signal (AS K YNCH FAST/SLOW) to a synchronous fast/slow signal (SYNCH FAST/SLOW 404) and initializing the clock inhibiter 500.
• the purpose of the clock inhibiter 500 is to inhibit INTCLK 166 from being output as CLKOUT 502 for a programmable number of clock cycles during mode transition when the INTCLK 166 may be unstable.
• the transition detector 400 which is comprised of simple combinational and sequential logic such as a synchronous one-shot, sends a RSTCLK 402 signal to initialize the clock inhibiter 500.
• the clock inhibiter 500 Upon receiving the RSTCLK 402 signal from the transition detector 400, the clock inhibiter 500, which may be a simple programmable counter, will inhibit CLKOUT 502 from being sent to the connected circuitry, e.g. the CPU, for a predetermined number of clock cycles.
• the clock inhibiter 500 serves to prevent logic anomalies as a result of an unstable clock frequency or a clock frequency in transition. After a predetermined number of clock cycles following mode transition, when presumptively the operation of the precision relaxation oscillator 1 is stable, the clock inhibiter 500 will allow the CLKOUT 502 to pass to the connected circuitry.
• the trailing edge of the RSTCLK 402 signal triggers the SYNCH FAST/SLOW 404 signal.
• the SYNCH FAST/SLOW 402 is used by the CTAT current generator 200 and PTAT current generator 300 to adjust the respective currents 290 and 390 for fast or slow mode operation, as described below.
• the CTAT current generator 200 is comprised of a CTAT bias generator 210 and a current mirror 250 for producing the CTAT current 290.
• the CTAT bias generator 210 is comprised of an amplifier circuit 220, at least one resistor 232, 233 & 234 with a small positive temperature coefficient for regulating the input current to the amplifier and a transistor 240 for providing an input current to the amplifier 220.
• the amplifier 220 is a cascode configuration for supply and noise rejection.
• the reference voltage 152 is coupled to an input of the amplifier 220.
• the different resistors 232, 233 & 234, which vary in impedance, are for controlling the current sent to the current mirror 250 and thus, determine the specific stable clock frequency independent of temperature which is produced by the oscillation generator 100.
• the present invention provides for selection logic 230 which inputs SYNCH FAST/SLOW 404 and a resistor select (R SELECT 236) for selecting one of the three resistors 232, 233 or 234. If the slow mode is activated by SYNCH FAST/SLOW 404, then the internal resistor R INT/LP 233 is selected. If the fast mode is activated by SYNCH FAST/SLOW 404 then the selection logic 230 considers the input R SELECT 236 in choosing as between the internal resistor R INT 232 and the external resistor R EX ⁇ 234.
• the fast mode ⁇ -internal resistor 232 is fabricated from polysilicon technology which provides for low impedance and thus, higher current which in turn provides for a faster clock.
• polysilicon technology has a low temperature coefficient (ppm/deg C) , thus providing improved frequency stability over temperature.
• the slow mode internal resistor 233 is preferably fabricated from doped silicon substrate, typically either through implantation and/or diffusion, e.g. Lightly Doped Drain (LDD) .
• doped silicon produces a high impedance which in turn reduces the current to the current mirror 250, and thus allows for operating at low power .
• the slow mode internal resistor 233 could be fabricated using polysilicon technology. However, the resistance per unit area of polysilicon is significantly lower than the resistance per unit area of doped silicon. Thus, a polysilicon resistor would require significantly greater semiconductor area than a doped silicon resistor for a similar resistance.
• the power consumption of the precision relaxation oscillator 1 in typical applications ranges from 250 ua (micro amperes) in the fast mode to 20 ua or less in the slow mode. No power is consumed when in the sleep mode.
• the current mirror 250 is comprised of a plurality of transistors 252 from one to n.
• the output the CTAT bias generator amplifier 220 is coupled to the current mirror transistors 252. Trimming the CTAT current 290 for achieving the proper CTAT: PTAT balance is programmed digitally by selecting qr enabling one or more of the current mirror transistors 252 via the calibration switches 254, which would sum, to obtain the desired CTAT current 290.
• the calibration switches 254 are also coupled the SYNCH FAST/SLOW 404 signal via the CTAT calibration select decode 256.
• the calibration switches 254 are configured to trim I CTAT for a fast clock.
• the calibration switches 254 may require a different configuration to trim I CTAT for a slow clock.
• the calibrations switches 254 toggle between a fast mode calibration and a slow mode calibration in response to the state of the SYNCH FAST/SLOW 404 signal.
• the current mirror 250 acts as a current divider which is well known to those skilled in the art. In other embodiments the current mirror 250 may be configured as a current multiplier.
• the CTAT current 290 is the sum of the selected outputs from the current mirror transistors 252.
• the PTAT current generator 300 known to those skilled in the art as a ⁇ V BE circuit, is comprised of PTAT bias generator 310 and a PTAT current mirror 350 for producing a PTAT current 390.
• the PTAT bias generator 310 is comprised of an amplifier circuit 320, a first bias circuit 330 for producing a first bias voltage across a selectable resistor with a small linear temperature coefficient 332, 333 and 334 and a second bias circuit 340 for producing a second bias voltage.
• the first and second bias voltages provide the inputs to the amplifier 320.
• the output of the amplifier 320 is P B1AS 325 which is coupled to the first 330 and second 340 bias circuits, the PTAT current mirror 350 and the bandgap reference voltage generator 150 (figure 1) .
• the different resistors 332, 333 and 334 which vary in impedance, are for controlling the current sent to the current mirror 350 and thus, determine the specific stable clock frequency independent of temperature which is produced by the oscillation generator 100.
• the PTAT bias generator 310 provides for selection logic 330 which inputs SYNCH FAST/SLOW 404 and the resistor select (R SELEC ⁇ 236) for selecting one of the three resistors 332, 333 or 334. If the slow mode is activated by SYNCH FAST/SLOW 404, then the internal resistor R INT/LP 333 is selected. If the fast mode is activated by SYNCH FAST/SLOW 404, then the selection logic 330 considers the input R SELECT 336 in choosing as between the internal resistor R INT 332 and the external resistor R ⁇ 334.
• the fast mode internal resistor 332 is fabricated from polysilicon technology which provides for low impedance and thus , higher current which in turn provides for a faster clock.
• polysilicon technology has a low temperature coefficient (ppm/deg C) , thus providing improved frequency stability over temperature.
• the slow mode internal resistor 333 is preferably fabricated from diffused technology, e.g. Lightly Doped Drain (LDD) . Diffused technology produces a high impedance which in turn reduces the current to the current mirror 350, and thus allows for operating at low power.
• the respective resistor pairs in the CTAT and PTAT bias generators 210 and 310 are matched to each other for optimum suability, ' e.g. both resistors (R EXT 234 and 334 or R INT 232 and 332) are polysilicon in the fast mode and both resistors (R ⁇ T LP 233 and 333) are doped silicon in the slow mode.
• the slow mode internal resistor 333 could be fabricated using polysilicon technology. However, the resistance per unit area of polysilicon is significantly lower than the resistance per unit area of diffused technology. Thus, a polysilicon resistor would require significantly greater semiconductor area than, a doped silicon resistor for a similar resistance.
• the PTAT current mirror 350 is comprised of a plurality of transistors 352 from one to n. Trimming is performed digitally by programming the selection or enablement of one or more of the current mirror transistors 352 via the calibration switches 354 to obtain the desired PTAT current 390.
• the calibration switches 354 are also coupled to the SYNCH FAST/SLOW 404 signal via the PTAT calibration select decode 356.
• the calibration switches 354 are configured to trim I PTAT for a fast clock.
• the calibration switches 354 may require a different configuration to trim I PTAT for a slow clock.
• the calibrations switches 354 toggle between a fast mode calibration and a slow mode calibration in response to the state of the SYNCH FAST/SLOW 404 signal.
• the current mirror 350 acts as a current divider which is well known to those skilled in the art. In other embodiments the current mirror 350 may be configured as a current multiplier.
• the PTAT current 390 is the sum of the selected outputs from the current mirror transistors 352.
• VI 112 reflects the charging and discharging of capacitor 110 (figure 1) .
• the positive slope (charging) of VI 112 is equal to I ccc 190 divided by the capacitance of capacitor 110.
• the maximum amplitude of VI 112 is equal to the reference voltage 152.
• CMPl reflects the output of the comparator 182 which is coupled to the set input 162 of the flip-flop 160.
• V2122 reflects the charging and discharging of capacitor 120.
• the positive slope of V2 122 is equal to I ccc 190 divided by the capacitance of capacitor 120.
• CMP2 reflects the output of the comparator 184 which is coupled to the reset input 164 of the flip-flop 160.
• CLK is the Q output 166 of the flip-flop 160.
• the values of- capacitors 110 & 120 are identical which result in similar slopes for VI 112 and V2 122.
• the respective comparator 182 & 184 pulses low which causes the flip-flop 160 to change state.
• RST reset
• FIG. 7 a timing diagram which illustrates the transition from slow mode to fast mode of the embodiment of figure 3 is shown.
• the relaxation oscillator.1 would operate similarly when transitioning from fast mode to slow mode.
• the relaxation oscillator 1 ( Figure 3) is first operating in the slow mode.
• the ASYNCH FAST/SLOW signal which is generated external to the present invention, is received by the transition detector 400.
• logic level zero indicates slow mode and logic level one indicates fast mode.
• the signal to transition to sleep mode is a separate, active high signal.
• the transition detector 400 Upon receiving the ASYNCH FAST/SLOW signal, that meets the required setup time in relation to the internal clock INTCLK 166, to transition to the fast mode, the transition detector 400 generates two outputs.
• the transition detector 400 outputs a reset pulse RSTCLK 402 to the clock inhibiter 500.
• the transition detector 400 also synchronizes the ASYNCH FAST/SLOW signal and at the ⁇ trailing edge of RSTCLK 402, the transition detector 400 outputs SYNCH FAST/SLOW 404 to the current generators 200 and 300. At this point the current generators 200 and 300 begin the switching to generate the currents required for the fast mode. As the current generators 200 and 300 begin their internal switching, several clock cycles are required to allow the bias currents to settle and for INTCLK 166 to stabilize.
• the clock inhibiter 500 Upon receiving RSTCLK 402, the clock inhibiter 500 immediately begins inhibiting CLKOUT 502. At the trailing edge of the RSTCLK 504 pulse, the relaxation oscillator 1 begins to transition from slow to fast mode. In one embodiment, the clock inhibiter counts and inhibits eight fast clock cycles of the INTCLK 166 for stabilization, before releasing the inhibit and allowing CLKOUT 504 to proceed with the fast mode clock.
• the present invention minimizes clock frequency drift due to fabrication process, supply voltage and temperature variances. This is accomplished by providing offsetting bias currents which when summed are independent of temperature variation, trimming via the programmable current mirrors 250 & 350 to eliminate process variations, using a stable voltage reference such as a bandgap reference voltage circuit 150 and a dual capacitor, dual comparator oscillation generator 100. Also, analog design techniques, well known to those skilled in the art, such as component matching and cascode current sources enhance the stability of the circuit.

Landscapes

• Semiconductor Integrated Circuits (AREA)
• Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=22763532

Family Applications (1)

Country Status (4)

Families Citing this family (23)

• 1999
  • 1999-12-06 KR KR1020007008568A patent/KR20010040690A/ko not_active Application Discontinuation
  • 1999-12-06 EP EP99963026A patent/EP1053596A1/de not_active Withdrawn
  • 1999-12-06 JP JP2000588893A patent/JP2003529227A/ja not_active Withdrawn
  • 1999-12-06 CN CN99804764A patent/CN1296665A/zh active Pending

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events