EP1008175A4 - Bedeckte dielektrische zwischenschicht zum chemisch-mechanischen schleifen - Google Patents

Bedeckte dielektrische zwischenschicht zum chemisch-mechanischen schleifen

Info

Publication number
EP1008175A4
EP1008175A4 EP96933088A EP96933088A EP1008175A4 EP 1008175 A4 EP1008175 A4 EP 1008175A4 EP 96933088 A EP96933088 A EP 96933088A EP 96933088 A EP96933088 A EP 96933088A EP 1008175 A4 EP1008175 A4 EP 1008175A4
Authority
EP
European Patent Office
Prior art keywords
capped
mechanical polishing
chemical mechanical
interlayer dielectric
interlayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96933088A
Other languages
English (en)
French (fr)
Other versions
EP1008175A1 (de
Inventor
Peng Bai
Kenneth C Cadien
Lie-Yea Cheng
Matthew J Prince
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP1008175A1 publication Critical patent/EP1008175A1/de
Publication of EP1008175A4 publication Critical patent/EP1008175A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP96933088A 1995-09-29 1996-09-23 Bedeckte dielektrische zwischenschicht zum chemisch-mechanischen schleifen Withdrawn EP1008175A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US53600795A 1995-09-29 1995-09-29
US536007 1995-09-29
PCT/US1996/015201 WO1997012393A1 (en) 1995-09-29 1996-09-23 Capped interlayer dielectric for chemical mechanical polishing

Publications (2)

Publication Number Publication Date
EP1008175A1 EP1008175A1 (de) 2000-06-14
EP1008175A4 true EP1008175A4 (de) 2000-10-18

Family

ID=24136721

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96933088A Withdrawn EP1008175A4 (de) 1995-09-29 1996-09-23 Bedeckte dielektrische zwischenschicht zum chemisch-mechanischen schleifen

Country Status (8)

Country Link
EP (1) EP1008175A4 (de)
JP (1) JPH11512877A (de)
KR (1) KR19990063743A (de)
CN (1) CN1203697A (de)
AU (1) AU7164596A (de)
IL (1) IL123749A0 (de)
TW (1) TW304297B (de)
WO (1) WO1997012393A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6153935A (en) * 1999-09-30 2000-11-28 International Business Machines Corporation Dual etch stop/diffusion barrier for damascene interconnects
US7316972B2 (en) 2002-08-30 2008-01-08 Matsushita Electric Industrial Co., Ltd. Contact hole formation method
US7521364B2 (en) * 2005-12-02 2009-04-21 Macronix Internation Co., Ltd. Surface topology improvement method for plug surface areas
US8067762B2 (en) 2006-11-16 2011-11-29 Macronix International Co., Ltd. Resistance random access memory structure for enhanced retention
DE102007063271B4 (de) 2007-12-31 2009-11-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines dielektrischen Zwischenschichtmaterials mit unterschiedlichen Abtragsraten während eines CMP-Prozesses

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293632A (ja) * 1988-05-23 1989-11-27 Nec Corp 半導体装置
EP0540321A1 (de) * 1991-10-30 1993-05-05 Samsung Electronics Co. Ltd. Verfahren zur Herstellung der dielektrischen Zwischenschicht einer Halbleitervorrichtung
US5340370A (en) * 1993-11-03 1994-08-23 Intel Corporation Slurries for chemical mechanical polishing

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0680638B2 (ja) * 1990-07-05 1994-10-12 株式会社東芝 半導体装置の製造方法
EP0469214A1 (de) * 1990-07-31 1992-02-05 International Business Machines Corporation Verfahren zur Herstellung geschichteter Leiter- und/oder Widerstandsbereiche in Multiebenen-Halbleiterbauelementen und daraus resultierende Struktur
US5164340A (en) * 1991-06-24 1992-11-17 Sgs-Thomson Microelectronics, Inc Structure and method for contacts in cmos devices
US5244837A (en) * 1993-03-19 1993-09-14 Micron Semiconductor, Inc. Semiconductor electrical interconnection methods
US5409858A (en) * 1993-08-06 1995-04-25 Micron Semiconductor, Inc. Method for optimizing thermal budgets in fabricating semiconductors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293632A (ja) * 1988-05-23 1989-11-27 Nec Corp 半導体装置
EP0540321A1 (de) * 1991-10-30 1993-05-05 Samsung Electronics Co. Ltd. Verfahren zur Herstellung der dielektrischen Zwischenschicht einer Halbleitervorrichtung
US5340370A (en) * 1993-11-03 1994-08-23 Intel Corporation Slurries for chemical mechanical polishing

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 082 (E - 0889) 15 February 1990 (1990-02-15) *
See also references of WO9712393A1 *

Also Published As

Publication number Publication date
WO1997012393A1 (en) 1997-04-03
JPH11512877A (ja) 1999-11-02
CN1203697A (zh) 1998-12-30
EP1008175A1 (de) 2000-06-14
KR19990063743A (ko) 1999-07-26
AU7164596A (en) 1997-04-17
IL123749A0 (en) 1998-10-30
TW304297B (de) 1997-05-01

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