EP1008175A1 - Couche intermediaire dielectrique coiffee pour polissage chimico-mecanique - Google Patents

Couche intermediaire dielectrique coiffee pour polissage chimico-mecanique

Info

Publication number
EP1008175A1
EP1008175A1 EP96933088A EP96933088A EP1008175A1 EP 1008175 A1 EP1008175 A1 EP 1008175A1 EP 96933088 A EP96933088 A EP 96933088A EP 96933088 A EP96933088 A EP 96933088A EP 1008175 A1 EP1008175 A1 EP 1008175A1
Authority
EP
European Patent Office
Prior art keywords
oxide layer
layer
insulating layer
forming
ild
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96933088A
Other languages
German (de)
English (en)
Other versions
EP1008175A4 (fr
Inventor
Peng Bai
Kenneth C. Cadien
Lie-Yea Cheng
Matthew J. Prince
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP1008175A1 publication Critical patent/EP1008175A1/fr
Publication of EP1008175A4 publication Critical patent/EP1008175A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment

Definitions

  • the present invention relates to the field of semiconductor fabrication and more specifically to a method of forming an interconnect structure in an integrated circuit.
  • Interconnection structures normally have a first layer of metallization, an interconnection layer 102 (typically aluminum alloy with up to 3% copper), a second layer of metallization 104, and sometimes a third or even a fourth level of metallization.
  • Interlevel dielectrics 106 such as silicon dioxide (Si ⁇ 2) are used to electrically isolate the different levels of metallization on silicon substrate or well 108.
  • the electrical connections between different interconnection levels are made through the use of metallized vias 110 formed in ILD 106.
  • metal contacts 112 are used to form electrical connections between interconnection levels and devices formed in well 108.
  • the metal vias 110 and contacts 112, hereinafter collectively referred to as “vias” or “plugs”, are generally filled with tungsten 114 and generally employ an adhesion layer 116 such as titanium.
  • a presently preferred interlevel dielectric film for ultra large scale mtegrated circuits is a borophosphosilicate glass (BPSG) film formed by atmospheric chemical vapor deposition (CVD).
  • BPSG borophosphosilicate glass
  • CVD atmospheric chemical vapor deposition
  • Atmospheric CVD BPSG layers are preferred because they can be formed very conformally and thereby can fill high aspect ratio gaps created by the high density placement of active devices on a semiconductor substrate. Atmospheric BPSG layers can fill high aspect ratio gaps without creating voids therein.
  • atmospheric BPSG layers are preferred because deposition machinery is relatively inexpensive as compared to other ILD equipment such as plasma enhanced chemical vapor deposition (PECVD) equipment. Additionally, atmospheric BPSG layers can be deposited relatively fast allowing for good wafer throughput.
  • PECVD plasma enhanced chemical vapor deposition
  • a presently preferred method of forming plugs on vias 110 and 112 in an ultra large scale in an ULSI circuit is a tungsten plug process which utilizes chemical mechanical polishing.
  • via holes are etched through an ILD to interconnection lines or semiconductor substrate formed below.
  • a thin adhesion layer such as titanium nitride is formed over the ILD and into the via hole.
  • a conformal tungsten film is blanket deposited over the adhesion layer and into the via. The deposition is continued until the via hole is completely filled with tungsten.
  • a metal film formed on top of the surface of the ILD is removed by chemical mechanical polishing to thereby form a metal via or plug.
  • Such processes are preferred because they can fill high aspect ratio vias which are required to make electrical connection to densely packed active devices formed below.
  • a problem with tungsten plug processes and atmospheric BPSG ILD layers is that they are incompatible with one another.
  • the problem is that tungsten polishing processes are not selective enough to atmospheric BPSG ILD layers. As such, when polishing back the tungsten layer, a substantial amount of ILD layer can be removed from areas which clear tungsten first. If too much ILD is lost during the tungsten plug process, shorts can develop between active devices and the first level metallization or between levels of metallization.
  • present processes which utilize both atmospheric BPSG layers and chemical mechanical tungsten plug processes are unreliable and unmanufacturable.
  • the present invention describes a method of forming a novel interconnection structure for an integrated circuit.
  • a first oxide layer comprising boron and phosphorous formed by atmospheric CVD is deposited over the semiconductor substrate.
  • the first oxide layer is then chemically mechanically polished (CMP) to form a planarized surface.
  • CMP chemically mechanically polished
  • a second undoped oxide layer formed by plasma enhanced CVD is deposited on the planarized first oxide layer.
  • An opening is then etched through the first and second oxide layers.
  • a conductive layer comprising tungsten is then deposited into the opening and over the second oxide layer.
  • the conductive layer is polished back from the second oxide layer to form a filled opening which is substantially planar with the second oxide layer.
  • Figure 1 is an illustration of a cross-sectional view showing a prior art interconnection structure.
  • Figure 2a is an illustration of a cross-sectional view showing a semiconductor substrate having a plurality of devices formed thereon.
  • Figure 2b is a cross-sectional illustration of a semiconductor substrate showing the formation of a first interlayer dielectric on the substrate of Figure 2a.
  • Figure 2c is an illustration of a cross-sectional view showing the planarization of the first interlayer dielectric on the substrate of Figure 2b.
  • Figure 2d is a cross-sectional illustration showing the formation of a second interlayer dielectric on the substrate of Figure 2c.
  • Figure 2e is an illustration of a cross-sectional view showing the formation of openings in the substrate of Figure 2d.
  • Figure 2f is an illustration of a cross-sectional view showing the formation of a via fill material on the substrate of figure 2e.
  • Figure 2g is an illustration of a cross-sectional view showing the polishing of the via fill material on the substrate of Figure 2f to form filled contact openings.
  • Figure 2h is an illustration of a cross-sectional view showing the formation of a level of metallization on the substrate of Figure 2g.
  • the present invention discloses a novel method of fabricating an interconnection structure in an integrated circuit.
  • numerous specific details such as specific process steps, materials, and dimensions, etc. are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well known integrated circuit manufacturing steps and equipment have not been set forth in detail in order to not unnecessarily obscure the present invention.
  • the present invention is a novel method of forming an interconnection structure for an integrated circuit.
  • the preferred embodiment of the present invention enables an atmospheric chemical vapor deposited BPSG layer to be used with a tungsten plug process utilizing chemical mechanical polishing (CMP) to provide a manufacturable, high density interconnect structure.
  • CMP chemical mechanical polishing
  • a semiconductor substrate 200 is provided.
  • Devices 202 such as metal oxide semiconductor (MOS) transistors are formed in the semiconductor substrate 200.
  • MOS metal oxide semiconductor
  • suicide is formed by a self-aligned process on the source, drain, and poly gates of the MOS devices to improve contact resistance and device performance.
  • the active devices are initially isolated from one another by field oxide regions 204.
  • substrate 200 may contain other completed or partially completed active and passive devices such as, but not limited to, bipolar transistors, thin film transistors, capacitors, and resistors, etc.
  • semiconductor substrate 200 is preferably a monocrystalline silicon substrate, substrate 200 can comprise other semiconductor material such as, but not limited to, gallium arsenide and germanium and may contain additional deposited semiconductor materials such as epitaxial silicon layers.
  • the first step according to the present invention is to form an interlayer dielectric (ILD) 206 over substrate 200 and devices 202 formed thereon.
  • ILD 206 is to electrically isolate devices 202 from subsequently formed metallization used to interconnect the devices into a functional circuit.
  • ILD 206 is preferably a borophosphosilicate glass (BPSG) formed by atmospheric chemical vapor deposition (CVD).
  • BPSG borophosphosilicate glass
  • CVD atmospheric chemical vapor deposition
  • An atmospheric BPSG layer is preferred because it can be formed conformally to the underlying topography and therefore fill small gaps between adjacent devices 202 without creating voids therein.
  • ILD 206 is preferably formed by atmospheric CVD in a WJ999 TEOS machine using a tetraethyl orthosilicate (TEOS), oxygen (O2), phosphine (PH3) and diborane (B2H6) chemistry to produce a silicon dioxide (Si ⁇ 2) film with an approximately 3% boron and 6.3% phosphorous concentration. An approximately 18,000A oxide layer is formed.
  • TEOS tetraethyl orthosilicate
  • O2 oxygen
  • PH3 phosphine
  • B2H6 diborane
  • ILD 206 is preferably densified using rapid thermal processing (RTP).
  • RTP rapid thermal processing
  • One of the goals of densifying ILD 206 is to accelerate the incorporation of dopants into the oxide to stabilize it.
  • steam flow processing can be eliminated.
  • the use of steam flow processing is undesirable because it grows a thin oxide at the BPSG /suicide interface which consumes a substantial portion of the suicide during its growth.
  • no oxide grows at the BPSG /suicide interface, enabling the scaling of suicide thickness formed on the source drain regions to accompany scaling of the source drain junction depths.
  • the use of RTP for densification improves the thermal budget, and in turn, transistor performance over steam furnace glass flow cycles.
  • the RTP process is preferably performed at a temperature less than 875 ° in order to prevent agglomeration of the suicides. That is suicide 203 cannot tolerate higher densification temperatures.
  • the top surface 208 of ILD 206 is nonplanar due to the underlying topography created by devices 202 and isolation regions 204.
  • the nonplanar topography is due to the conformal deposition nature of BPSG layer 206. Additionally, the nonplanar topography is also due to the fact that steam flow processing is preferably not used in the present invention. Steam flow steps generally help to smooth or planarize the topography of BPSG layers. Because the top surface 208 of ILD 206 is nonplanar, it is planarized as shown in Figure 2c. ILD 206 is preferably planarized by chemical mechanical polishing because it creates global planarization as opposed to only local planarization associated with reflow and etch back processes.
  • ILD 206 is preferably polished back from 18,OO ⁇ A to approximately 4500 A ⁇ 1500 A over devices 202 to form a planar surface 210. By initially forming ILD 206 very thick, a good amount of margin is provided for the chemical mechanical polishing process.
  • ILD 206 is chemically mechanically polished using a slurry comprising silica in a solution of potassium hydroxide and water (KOH + H2O) using a Westech 372M polisher. It is to be appreciated however, that any well known CMP process can be used to planarize ILD 206.
  • ILD 206 Global planarization of ILD 206 is desired because it forms a very planar ILD surface 210 which enables the shrinking of metal lines, as well as increasing the number of metallization layers which may be used in a process. It is to be appreciated that the stacking of additional interconnection layers on top of one another produces a more rugged topography. Because of the planarization of ILD 206, fabrication problems such as poorly resolved contact/ via openings, and /or metal lines, poor metal step coverage, electromigration, and metal stingers are reduced in the present invention.
  • ILD 212 is deposited onto ILD layer 206 as shown in Figure 2d.
  • ILD 212 is formed of a different dielectric material than ILD 206.
  • ILD 212 is a material which polishes significantly slower (8x) than does ILD 206 during a subsequent polishing step for plug formation.
  • ILD 212 and ILD 206 together form a composite ILD 214 which is used to isolate subsequent electrical connections.
  • the final total thickness of composite ILD 214 must be sufficient to electrically isolate subsequently formed metallization from devices 202. Because ILD 212 is formed thin, approximately 2000 A, and is formed on a planarized surface 210 of ILD 206, composite dielectric 214 exhibits a very planar top surface 215 without any additional planarization.
  • ILD 212 is preferably an undoped oxide layer formed by plasma enhanced chemical vapor deposition (PECVD) utilizing TEOS and ⁇ 2 source gases in an AMAT 5000 deposition machine.
  • PECVD undoped oxide layer 214 can be formed uniformly and consistently enough to provide a planar capping layer 212 for planarized ILD layer 206 used to fill the high aspect gaps between adjacent devices 202.
  • a valuable characteristic of plasma enhanced CVD processes is that they form dense dielectric layers. Dense oxide layers tend to polish at a slower rate than do less dense oxide layers such as doped atmospherically deposited CVD oxide layers.
  • openings 216 are formed through ILD 206 and ILD 212. Openings 216 provide vias or contact openings to allow electrical connections through ILD 206 and ILD 212 to devices 202 formed below. Any well known method can be used to form openings 216 such as reactive ion etching (RIE) in a LAM Research 4500 etcher with a freon based chemistry.
  • RIE reactive ion etching
  • devices 202 must be packed closely together necessitating the formation of narrow (approximately 0.4 microns wide) and closely spaced contact/via openings 216. Since composite ILD 214 must be sufficiently thick to isolate devices 202 and because of the desire to form narrow openings, high aspect ratio (i.e. deep and narrow openings) are preferably formed. The best method presently available to fill such high aspect ratio openings is to use plug technology.
  • a contact fill material 218 is blanket deposited over undoped oxide layer 212 and into opening 216.
  • the preferred contact fill material 218 is tungsten because it can be formed very conformally allowing for the filling of high aspect ratio openings without the creation of voids therein.
  • a thin composite titanium/ titanium nitride adhesion layer is used.
  • an approximately 20 ⁇ A titanium layer 222 is sputter deposited by well known means over ILD 212 and along the sidewalls and bottom of openings 216.
  • an approximately 60 ⁇ A titanium layer 224 is sputter deposited by well known means over titanium layer 222.
  • a conformal layer of tungsten 220 is formed by first forming an initial seed layer of (approximately 30 ⁇ A) of tungsten by CVD using a silane (SiH4) reduction of tungsten hexafluoride WF ⁇ ) followed by the formation of the bulk (approximately 4500A) of the tungsten layer by CVD using a hydrogen (H ) reduction of WF ⁇ .
  • contact fill material 218 preferably comprises a tri-layer metal comprising titanium, titanium nitride, and tungsten. It is to be appreciated that other contact fill materials a combination of materials may be used to fill openings 216.
  • contact fill material 218 is chemically mechanically polished back to remove contact fill material 218 from the top surface of ILD 212 and to thereby form a filled opening or plug 226 which is substantially planar with the top surface of ILD 214.
  • the contact fill material is tungsten
  • the tungsten layer is preferably chemically mechanically polished back using a chemistry comprising 0.01 to 0.3 molar potassium fericyanide (K3Fe(CN6)) and 1-25% silica by weight.
  • K3Fe(CN6) potassium fericyanide
  • a water diluted version (9:1) of the tungsten slurry can be used to polish off titanium nitride adhesion layer 224.
  • a slurry comprising approximately 0.5 molar potassium fluoride and approximately 0.5% silica by weight is preferably used to polish off titanium adhesion layer 222 from ILD 212.
  • the above specified slurries are preferred in the present invention because they allow for uniform and consistent polishing of tungsten layer 220 and adhesion layers 222 and 224 and the formation of a plug 226 without substantially recessing plug 226 beneath ILD 212 or without causing an "etch out" of plug 226. Details on the methodology and slurries for polishing tungsten, titanium nitride and titanium film utilizing the above specified slurries are described in full in U.S. Patent No. 5,340,370 assigned to the present assignee, which is hereby incorporated by reference.
  • An important aspect of the present invention is for the plug polishing process to be selective to ILD capping layer 212. That is, it is important for ILD capping layer 212 to polish at a rate significantly slower than contact fill material 218. In this way, nonuniformities exists across substrate 300, those areas which clear contact material first to reveal ILD 212 will essentially stop polishing (or least retard the polishing) while other areas with contact fill material still present will continue to polish.
  • Capping layer 212 allows "overpolishing" to be utilized in the present invention to assure substantially complete removal of contact fill material 218 across the entire substrate 300 without significantly polishing away local areas of ILD 214. In this way, a plug polishing process can be reliably utilized without worrying about overpolishing causing excessive ILD loss.
  • capping layer 212 can be completely polished off during plug formation. Capping layer 212 should provide enough selectivity to sufficiently retard the polishing process to preserve enough ILD to fabricate reliable interconnects.
  • the tungsten polishing process exhibits about a 32:1 tungsten to PECVD oxide selectivity- The use of ILD capping layer 212 makes the interconnection process of the present invention both manufacturable and reliable.
  • polish rates and selectivities provided herein were calculated by polishing thin films blanket deposited over -li ⁇ an entire wafer. Selectivities on portions of the substrate will actually be much lower due to a "dishing" effect which occurs during plug polishing. "Dishing” is due to the fact that ILDs between densely placed contacts polish much faster than do ILDs between less densely placed contacts. As such, “dishing” causes a substantial reduction in polish selectivity in areas with a high density of contacts. Thus, care should be taken to ensure that capping layer 212 provides enough selectivity to counter any "dishing" effect.
  • ILD capping layer 212 is an undoped oxide layer formed by plasma enhanced CVD.
  • Plasma enhanced CVD processes produce dense oxide layers. While atmospheric CVD processes produce oxide layers which are substantially less dense. Additionally, doped oxide layers tend to be less dense than undoped oxide layers. Dense oxide layers generally polish at slower rates than do less dense oxide layers.
  • undoped PECVD oxide capping layer 212 polishes about eight times slower during tungsten plug polishing than does doped atmospheric CVD oxide layer 206 used for the bulk of composite ILD 214.
  • undoped PECVD oxide capping layer 212 on doped atmospheric CVD oxide layer 206, the tungsten plug polishing process is much more selective to composite ILD 214 than if only a doped atmospheric CVD oxide layer were utilized. It is to be appreciated, that although atmospheric BPSG layers are incompatible with tungsten polishing processes, they are required to fill small aspect ratio gaps created by high density placement of devices 202. Additionally BPSG layers formed by atmospheric CVD are significantly more economical than PECVD oxides because they require less expensive machinery and because they can be formed faster (i.e. the)' provide better wafer throughput). The use of a thin undoped PECVD oxide capping layer 212 enables the use of a low density, high aspect ratio filling atmospheric CVD BPSG layer with a tungsten plug process. 2393 PCI7US96/15201
  • Atmospheric BPSG layers are used to fill high aspect ratio gaps created by dense placement of devices 202 and tungsten plugs are used to fill high aspect ratio contact openings necessary to make contact to the densely placed devices 202.
  • Interconnects 230 can be formed by any well known means such as by blanket depositing an aluminum layer (and adhesion layers if desired) over ILD 212 and plugs 226 and then etching the aluminum layers into individual metal lines 230 utilizing well known photolithographic techniques. At this point, the interconnection structure of the present invention is complete.
  • a very planar high density interconnection structure has been fabricated. Because plug 226 is substantially planar with ILD 214, a planar interconnection layer 230 is formed. It is to be appreciated that the present invention can be utilized to form additional interconnection and via /contact layers if desired. Because of the very planar nature of the interconnect scheme of the present invention and almost unlimited number of metallization layers can be fabricated allowing for the interconnection of a large number of discrete devices formed in a semiconductor substrate such as required in ULSI circuits.
  • the present invention has been described with respect to a preferred embodiment where a PECVD oxide capping layer is formed over an atmospheric CVD BPSG layer in order to increase the ILD selectivity to a tungsten plug process, it is expected that the concepts of the present invention may be applied to other semiconductor processes. That is, the present invention can generally be applied to any process which utilizes a chemical mechanical polishing (CMP) process to polish back one material to fill an opening in a second material and where the selectivity of the polishing process is not sufficiently selective to the second material to provide a robust process. In such cases, a suitable capping layer is provided to increase the selectivity of the polishing process to provide a reliable process.
  • CMP chemical mechanical polishing
  • the present invention can be used to form interconnects, such as interconnects 230, by blanket depositing an aluminum layer over an ILD with an opening formed therein and then polishing back the aluminum layer to form metal interconnects.
  • the present invention can be used to increase the selectivity in a CMP process used to fill trenches for isolation or to form capacitors.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé permettant de constituer une nouvelle structure d'interconnexion de haute densité. On commence par constituer une première couche isolante sur un substrat semi-conducteur (206) et on la planarise. On forme une seconde couche isolante (212) au-dessus de la première couche isolante planarisée. On grave un orifice au travers de la première et de la seconde couches isolantes. On dépose un matériau conducteur (226) dans l'orifice et à la surface supérieure de la seconde couche isolante. On retire par polissage le matériau conducteur de la seconde couche isolante de façon à constituer un orifice rempli de matériau conducteur qui soit sensiblement au même niveau que la seconde couche isolante.
EP96933088A 1995-09-29 1996-09-23 Couche intermediaire dielectrique coiffee pour polissage chimico-mecanique Withdrawn EP1008175A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US53600795A 1995-09-29 1995-09-29
US536007 1995-09-29
PCT/US1996/015201 WO1997012393A1 (fr) 1995-09-29 1996-09-23 Couche intermediaire dielectrique coiffee pour polissage chimico-mecanique

Publications (2)

Publication Number Publication Date
EP1008175A1 true EP1008175A1 (fr) 2000-06-14
EP1008175A4 EP1008175A4 (fr) 2000-10-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP96933088A Withdrawn EP1008175A4 (fr) 1995-09-29 1996-09-23 Couche intermediaire dielectrique coiffee pour polissage chimico-mecanique

Country Status (8)

Country Link
EP (1) EP1008175A4 (fr)
JP (1) JPH11512877A (fr)
KR (1) KR19990063743A (fr)
CN (1) CN1203697A (fr)
AU (1) AU7164596A (fr)
IL (1) IL123749A0 (fr)
TW (1) TW304297B (fr)
WO (1) WO1997012393A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6153935A (en) * 1999-09-30 2000-11-28 International Business Machines Corporation Dual etch stop/diffusion barrier for damascene interconnects
US7316972B2 (en) 2002-08-30 2008-01-08 Matsushita Electric Industrial Co., Ltd. Contact hole formation method
US7521364B2 (en) * 2005-12-02 2009-04-21 Macronix Internation Co., Ltd. Surface topology improvement method for plug surface areas
US8067762B2 (en) 2006-11-16 2011-11-29 Macronix International Co., Ltd. Resistance random access memory structure for enhanced retention
DE102007063271B4 (de) 2007-12-31 2009-11-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines dielektrischen Zwischenschichtmaterials mit unterschiedlichen Abtragsraten während eines CMP-Prozesses

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPH01293632A (ja) * 1988-05-23 1989-11-27 Nec Corp 半導体装置
EP0540321A1 (fr) * 1991-10-30 1993-05-05 Samsung Electronics Co. Ltd. Procédé de fabrication de la couche intermédiaire diélectrique d'un dispositif semi-conducteur
US5340370A (en) * 1993-11-03 1994-08-23 Intel Corporation Slurries for chemical mechanical polishing

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Publication number Priority date Publication date Assignee Title
JPH0680638B2 (ja) * 1990-07-05 1994-10-12 株式会社東芝 半導体装置の製造方法
EP0469214A1 (fr) * 1990-07-31 1992-02-05 International Business Machines Corporation Procédé pour la fabrication de domaines en polysilicium conducteur et/ou résistant en couches superposées dans des dispositifs à semiconducteurs multiniveaux et structures résultantes
US5164340A (en) * 1991-06-24 1992-11-17 Sgs-Thomson Microelectronics, Inc Structure and method for contacts in cmos devices
US5244837A (en) * 1993-03-19 1993-09-14 Micron Semiconductor, Inc. Semiconductor electrical interconnection methods
US5409858A (en) * 1993-08-06 1995-04-25 Micron Semiconductor, Inc. Method for optimizing thermal budgets in fabricating semiconductors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293632A (ja) * 1988-05-23 1989-11-27 Nec Corp 半導体装置
EP0540321A1 (fr) * 1991-10-30 1993-05-05 Samsung Electronics Co. Ltd. Procédé de fabrication de la couche intermédiaire diélectrique d'un dispositif semi-conducteur
US5340370A (en) * 1993-11-03 1994-08-23 Intel Corporation Slurries for chemical mechanical polishing

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 082 (E-0889), 15 February 1990 (1990-02-15) & JP 01 293632 A (NEC CORP), 27 November 1989 (1989-11-27) *
See also references of WO9712393A1 *

Also Published As

Publication number Publication date
JPH11512877A (ja) 1999-11-02
IL123749A0 (en) 1998-10-30
TW304297B (fr) 1997-05-01
AU7164596A (en) 1997-04-17
CN1203697A (zh) 1998-12-30
KR19990063743A (ko) 1999-07-26
WO1997012393A1 (fr) 1997-04-03
EP1008175A4 (fr) 2000-10-18

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