EP0999483B1 - Method for adjusting the frequency of a clock module by means of fuses melted using a laser beam - Google Patents

Description

The present invention relates to a method for adjusting the running of a watch module, said watch module including a quartz and an integrated circuit comprising a quartz-driven oscillator, a multi-stage frequency divider circuit, a adjustment circuit for introducing a factor for correcting the rate of division of said frequency divider circuit and a memory circuit containing information representative of said correction factor.

By "gait adjustment method" is meant a method of introducing a factor of correction of the division ratio of the frequency divider circuit, so that the frequency of the pulses delivered at the output thereof is corrected. so as to be in a predetermined range.

By "module", one will also hear a semi-finished or intermediate system, ready to be mounted in the final product. In particular, by "watch module", will be understood in the following description, a printed circuit comprising different electronic components, in particular quartz and the aforementioned integrated circuit.

Adjusting the frequency of the oscillator, particularly a crystal oscillator, is a particularly complicated and delicate operation. Indeed, as stated in the disclosure CH 534 913 this adjustment is carried out according to a first coarse adjustment step by precision mechanical operations on the quartz, then a second step of fine adjustment on the encapsulated quartz, and finally according to a final step of adjustment and compensation of the aging by an adjustment system or trimmer.

These steps have the disadvantages of being delicate and complex, which greatly influences the cost of the part. On the other hand, the frequency stability of the quartz is substantially deteriorated. Therefore, the patent CH 534 913 proposes a satisfactory and inexpensive solution, acting directly on the division rate of the frequency divider circuit by the introduction of a correction factor, the effect of which is to improve the stability of the quartz and to overcome the use of a trimmer. For this purpose, the frequency divider circuit proposed in the patent CH 534 913 presents auxiliary electrical inputs whose logic state determines the division ratio of the frequency divider and a memory circuit, connected to these auxiliary inputs, for retaining in coded form information representative of the correction factor of the division ratio of the divider circuit of the frequency.

The system that has just been mentioned operates by inhibition or periodic suppression of a given number of pulses delivered by the oscillator. It will be mentioned that a system operating alternatively by adding a determined number of pulses is furthermore proposed in the patent. CH 558 559 .

Whatever the chosen system, the adjustment circuit is typically connected to a memory circuit containing the information representative of the factor of correction of the division rate. The storage of this information is preferably nonvolatile so that it is not lost during a battery change or during an interruption of the power supply.

Various embodiments of the memory circuit are known from the prior art. In particular, one generally opts for solutions using reprogrammable non-volatile memories (EPROMs / EEPROMs) or additional contact pads.

The use of an EPROM / EEPROM requires a significant investment in terms of integrated circuit surface, because such memory must not only include a sufficient number of bits to encode the information representative of the correction factor, but also requires the implementation of programming logic to program it and a voltage multiplier circuit to produce the high voltages necessary for this programming. This obviously translates into a substantial increase in the manufacturing cost of the integrated circuit due in particular to the additional steps necessary for the integration of the EPROM / EEPROM and has repercussions on the manufacturing cost of the watch module and the timepiece. as such.

The use of additional contact pads also requires a large investment surface (a contact area per bit) and additional connection tracks on the printed circuit.

The implementation of such contact areas also leads to an increase in the manufacturing cost of the integrated circuit and the watch module.

It will be noted that the relative cost of the aforementioned solutions essentially depends on the circuit surface, the number of bits and the additional manufacturing cost due to the possible integration of an EPROM / EEPROM.

It will be mentioned, moreover, that the higher the surface of the circuit, the lower the cost of the surface investment, whatever the solution chosen, is proportionally small and becomes negligible for a circuit of a few tens of mm ² .

On the other hand, the relative cost related to the additional manufacturing steps of an EPROM / EEPROM remains constant as a function of the surface and thus constitutes the determining element for large circuits. In other words, the additional cost of implementing the EPROM / EEPROM bits is substantially proportional to the circuit surface, which is why the solution employing contact pads additional is more economical for large circuits.

For small circuits (a few mm ² ) the choice is much more questionable. Surface investment becomes proportionally important.

An EPROM / EEPROM bit requires less area than an additional contact area, but nevertheless generates a fixed investment due in particular to the programming logic and the voltage multiplier. Thus, the higher the number of bits, the more economical the EPROM / EEPROM solution is at the surface compared to the solution employing additional contact pads. On the other hand, the manufacturing cost per unit area remains proportionally higher.

In practice, for circuits of a few mm ² , the surface advantage of the EPROM / EEPROM solution balances the additional manufacturing costs and the two solutions are thus economically comparable.

For example, it should be noted that the request for FR 2,238,280 discloses an integrated oscillator and its digital frequency tuning method including memory elements programmable from outside the integrated circuit. These elements are diodes some of which are short-circuited in order to modify their state permanently. Each element is connected to a terminal of the integrated circuit.

According to the patent CH 534 913 already cited, it is proposed to use a memory circuit consisting of a plurality of individual memory elements, for example electrically alterable, each associated with a programming terminal of the integrated circuit.

According to the patent CH 621 036 there is described yet another integrated system for adjusting the division ratio of a frequency divider circuit. This integrated system comprises memory circuits comprising a diode in series with a memory element formed of a fuse consisting of a particular metallization of the integrated circuit that can be destroyed by passing it over. integrated circuit comprises memory circuits comprising a diode in series with a memory element formed of a fuse consisting of a particular metallization of the integrated circuit that can be destroyed by passing a current of some importance. Each memory element can be addressed separately by means of the diodes by applying between the terminals of the integrated circuit a particular combination of voltages.

It will be seen that the solutions proposed in the above-mentioned patents necessarily require the use of existing and / or additional connection terminals of the integrated circuit so as to allow storage of the correction factor. Some solutions also sometimes require the disconnection of certain elements, including the power source, when programming the memory which makes the programming operation sometimes complex and time consuming.

A solution to reducing the number of connection terminals is defined in the EP 0 645 689 which describes a system for providing clock signals. This system comprises a crystal oscillator whose frequency can be divided by at least one frequency divider circuit, in particular for a frequency synthesizer. The system also includes a memory circuit having fusible elements, which can be cut by a laser beam so as to adjust the output frequency of the divider circuit (s). However, this patent does not describe a gait adjustment method of a watch module.

An object of the present invention is therefore to propose a method of adjusting the step of a watch module that does not require a complex implementation at the integrated circuit, so that the manufacturing cost of the latter, and therefore the module as such, is not greatly affected.

Another object of the present invention is to propose a method of adjusting the step of a a watch module particularly adapted to mass or automated production of watch modules, ie a simple and quick adjustment process.

For this purpose, the present invention relates to a method for adjusting the step of a watch module as defined in claim 1.

An advantage of the present invention lies in the fact that the storage of the information representative of the correction factor is performed in a simple and above all fast manner, therefore particularly suitable for the mass production of such modules. The speed and simplicity of the adjustment method according to the present invention thus ensures a substantial reduction in manufacturing costs.

It will be further noted that the present invention also has the advantage of allowing the adjustment of the step of a watch module, that is to say a finite or intermediate set comprising other electronic components that the quartz, the oscillator, the circuit frequency divider, dividing rate adjusting circuit, or memory circuit. In this way, the adjustment can be made taking into consideration the influences of all the electronic components of the module.

Another advantage of the present invention lies in the fact that the cost of the integrated circuit and the watch module as such is not substantially affected. In particular, the use of memory elements formed of laser destructible fuses does not require a complex and expensive implementation at the level of the integrated circuit.

• la figure 1 représente un schéma bloc d'un module horloger comportant un quartz, un oscillateur, un circuit diviseur de fréquence, un circuit d'ajustement et un circuit mémoire;
• les figures 2a à 2c présentent divers exemples d'implémentation d'un circuit mémoire 6 bits comprenant des éléments mémoires formés de fusibles destructibles par laser.

Other features and advantages of the present invention will appear on reading the description which follows, made with reference to the accompanying drawings, given solely by way of example, and in which:

• the figure 1 represents a block diagram of a watch module comprising a quartz, an oscillator, a frequency divider circuit, an adjustment circuit and a memory circuit;
• the Figures 2a to 2c present various examples of implementation of a 6-bit memory circuit comprising memory elements formed of lasable destructible fuses.

The figure 1 is a schematic representation of a watch module comprising a printed circuit 1 including a quartz 10 and an integrated circuit 20. This integrated circuit 20 comprises an oscillator 21 controlled by the quartz 10 so as to typically deliver pulses at a frequency of 32768 Hz. This frequency is divided several times by a frequency divider circuit 22 so as to output at its output pulses at a frequency of 1 Hz and thus allow the formation and display of a time indication.

In the example shown in figure 1 , the frequency divider circuit 22 thus comprises a total number of 15 binary division stages 22.1 to 22.15. The first two stages 22.1 and 22.2 make it possible in particular to deliver a signal at a frequency of 8192 Hz which is used to enable correction of the division ratio of the frequency divider circuit 22.

An adjustment circuit 23 allows for this purpose the introduction of a correction factor of the rate of division of the frequency divider circuit 22. A memory circuit 24 thus contains information, generally in the form of a binary number N, representative of the factor of correction of the division ratio of the frequency divider circuit 22.

It will be recalled that various techniques for adjusting the division ratio are known from the prior art. One of them, described in the patent CH 534 913 so-called inhibition technique consists in suppressing a number N of pulses during a given period. The following description is based on such a technique, but it will be understood of course that the invention may be extended by analogy with other known techniques such as that of adding a number of missing pulses.

The adjustment method essentially consists in correcting the frequency difference existing between the frequency of the oscillator 21 and the frequency delivered by a standard oscillator, this frequency difference being measured in ppm (parts per million). This frequency difference can be corrected, according to the inhibition technique, by the deletion of a number N of pulses of period T _i during a determined period T _h , the so-called inhibition period.

In the example of the figure 1 , the inhibition is carried out at the output of the first two division stages 22.1 and 22.2 of the frequency divider circuit 22, or from pulses delivered at a frequency of 8192 Hz (T _i = 122 μs). By performing the inhibition periodically, for example every 60 seconds, the resolution of the system thus reaches 2.03 ppm.

With such a resolution and so as to obtain a sufficient correction range, for example of the order of 100 ppm, it will be found therefore that the number N will require at least 6 bits of memory. In practice, depending on the application, this number may require between 4 and 9 bits.

According to the present invention, the memory circuit 24 comprises memory elements formed of lasable destructible fuses. The figure 2a illustrates a first example of a 6-bit memory circuit comprising 6 memory elements 24.1 to 24.6 connected in parallel and each having a pair of fuses F1 and F2 laser destructible. The fuses F1 and F2 of each memory element are connected in series between a potential line "high" Vdd and a potential line "low" Vss. The destruction of one of the fuses F1 or F2 thus makes it possible to put the intermediate point situated between the fuses F1, F2 at the high potential Vdd or low Vss respectively. The coding of information (number N) representative of the correction factor of the division ratio of the frequency divider circuit 22 can thus easily be achieved by means of a laser by destroying one or the other of the fuses F1 or F2. .

The figure 2b presents a second example of a 6-bit memory circuit comprising 6 memory elements 24.1 to 24.6 each having a laser destructible fuse F.1 to F.6 associated with an interface circuit L.1 to L.6. The interface circuit L and the fuse F are connected in series between a "high" potential line Vdd and a "low" potential line Vss. The interface circuit may be realized by those skilled in the art in a conventional manner in the form of a latch for copying the input state defined by the fuse. For this purpose, the lock further comprises a loading input CKP on activation from which an output Lout of the lock takes the corresponding state defined by the state of the associated fuse. In this case, the output Lout of the lock takes the state "high" if the fuse is destroyed and the state "low" if the fuse is intact.

The Figure 2c shows yet another example of a 6-bit memory circuit. This solution partially integrates a logic of inhibition of the frequency divider circuit 22. The six memory elements 24.1 to 24.6, connected in series, each comprise a fuse F.1 * to F.6 * connected in parallel with a transistor T1 to T6. Each transistor is respectively controlled by the clock signals of the six division stages of the frequency divider circuit 22 on which the inhibition is carried out in accordance with what has been previously described.

If the fuse is intact, the transistor is short-circuited and the clock signal at its input has no effect. If the fuse is destroyed, the transistor can then have an effect on the inhibition of the frequency divider circuit 22. By the selective destruction of certain fuses among the fuses F.1 * to F.6 *, it is thus possible to adjust the inhibition rate of the frequency divider circuit 22.

It will be seen that the use of laser destructible fuses is a substantial advantage over the use of current destructible fuses. Indeed, the fuses can be selectively destroyed directly on the integrated circuit by means of a laser device. This process does not require the use of terminals and special addressing means. The use of laser destructible fuses is also much more economical than all known solutions because it does not imply a significant investment in terms of area at the level of the integrated circuit.

No additional manufacturing cost is additionally generated in the integrated circuit, because the production of such fuses can easily be performed simultaneously during one of the manufacturing steps of the integrated circuit 20. The integration of an EPROM / EEPROM or additional contact pads would imply, as already mentioned, an additional manufacturing cost.

The use of laser destructible fuses is not, however, directly necessary as the most appropriate solution for the skilled person. Indeed, the skilled person is faced with various constraints and difficulties related to the use of laser destructible fuses. In the rest of the description, we will try to describe briefly these constraints and difficulties.

A first constraint resides in the fact that the use of a laser beam for selectively destroying the fuses on the integrated circuit implies that this operation must be carried out before the deposition of the protective resin thereon. It is indeed not conceivable to carry out the destruction of the fuses by means of the laser through the protective resin, which in this case should be transparent, since this would have the effect of totally annihilating the interest of such a device. deposit, or in particular the protection of the integrated circuit against ambient impurities and light.

In addition, it will be seen that the subsequent deposition of this protective resin causes changes in the electrical characteristics of the integrated circuit and therefore in the frequency characteristics of the latter. It is therefore necessary to compensate for this influence when calculating the correction factor of the frequency divider circuit.

Another constraint lies in the fact that the lighting conditions also have a significant influence on the characteristics of the integrated circuit. The adjustment operation, in particular the operation of measuring the step of the module, is thus preferably carried out under clearly defined lighting conditions.

The method of adjusting the step of the watch module according to the present invention requires a preliminary preparation phase before performing the actual adjustment of the step.

The preparation phase consists in previously implementing the number of fuses necessary to allow the coding of the information (number N) representative of the factor of correction of the division ratio of the frequency divider circuit according to what has been previously described.

This preparation phase also consists in mounting the various electronic components on the module, in particular the quartz and the integrated circuit without applying the protective resin on the integrated circuit (so-called "potting" operation).

Following this preliminary phase, the module is ready to undergo the adjustment operation itself.

The adjustment phase thus consists in measuring, by means of external equipment, the march of the watch module, that is to measure the variation of the frequency of the quartz oscillator with respect to the frequency of a standard oscillator as this has been done. described above.

In order not to disturb the characteristics of the integrated circuit, this measurement is preferably carried out under clearly defined lighting conditions.

From this frequency difference, a correction factor is calculated. It will be recalled that this correction factor is determined by calculating a corresponding number N, in the case of an inhibition technique, to the number of pulses to be suppressed during a given period T _h .

It will also be mentioned that when calculating the correction factor, the various influences of the environment, in particular the illumination conditions, and the subsequent deposition of the protective resin will be taken into account. This influence can be estimated experimentally by a series of preliminary tests to define an offset value. This offset value is then considered when calculating the correction factor.

The next step consists in memorizing the information (number N) representative of the calculated correction factor. For this purpose, the watch module is aligned under a laser device. In particular, it will be ensured to align the laser device essentially with respect to an integrated circuit zone comprising the laser destructible fuses.

Once this alignment operation has been performed, the laser device is activated to selectively destroy the fuses necessary for encoding the information (number N) representative of the correction factor.

Once the coding operation has been performed, the protective resin can then be deposited on the integrated circuit.

Steps subsequent to this adjustment phase, including in particular a final test step of the step of the watch module are then performed.

The gait adjustment method of a watch module according to the present invention thus proves particularly suitable for the mass production and automation of such an operation. It will be seen that the adjustment method according to the present invention thus allows a great simplification of the manufacturing process and also a substantial gain in terms of manufacturing costs.

It will be understood that many modifications can be made to the method of adjusting the step of a watch module without departing from the scope of the present invention as defined by the claims. This invention is thus not only limited to the adjustment of the march of a watch module according to the inhibition technique but also applies by analogy to the pulse addition adjustment technique.

Claims (2)

1. Method for adjusting the rate of a horological module, said horological module including a printed circuit (1) on which are mounted in particular a quartz (10) and an integrated circuit (20) including:

   - an oscillator (21) driven by said quartz (10),

   - a frequency divider circuit (22),

   - an adjustment circuit (23) allowing a correction factor of the rate of said horological module to be introduced into said frequency divider circuit (22), and

   - a memory circuit (24) containing data (N) representing said correction factor, the memory circuit including memory elements (24.1 to 24.6) formed of fuses (F1, F2; F.1 to F.6; F.1* to F.6*) which can be destroyed by laser,

   this method including the following steps:

   a) mounting said integrated circuit (20) on said printed circuit (1) without depositing a protective resin;

   b) measuring the rate of said horological module;

   c) calculating said correction factor of the rate of said horological module;

   d) storing said data (N) representing said correction factor in said memory circuit (24),

   the storage step d) including the following steps:

   d1) aligning the module under a laser device;

   d2) destroying, by means of said laser device, said fuses (F1, F2; F.1 to F.6; F.1* to F.6*) necessary for coding said data (N) representing the correction factor of the rate of the horological module;

   this storage step d) being further followed by the following step:

   e) depositing said protective resin over said integrated circuit (20),

   said correction factor calculated at step c) further including an offset value generated by the subsequent deposition of said protective resin at step e).
2. Method for adjusting the rate of a horological module according to claim 1, characterised in that the method is performed in determined lighting conditions so that the measurement of the rate of said horological module at step b) is not disturbed.

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