EP0990266B1 - Transistor hyperfrequence a structure quasi-autoalignee et son procede de fabrication - Google Patents
Transistor hyperfrequence a structure quasi-autoalignee et son procede de fabrication Download PDFInfo
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- EP0990266B1 EP0990266B1 EP98929532A EP98929532A EP0990266B1 EP 0990266 B1 EP0990266 B1 EP 0990266B1 EP 98929532 A EP98929532 A EP 98929532A EP 98929532 A EP98929532 A EP 98929532A EP 0990266 B1 EP0990266 B1 EP 0990266B1
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- layer
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- sticker
- polycrystalline silicon
- silicon
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- 238000000034 method Methods 0.000 title claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 238000010292 electrical insulation Methods 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910015900 BF3 Inorganic materials 0.000 claims description 4
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 4
- 238000007669 thermal treatment Methods 0.000 claims 3
- 238000010438 heat treatment Methods 0.000 description 13
- 238000009413 insulation Methods 0.000 description 13
- 229910052796 boron Inorganic materials 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 9
- 238000002513 implantation Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000009776 industrial production Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
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- 230000007547 defect Effects 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
Definitions
- the present invention relates to a transistor bipolar of the type with a quasi-self-aligned structure and a process for producing such a transistor. She relates more specifically to the manufacture of microwave bipolar transistors. So, the invention is part of the technical field of microelectronics on silicon, especially for manufacture of bipolar integrated circuits and BiCMOS (Bipolar Complementary Metal Oxide Semiconductor).
- BiCMOS Bipolar Complementary Metal Oxide Semiconductor
- the invention finds applications in the realization of logic, analog and particular of radio frequency circuits.
- transistors self-aligned double-polysilicon structures These transistors are among the most efficient in the in terms of speed of operation. Their high operating speed is precisely linked to self-aligned character of the constituent parts of these transistors, which guarantees the accuracy of their arrangement.
- the self-aligned structure allows to obtain transistors of reduced dimensions perfectly suited to the creation of circuits integrated. We can refer to this subject in the documents (1) and (2) whose references are given at the end of this description.
- a transistor 102 formation region in making thick silicon oxide blocks 104 designated by "LOCOS" (Local Oxidation of Silicon), at the substrate surface.
- LOC Local Oxidation of Silicon
- a first layer of boron doped polycrystalline 106 and a layer insulation 108 of silicon oxide or nitride of silicon are successively formed on the surface of the silicon substrate.
- the reference 110 in FIG. 1 designates an N + layer, doped with arsenic, buried in the substrate 100. This layer constitutes the collector of the transistor which is produced subsequently.
- An engraving mask 112 is formed above the insulation layer 108.
- the mask has a opening that defines the future location of the transmitter of the transistor.
- a next step consists in practicing a window 114 through the layer of polycrystalline silicon 106 and the layer of insulation 108 in order to expose a portion of the 100 silicon substrate.
- the location of the window is determined by the opening of the mask 112 formed on the insulation layer 108.
- the window 114 is produced according to a technique anisotropic reactive ion etching.
- the depth of the engraving is adjusted in particular by selecting the engraving time.
- a next step, illustrated in FIG. 3, essentially comprises the manufacture of the emitter of the transistor in the window 114.
- the emitter comprises a layer of polycrystalline silicon 116 of the N + type doped with arsenic. It is electrically isolated from the sides of the window 114 by a layer of thin thermal oxide 118 and lateral spacers 120 covering the sides. The emitter is also isolated from the first layer 106 of polycrystalline silicon by the insulating layer 108.
- boron ions are implanted in the substrate 100 through window 114. This implantation creates in the substrate a base region designated by intrinsic base. This region is indicated in figure 3 with the reference 122.
- the heat treatment used for the realization of the thermal oxide layer 118 or a other heat treatment implemented after realization of the transmitter cause the diffusion doping impurities from the first layer of polycrystalline silicon 106 and from the layer of polycrystalline silicon 116 forming the emitter, in the silicon substrate.
- the diffusion of impurities, and in particular of boron, the first layer of polycrystalline silicon 106 in the substrate makes it possible to form regions there doped called "extrinsic base" in the following text. These regions are indicated with the reference 124 in Figure 3. Furthermore, the diffusion of arsenic of the polycrystalline silicon layer 116 of the transmitter in the substrate 100 extends the transmitter of an emitter region in contact with the region of intrinsic base 122. The emitter region broadcast in the substrate is shown in Figure 3 with the reference 126.
- Extrinsic base region 124 and the transmitter are heavily doped regions. He is by therefore essential that these regions be sufficiently distant from each other to avoid risk of electrical leakage from the transistor.
- the window overlay 114 (figure 2) is very deep, the diffused area forming the extrinsic base no longer reaches the part of the substrate under the transmitter. There is then a risk of remove the electrical contact between the bases extrinsic and intrinsic. If so, the base intrinsic remains without electrical access. In addition, a significant overprint significantly reduces the distance between the intrinsic base 122 and the layer of collector 110 ( Figure 3) buried. This reduces the voltage withstand between the base and the collector and a breakdown or a base-collector avalanche could occur in the transistor.
- the etching of window 114 and the etching in the silicon of the substrate induces crystallographic defects at the interface emitter-base. These faults generate a current of leakage of the emitter-base junction which degrades the gain current from the transistor.
- the character anisotropic of the engraving of the window 114 gives a rough transmitter-base interface. This roughness at a influence on the result of the chemical treatments that undergoes the substrate during the process of making the transistor. For example, there may be an impact negative on the oxidation rate or on the quality of cleaning between the different stages of manufacturing. The influence of roughness is not controllable.
- the structure shown in Figure 4 is differs from that of FIG. 2, essentially, by a sticker 203 deposited on the substrate 200 in the transistor forming area 202.
- the sticker 203 is a layer of silicon oxide with a thickness of in the range of 20 to 50 nm. It has a layer function burning stop explained below.
- the formation of sticker 203 takes place after that of the insulation pavers thick 204 which delimit the zone of formation of the transistor 202, and before the deposition of the layer of 206 doped polycrystalline silicon and layer insulation 208.
- the surface of the sticker 203 is greater to the dimensions of the opening provided in the mask for engraving the transmitter window. So, this overflow between the opening of the mask and the sticker is compatible with the possibilities photorepeater alignment, which is typically 0.2 ⁇ m.
- a next step, illustrated by FIG. 5, is the etching of a transmitter window 214 through the layer of doped polycrystalline silicon 206 and at through the insulation layer 208.
- This engraving by example a reactive ion etching is stopped by the vignette 203.
- the layer of silicon oxide forming the sticker is produced thick enough to guarantee stopping the engraving and prevent any over-etching of the substrate 200.
- deoxidation After the etching of polycrystalline silicon, deoxidation also removes the part of the sticker exposed at the bottom of the window emitter.
- a heat treatment for example for the formation of the thermal oxide layer 218, makes it possible to make diffuse the doping species of the silicon layer polycrystalline 206 in the substrate 200 to form there the extrinsic base regions 224 such as already described with reference to Figure 3.
- the transistor is inoperative because there is no more electrical access to the base intrinsic.
- Another solution is to form a region of base throughout the transistor manufacturing area 202 (see Figure 4) by implantation of impurities appropriate dopants in the silicon substrate. This implantation is carried out in this case before the production of the sticker and other layers described above.
- Such a process not only avoids an over-etching of the substrate thanks to the sticker but also guarantees electrical contact to the base of the transistor.
- doping impurities implanted in the substrate for form the base continue to diffuse during the stages subsequent and especially during the stages requiring heat treatment.
- the operating frequency of the circuits including such transistors is thereby reduced.
- the object of the present invention is to provide a manufacturing process of a bipolar transistor does not presenting the difficulties set out above.
- One goal is in particular to avoid problems of the over-etching of the substrate during the burning the transmitter window and the problems alignment between the engraving mask and a sticker burning stop.
- a goal is also to avoid a diffusion excessive base regions and speed losses of operation of the resulting transistor.
- Another goal is to guarantee access electric at the base and in particular to a region of intrinsic base in contact with the transmitter.
- the sticker can thus be sized from so that the etching of the insulation layer does not be not critical.
- the first layer of sticker allows avoid over-etching of the substrate and problems generated by such an overprint.
- the first layer of sticker can be a layer of silicon oxide of a thickness between 3 and 10 nm.
- the undoped thermal oxide avoids a direct contact between the doping source, formed by the doped polycrystalline silicon, and the silicon in the intrinsic region of the transistor. So any risk of unintentional boron contamination of this region is discarded.
- thermal oxide guarantees good interface quality silicon / oxide in the active area and in particular there where the emitter-base junction opens.
- thermal oxide unlike a deposited oxide (less dense), degrades less quickly under the action of hot carriers during a polarization in reverse of the emitter-base junction. The duration of operation of the transistor is found as well considerably increased.
- thermal oxide can also be leveraged for the achievement of the MOS transistor gate insulator, in the case of the realization of BiCMOS structures combining bipolar transistors and MOS.
- the silicon polycrystalline subsequently formed can be used also for the realization of the transistor grids MOS.
- heat treatment can take place during step e), during the formation of a layer of thermal oxide covering the sides of the window emitter.
- a single heat treatment allows both to form a layer of thermal oxide which covers the walls of the transmitter window and diffusing doping impurities from the layer of polycrystalline silicon in the substrate to form the extrinsic base and connecting regions.
- the thermal oxide layer is removed from the bottom of the window before the emitter layer is formed.
- step a) of process may further include the formation of a second layer of sticker covering the first sticker layer, the second sticker layer being of doped polysilicon and constituting a reservoir doping impurities for the formation of the region of link base.
- This improvement is particularly advantageous. It allows indeed, by adjusting respectively the doping of the first layer of polycrystalline silicon and the second layer of sticker, independently control the concentration dopants in the intermediate base regions and link base.
- greater doping of the second layer of sticker compensates partial stopping of impurities by the first layer of vignette, and thus obtain basic regions extrinsic and binding with a concentration substantially uniform.
- the first sticker layer may be a layer of silicon oxide (SiO 2 ), and the second sticker layer a layer of polycrystalline silicon doped with boron fluoride (BF 2 ).
- SiO 2 silicon oxide
- BF 2 boron fluoride
- the presence of fluorine in the second layer of vignette facilitates the diffusion of boron through the first layer of sticker.
- the subject of the invention is also a bipolar transistor comprising on the surface of a silicon substrate, a base, called extrinsic, topped by a first layer of silicon polycrystalline doped, a so-called intrinsic base, separate of the extrinsic base and surmounted by a second polycrystalline silicon layer, forming an emitter, and isolated from the first layer of silicon polycrystalline, and a third base, called a link, connecting the extrinsic base to the intrinsic base.
- the link base is for the essentials located under the first layer of silicon polycrystalline doped.
- the connecting base is located under the first layer of doped silicon, the contact between the extrinsic base and the intrinsic base is guaranteed.
- Such a transistor can be obtained with a process as previously indicated.
- the transistor can further include a layer of silicon oxide separating the bonding base from the first layer of polycrystalline silicon.
- the transistor further comprises a layer additional doped polycrystalline silicon, arranged on the silicon oxide layer and separating the base of bonding of the first silicon layer Polycrystalline.
- the manufacture of the transistor begins with the formation of oxide blocks thick 304 which delimit on a silicon substrate 300 a region 302 of transistor formation. This region has dimensions of the order of 1.1 to 1.8 ⁇ m.
- Pavers 304 are formed by local oxidation substrate silicon using a technique known in itself and usually referred to as "LOGOS". Their thickness is of the order of 0.5 to 0.6 ⁇ m.
- thumbnails indicated with references 303a and 303b are formatted according to usual photolithography processes.
- the first layer of sticker is a layer silicon oxide whose thickness is between 3 and 10 nm and preferably equal to 5 nm.
- the thickness layer is adjusted to allow subsequent diffusion of doping impurities through the layer while retaining stop properties of engraving exposed further on.
- the second sticker layer 303b is a layer of polycrystalline silicon with a thickness of the order of 30 nm to 50 nm, for example. It is doped with boron fluoride BF 2 . The concentration of doping impurities is for example from 10 19 to 10 20 cm -3 .
- a first layer of P + doped polycrystalline silicon 306, with boron, is then deposited on the substrate 300 in order to cover the vignettes 303a, 303b, but also the whole of the transistor manufacturing area 302.
- the first layer of polycrystalline silicon 306 has a thickness of the order of 100 to 300 nm and a concentration of boron impurities of the order of 10 19 to 10 20 cm -3 .
- a layer 308 of oxide or nitride of silicon is then deposited on the whole of the first layer of polycrystalline silicon.
- Layer silicon oxide or nitride is a layer electrical insulation. It also presents a thickness of the order of 100 nm to 300 nm.
- an engraving mask 312, made of resin photosensitive is formed above the layer 308 insulation.
- the mask has an opening substantially aligned with the labels 303a, 303b.
- the dimensions of the opening are preferably chosen slightly lower than the thumbnails so alignment is not critical.
- the opening of the mask 312, of same as vignettes 303a, 303b are planned substantially in the center of the 302 zone of formation of the transistor.
- a successive etching of the insulation layers 308 and polycrystalline silicon 306, 303b, through the opening of the mask allows to practice a window 314 known as the transmitter window.
- Etching, for example an anisotropic reactive ion etching is stopped by the first layer of sticker 303a in oxide of silicon. As shown in Figure 8, this layer is exposed at the bottom of window 314.
- the transmitter window has a diameter of in the range of 0.5 to 0.8 ⁇ m. When centered in the manufacturing area of transistor 302, it remains separated from 304 oxide pavers by a distance of about from 0.3 to 0.5 ⁇ m.
- the silicon oxide of the first sticker layer, exposed at the bottom of the window, can be eliminated.
- the engraving mask 312 is also.
- a thin layer of oxide 318 for example thermal oxide is formed in order to line all the walls of the window of transmitter and in particular the lateral sides.
- the concentration of doping impurities in this region is of the order of 10 18 cm -3 .
- the layout is roughly represented by arrows.
- a heat treatment carried out at a temperature of the order of 700 ° C to 950 ° C, advantageously at 850 ° C, for a few minutes can be used for the formation of the thermal oxide layer 318 mentioned above.
- This heat treatment also allows the diffusion of boron from the first layer of polycrystalline silicon 306 into the substrate 300 to form so-called extrinsic base regions 324.
- the concentration of doping impurities in these regions is of the order of 10 20 cm - 3 .
- the heat treatment also allows the diffusion of boron from the second sticker layer 303b, remaining on either side of the window emitter 314, in the substrate 300, through the remaining part of the first layer of sticker 303a. This diffusion, facilitated by the presence of fluorine, allows to form doped regions 323 called "base of bond ".
- the concentration of doping impurities in the binding bases is of the order of 5.10 19 cm -3 to 8.10 19 cm -3 .
- These connecting bases provide electrical continuity between the intrinsic and extrinsic bases.
- a next step, illustrated in Figure 10 includes transmitter training in the window emitter.
- side spacers 320 of silicon nitride are formed on the sides of the transmitter window, on the thermal oxide layer 318.
- the spacers are formed by depositing a layer of silicon nitride followed an anisotropic etching of this layer.
- This layer of polycrystalline silicon 316 is doped with arsenic with a concentration of the order of 10 20 cm -3 . Its thickness is of the order of 200 to 400 nm.
- the emitter layer 316 as well as the layer of the underlying 308 insulation, are then put in form in a new stage of photolithography.
- the outer flanks of the emitter layer 316 can be protected by an insulating flank cover of nitride or silicon oxide. This cover is indicated with the reference 330 in Figure 10.
- a new heat treatment can still to be implemented.
- This heat treatment carried out preferably at a temperature of 950 to 1050 ° C with a duration of the order of 5 to 20 s (for example 1025 ° C for 20 seconds) completes the broadcast of the regions of base 322, 323, 324, already described, and causes a diffusion of an N-doped region 322 which extends the emitter layer in substrate 300. This region is designated by issuer region and bears the reference 326.
- Differences in doping concentration between the first layer of polycrystalline silicon 306 and the polycrystalline silicon layer of the second sticker 303b allow, as mentioned in the first part of the description, to precisely adjust and independently the extrinsic base concentrations and liaison.
- the manufacture of the transistors can by elsewhere to be completed by carrying out contact on the base, emitter and collector and construction of connecting lines electrics between the transistors in order to form integrated circuits.
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
- les figures 1 à 3, déjà décrites, sont des coupes schématiques de la structure d'un transistor bipolaire lors d'étapes successives d'un procédé de fabrication connu,
- les figures 4 à 6, déjà décrites, sont des coupes schématiques de la structure d'un transistor bipolaire lors d'étapes successives d'un autre procédé de fabrication connu,
- les figures 7 à 10 sont des coupes schématiques de la structure d'un transistor bipolaire lors d'étapes successives de fabrication, conformément à une mise en oeuvre particulière du procédé de l'invention. La figure 10 montre également en coupe la structure d'un transistor conforme à l'invention obtenu au terme du procédé.
J.D. hayden, Senior Member, IEEE, J.D. Burnett, J.R. Pfiester, Senior Member, IEE, And M.P. Woo
IEEE transactions on electron devices, vol. 41, n°1 January 1994, pages 63-67.
J.D. Hayden, J.D. Burnett, J.R. Pfiester, and M.P. Woo, Advanced Products Research and Development Laboratory, Motorola Inc.,
IEEE 1992 Bipolar Circuits and Technology Meeting 4.5, pages 96-99.
Claims (8)
- Procédé de fabrication d'un transistor bipolaire sur un substrat de silicium (300) avec une couche de collecteur (310) enterrée, comprenant les étapes successives suivantes :a) réalisation d'une première couche (303a), dite de vignette en oxyde thermique non dopé, recouvrant une partie d'une région (302) de formation de transistor du substrat,b) formation d'une première couche (306) de silicium polycristallin dopé recouvrant la région (302) de formation de transistor et la première couche de vignette, et d'une couche (308) d'isolation électrique recouvrant la couche de silicium polycristallin dopé,c) gravure de la couche d'isolation électrique (308) et de la première couche (306) de silicium polycristallin dopé avec arrêt sur la première couche de vignette (303a) afin d'y pratiquer une fenêtre (314), dite fenêtre d'émetteur, au-dessus d'une partie de la première couche de vignette (303a),d) implantation d'impuretés dopantes pour former une région de base (322), dite intrinsèque, dans le substrat sous la fenêtre d'émetteur (314) et élimination locale de la première couche de vignette (303a) dans la fenêtre d'émetteur,e) isolation latérale des flancs de la fenêtre d'émetteur et formation d'une deuxième couche de silicium polycristallin (316), dite couche d'émetteur,
- Procédé selon la revendication 1, dans lequel la première couche de vignette (303a) est une couche d'oxyde de silicium d'une épaisseur comprise entre 3 et 10 nm.
- Procédé selon la revendication 1, dans lequel le traitement thermique a lieu pendant l'étape e), lors d'une formation d'une couche d'oxyde thermique (318) recouvrant les flancs de la fenêtre d'émetteur (314).
- Procédé selon la revendication 1, dans lequel l'étape a) comporte en outre la formation d'une deuxième couche de vignette (303b) recouvrant la première couche de vignette (303a), la deuxième couche de vignette (303b) étant en polysilicium dopé et constituant un réservoir d'impuretés dopantes pour la formation de la région (323) de base de liaison.
- Procédé selon la revendication 4, dans lequel la première couche de vignette (303a) est une couche d'oxyde de silicium (SiO2) et dans lequel la deuxième couche de vignette (303b), en silicium polycristallin, est dopée au fluorure de bore (BF2).
- Transistor bipolaire comprenant à la surface d'un substrat de silicium (300) une base (324), dite extrinsèque, surmontée par une première couche (306) de silicium polycristallin dopé, une base (322) dite intrinsèque, séparée de la hase extrinsèque (324) et surmontée par une deuxième couche (316) de silicium polycristallin, formant émetteur, et isolée de la première couche (306) de silicium polycristallin, et une troisième base (323), dite de liaison, reliant la base extrinsèque (324) à la base intrinsèque (322), la base de liaison (323) étant pour l'essentiel située sous la première couche (306) de silicium polycristallin dopé, caractérisé en ce que le transistor comprend en outre une couche d'oxyde thermique de silicium, non dopée, (303a) séparant la base de liaison (323) de la première couche de silicium polycristallin (306), la couche d'oxyde présentant une épaisseur suffisamment importante pour constituer une couche d'arrêt de gravure et suffisamment mince pour autoriser une diffusion thermique d'impuretés à travers cette couche.
- Transistor selon la revendication 6, comprenant en outre une couche additionnelle (303b) de silicium polycristallin dopé, disposée sur la couche d'oxyde de silicium (303a) et séparant la base de liaison (323) de la première couche de silicium polycristallin (306).
- Transistor selon la revendication 7, dans lequel la couche additionnelle (303b) de silicium polycristallin et la première couche (306) de silicium polycristallin présentent des concentrations de dopage différentes.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9707237A FR2764733B1 (fr) | 1997-06-11 | 1997-06-11 | Transistor hyperfrequence a structure quasi-autoalignee et son procede de fabrication |
FR9707237 | 1997-06-11 | ||
PCT/FR1998/001183 WO1998057367A1 (fr) | 1997-06-11 | 1998-06-10 | Transistor hyperfrequence a structure quasi-autoalignee et son procede de fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0990266A1 EP0990266A1 (fr) | 2000-04-05 |
EP0990266B1 true EP0990266B1 (fr) | 2002-09-11 |
Family
ID=9507855
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98929532A Expired - Lifetime EP0990266B1 (fr) | 1997-06-11 | 1998-06-10 | Transistor hyperfrequence a structure quasi-autoalignee et son procede de fabrication |
Country Status (5)
Country | Link |
---|---|
US (1) | US6403437B1 (fr) |
EP (1) | EP0990266B1 (fr) |
DE (1) | DE69807877D1 (fr) |
FR (1) | FR2764733B1 (fr) |
WO (1) | WO1998057367A1 (fr) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2799048B1 (fr) * | 1999-09-23 | 2003-02-21 | St Microelectronics Sa | Procede de fabrication d'un transistor bipolaire vertical auto-aligne |
FR2805923B1 (fr) * | 2000-03-06 | 2002-05-24 | St Microelectronics Sa | Procede de fabrication d'un transistor bipolaire double- polysilicium auto-aligne |
US6534372B1 (en) * | 2000-11-22 | 2003-03-18 | Newport Fab, Llc | Method for fabricating a self-aligned emitter in a bipolar transistor |
DE10205712A1 (de) * | 2002-02-12 | 2003-08-28 | Infineon Technologies Ag | Polysilizium-Bipolartransistor und Verfahren zur Herstellung desselben |
US6683366B1 (en) * | 2002-06-04 | 2004-01-27 | Newport Fab, Llc | Bipolar transistor and related structure |
US6759731B2 (en) | 2002-06-05 | 2004-07-06 | United Microelectronics Corp. | Bipolar junction transistor and fabricating method |
US20060160030A1 (en) * | 2003-03-24 | 2006-07-20 | Leibiger Steve M | Single polisilicon emitter bipolar junction transistor processing technique using cumulative photo resist application and patterning |
US7002221B2 (en) * | 2003-08-29 | 2006-02-21 | International Business Machines Corporation | Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same |
US7288829B2 (en) * | 2004-11-10 | 2007-10-30 | International Business Machines Corporation | Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide |
FR2883432B1 (fr) | 2005-03-18 | 2008-02-22 | St Microelectronics Sa | Circuit de filtrage accordable en frequence integrable, comportant un jeu de resonateurs baw |
FR2904492A1 (fr) | 2006-07-28 | 2008-02-01 | St Microelectronics Sa | Circuit de filtrage dote de resonateurs acoustiques |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5352624A (en) * | 1992-01-23 | 1994-10-04 | Sony Corporation | SOI type semiconductor device and manufacturing method therefor |
US5616508A (en) * | 1995-01-09 | 1997-04-01 | Texas Instruments Incorporated | High speed bipolar transistor using a patterned etch stop and diffusion source |
US5593905A (en) * | 1995-02-23 | 1997-01-14 | Texas Instruments Incorporated | Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link |
-
1997
- 1997-06-11 FR FR9707237A patent/FR2764733B1/fr not_active Expired - Fee Related
-
1998
- 1998-06-10 US US09/445,425 patent/US6403437B1/en not_active Expired - Fee Related
- 1998-06-10 DE DE69807877T patent/DE69807877D1/de not_active Expired - Lifetime
- 1998-06-10 EP EP98929532A patent/EP0990266B1/fr not_active Expired - Lifetime
- 1998-06-10 WO PCT/FR1998/001183 patent/WO1998057367A1/fr active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
FR2764733A1 (fr) | 1998-12-18 |
DE69807877D1 (de) | 2002-10-17 |
WO1998057367A1 (fr) | 1998-12-17 |
FR2764733B1 (fr) | 2003-11-14 |
US6403437B1 (en) | 2002-06-11 |
EP0990266A1 (fr) | 2000-04-05 |
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