EP0963601A1 - Procede de production d'un condensateur au silicium - Google Patents

Procede de production d'un condensateur au silicium

Info

Publication number
EP0963601A1
EP0963601A1 EP98905245A EP98905245A EP0963601A1 EP 0963601 A1 EP0963601 A1 EP 0963601A1 EP 98905245 A EP98905245 A EP 98905245A EP 98905245 A EP98905245 A EP 98905245A EP 0963601 A1 EP0963601 A1 EP 0963601A1
Authority
EP
European Patent Office
Prior art keywords
layer
hole structures
conductive
silicon substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98905245A
Other languages
German (de)
English (en)
Inventor
Hermann Wendt
Hans Reisinger
Andreas Spitzer
Reinhard Stengl
Ulrike GRÜNING
Josef Willer
Wolfgang HÖNLEIN
Volker Lehmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Electronics AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0963601A1 publication Critical patent/EP0963601A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor

Definitions

  • the perforated structures 2 begin to grow from unevenness in the main surface 11, which are present with a statistical distribution in each surface.
  • These bumps can be produced using conventional photolithography, for example.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de production d'un condensateur au silicium, consistant à produire, sur un substrat de silicium, des structures à trous (2) à la surface desquelles est créée, par dopage, une zone conductrice (3) dont la surface est pourvue d'une couche diélectrique (4) et d'une couche conductrice (5), sans remplir les structures à trous (2). Afin de compenser les contraintes mécaniques subies par le substrat de silicium (1) et provoquées par le dopage de la zone conductrice (3), une couche auxiliaire conforme, subissant une contrainte mécanique de compression, est formée sur la surface de la couche conductrice (5).
EP98905245A 1997-01-21 1998-01-12 Procede de production d'un condensateur au silicium Withdrawn EP0963601A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19701935A DE19701935C1 (de) 1997-01-21 1997-01-21 Verfahren zur Herstellung eines Siliziumkondensators
DE19701935 1997-01-21
PCT/DE1998/000089 WO1998032166A1 (fr) 1997-01-21 1998-01-12 Procede de production d'un condensateur au silicium

Publications (1)

Publication Number Publication Date
EP0963601A1 true EP0963601A1 (fr) 1999-12-15

Family

ID=7817901

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98905245A Withdrawn EP0963601A1 (fr) 1997-01-21 1998-01-12 Procede de production d'un condensateur au silicium

Country Status (7)

Country Link
US (1) US6165835A (fr)
EP (1) EP0963601A1 (fr)
JP (1) JP2001508948A (fr)
KR (1) KR20000070287A (fr)
DE (1) DE19701935C1 (fr)
TW (1) TW370705B (fr)
WO (1) WO1998032166A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10138759A1 (de) * 2001-08-07 2003-03-06 Bosch Gmbh Robert Verfahren zur Herstellung eines Halbleiterbauelements sowie Halbleiterbauelement, insbesondere Membransensor
DE102004063560B4 (de) * 2004-12-30 2009-01-29 Infineon Technologies Ag Kapazitive Struktur und Verfahren zur Herstellung einer kapazitiven Struktur
US7911802B2 (en) 2007-04-06 2011-03-22 Ibiden Co., Ltd. Interposer, a method for manufacturing the same and an electronic circuit package
US7670931B2 (en) * 2007-05-15 2010-03-02 Novellus Systems, Inc. Methods for fabricating semiconductor structures with backside stress layers
US8487405B2 (en) 2011-02-17 2013-07-16 Maxim Integrated Products, Inc. Deep trench capacitor with conformally-deposited conductive layers having compressive stress
US11075204B2 (en) * 2018-12-14 2021-07-27 Xia Tai Xin Semiconductor (Qing Dao) Ltd. Semiconductor device and method for fabricating the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4125199C2 (de) * 1991-07-30 1994-04-28 Siemens Ag Kompakte Halbleiterspeicheranordnung, Verfahren zu deren Herstellung und Speichermatrix
RU2082258C1 (ru) * 1991-08-14 1997-06-20 Сименс АГ Схемная структура с по меньшей мере одним конденсатором и способ ее изготовления
GB2262186A (en) * 1991-12-04 1993-06-09 Philips Electronic Associated A capacitive structure for a semiconductor device
US5348627A (en) * 1993-05-12 1994-09-20 Georgia Tech Reserach Corporation Process and system for the photoelectrochemical etching of silicon in an anhydrous environment
JPH07130871A (ja) * 1993-06-28 1995-05-19 Toshiba Corp 半導体記憶装置
US5619061A (en) * 1993-07-27 1997-04-08 Texas Instruments Incorporated Micromechanical microwave switching
DE4428195C1 (de) * 1994-08-09 1995-04-20 Siemens Ag Verfahren zur Herstellung eines Siliziumkondensators
US5508542A (en) * 1994-10-28 1996-04-16 International Business Machines Corporation Porous silicon trench and capacitor structures

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9832166A1 *

Also Published As

Publication number Publication date
US6165835A (en) 2000-12-26
JP2001508948A (ja) 2001-07-03
KR20000070287A (ko) 2000-11-25
TW370705B (en) 1999-09-21
DE19701935C1 (de) 1997-12-11
WO1998032166A1 (fr) 1998-07-23

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