GB2262186A - A capacitive structure for a semiconductor device - Google Patents
A capacitive structure for a semiconductor device Download PDFInfo
- Publication number
- GB2262186A GB2262186A GB9125824A GB9125824A GB2262186A GB 2262186 A GB2262186 A GB 2262186A GB 9125824 A GB9125824 A GB 9125824A GB 9125824 A GB9125824 A GB 9125824A GB 2262186 A GB2262186 A GB 2262186A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- dielectric material
- semiconductor device
- electrically conductive
- pores
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 239000011148 porous material Substances 0.000 claims abstract description 58
- 229910021426 porous silicon Inorganic materials 0.000 claims abstract description 47
- 238000000576 coating method Methods 0.000 claims abstract description 41
- 239000003989 dielectric material Substances 0.000 claims abstract description 38
- 239000011248 coating agent Substances 0.000 claims abstract description 35
- 239000012799 electrically-conductive coating Substances 0.000 claims abstract description 20
- 230000005669 field effect Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 238000007743 anodising Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000002800 charge carrier Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 239000012535 impurity Substances 0.000 description 10
- 238000001465 metallisation Methods 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 238000002048 anodisation reaction Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000003792 electrolyte Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- WCUXLLCKKVVCTQ-UHFFFAOYSA-M Potassium chloride Chemical compound [Cl-].[K+] WCUXLLCKKVVCTQ-UHFFFAOYSA-M 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 101000836826 Homo sapiens Protein shortage in chiasmata 1 ortholog Proteins 0.000 description 1
- 101000693444 Homo sapiens Zinc transporter ZIP2 Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 102100025451 Zinc transporter ZIP2 Human genes 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002808 molecular sieve Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 235000011164 potassium chloride Nutrition 0.000 description 1
- 239000001103 potassium chloride Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- URGAHOPLAPQHLN-UHFFFAOYSA-N sodium aluminosilicate Chemical compound [Na+].[Al+3].[O-][Si]([O-])=O.[O-][Si]([O-])=O URGAHOPLAPQHLN-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
- H01L29/742—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a field effect transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
Abstract
A semiconductor body has adjacent one major surface (3) a porous silicon portion in which the walls (11a) of the pores are provided with a dielectric material coating (12). An electrically conductive coating (13) is provided in the pores over the dielectric material coating (12) to provide an electrode which is capacitively coupled to the semiconductor body via the dielectric material coating (12). A semiconductor device can thus be produced which may provide a high density capacitive structure which, for the capacitance achieved, occupies relatively little of the surface area of the semiconductor body. The capacitive structure may form the insulated gate structure of an insulated gate field effect device. <IMAGE>
Description
DESCRIPTION
A SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURINC A
SEMICONDUCTOR DEVICE
This invention relates to a semiconductor device and a method of manufacturing a semiconductor device, which semiconductor device comprises a semiconductor body having adjacent one major surface a porous silicon portion in which the pores are provided with a dielectric material coating.
As discussed in a paper entitled "Novel Applications of porous silicon" by J.M. Keen presented at ESSDERC 90 Nottingham, September 1990, Session ZIP2, porous silicon was originally discovered as a result of investigations into electropolishing of silicon with hydrofluoric acid electrolytes and was found to occur as a result of anodisation at anodic voltages lower than those required for true electropolishing. Porous silicon is now recognised to be formed by the original silicon strained and riddled with holes formed by localised electrochemical attack. Many applications have been proposed for such porous silicon. Thus, for example, as discussed in the aforementioned paper, porous silicon may be completely oxidised to provide dielectric isolation for semiconductor devices or may be metallised, for example using tungsten, by a silicidation process.
US-A-4801380 discusses a further use of porous silicon. In this example, the anodisation is controlled to provide micropores with a diameter of less than 20 nanometres (nm) to provide a porous layer which may then be attached to a substrate and used as a filter in molecular separation processes, that is the layer may be used as a so-called molecular sieve. The pore walls may be plated with a metal such as copper or silver after anodisation by transferring the anodised porous silicon film to a plating cell.
The porous silicon film may be stabilised against oxidation of the pore walls in other ways and a controlled oxidation of the pore walls may be used to reduce the pore size.
It is an aim of the present invention to provide a method of manufacturing a semiconductor device in which the properties of porous silicon can be used to form a capacitive structure.
According to one aspect of the present invention, there is provided a semiconductor device comprising a semiconductor body having adjacent one major surface a porous silicon portion in which the pores are provided with a dielectric material coating, characterised in that an electrically conductive coating is provided in the pores over the dielectric material coating to provide an electrode which is capacitively coupled to the semiconductor body via the dielectric material coating.
In another aspect, the present invention provides a method of manufacturing a semiconductor device, which method comprises providing a semiconductor body having a crystalline silicon portion adjacent one major surface, anodising the crystalline silicon portion to form a porous silicon portion and providing a dielectric material coating on the walls of the pores, characterised by depositing electrically conductive material into the pores to form on the dielectric material coating an electrically conductive coating which provides an electrode capacitively coupled to the semiconductor body via the dielectric material coating.
Thus, using the present invention, a semiconductor device can be produced which may provide a high density capacitive structure which, for the capacitance achieved, occupies relatively little of the surface area of the semiconductor body. Such a high density capacitive structure may be used for forming capacitors within integrated semiconductor device circuits, for example within so-called smart power circuits where one or more power semiconductor devices are integrated with logic device for controlling operation of the power semiconductor devices.
The capacitive structure formed by the dielectric material and electrically conductive coatings may form the insulated gate structure of an insulated gate field effect device such as, for example, a power MOSFET, an IGBT (Insulated Gate Bipolar
Transistor) or a MOS-controlled thyristor. In one example of such an insulated gate field effect device, the semiconductor body has a first region of one conductivity type adjacent the porous silicon portion, the porous silicon portion comprises a second region of the opposite conductivity type forming a first pn junction with the first region, a third region of the one conductivity type spaced from the first region by the second region forms a second pn junction with the second region, and the dielectric material and electrically conductive coatings define an insulated gate structure overlying a conduction channel area of the second region for providing a gateable connection between the third and first regions.
Where the semiconductor device is an IGBT or MOS-controlled thyristor, the semiconductor body may have one or more fourth regions of the opposite conductivity type spaced from the second region by the first region and forming a pn junction with the first region for injecting minority charge carriers into the first region.
Using a method in accordance with the invention enables an insulated gate structure to be provided which has an effective channel width which is an order of magnitude greater than can be achieved with known so-called Trenchfet technology described in, for example, a paper entitled 'self-aligned DMOSFET's with a specific on-resistance of 1cm2' by H.R. Chang et al published in IEEE Transactions on Electron Devices, Vol. ED 34, No. 11,
November 1987 at pages 2329 to 2334 and in, for example,
EP-A-238749.
The dielectric coating may be provided by thermal oxidation of the pore walls. The electrically conductive coating may be formed of doped polycrystalline silicon deposited into the pores. The polycrystalline silicon may be doped before or during deposition.
Other electrically conductive coatings may be used. Thus, for example, nickel or copper could be deposited into the pores using an electroless deposition technique.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:
Figure 1 is a cross-sectional view of part of a first embodiment of a semiconductor device in accordance with the invention;
Figure 2 is a cross-sectional view of part of a second embodiment of a semiconductor device in accordance with the invention;
Figures 3 and 4 are cross-sectional views of a portion of the part shown in Figures 1 and 2 for illustrating steps in a first embodiment of a method in accordance with the invention;
Figures 5 is a cross-sectional view of a portion of the part shown in Figures 1 and 2 for illustrating steps in a second embodiment of a method in accordance with the invention; and
Figures 6 and 7 are enlarged views of part of the porous silicon portion of a semiconductor device in accordance with the invention for illustrating steps in a method in accordance with the invention.
It should be understood that the Figures are merely schematic and are not drawn to scale. In particular certain dimensions such as the thickness of layers or regions may have been exaggerated whilst other dimensions may have been reduced. It should also be understood that the same reference numerals are used throughout the
Figures to indicate the same or similar parts.
Referring now to the drawings, there is illustrated in, for example, Figure 1 or Figure 2 a semiconductor device 1, 1' comprising a semiconductor body 2 having adjacent one major surface 3 a porous silicon portion 10 in which the walls lla of the pores 11 (indicated merely by dashed lines in Figures 1 to 6 but shown in
Figures 6 and 7) are provided with a dielectric material coating 12. In accordance with the invention, an electrically conductive coating 13 (Figure 7) is provided in the pores 11 over the dielectric material coating 12 to provide an electrode G which is capacitively coupled to the semiconductor body 2 via the dielectric material coating 12.
Figures 1 to 7 illustrate a method of manufacturing a semiconductor device 1 which method comprises providing a semiconductor body 2 having a crystalline silicon portion adjacent one major surface 3, anodising the crystalline silicon portion to form a porous silicon portion 10 (Figure 6) and providing a dielectric material coating 12 on the walls Ila of the pores 11.
In accordance with the invention, the method further comprises depositing electrically conductive material into the pores 11 to form on the dielectric material coating 12 an electrically conductive coating 13 (Figure 7) which provides an electrode G capacitively coupled to the semiconductor body 2 via the dielectric material coating 12.
A semiconductor device 1 may thus be produced which can provide a high density capacitive structure which, for the capacitance achieved, occupies relatively little of the surface area of the semiconductor body. Such a high density capacitive structure may be used for forming capacitors within integrated semiconductor device circuits, for example within so-called smart power circuits where one or more power semiconductor devices are integrated with logic devices for controlling operation of the power semiconductor devices.
As will be described below with reference to the drawings the capacitive structure formed by the dielectric material and electrically conductive coatings 12 and 13 may form the insulated gate structure 31 of an insulated gate field effect device such as, for example, a power MOSFET, IGBT (insulated gate bipolar transistor) or MOS-controlled thyristor.
Referring now specifically to Figure 1, there is illustrated part of a semiconductor device 1 embodying the invention. In this example, the semiconductor device 1 is a vertical insulated gate field effect transistor or MOSFET. It should be understood that the term 'vertical' is used herein to define a device in which the main current path is between the two major surfaces 3 and 4 of the semiconductor body 1.
In this example, the semiconductor body 1 comprises a first region 2 in the form of a relatively highly doped monocrystalline silicon substrate 2a, in this case an n-conductivity type substrate, and a relatively lowly doped n conductivity type silicon epitaxial layer 2b provided on the substrate 2a and having a resistivity of, typically, 1 to 5 Ohm-cm, although the resistivity will depend very much on the desired breakdown voltage of the device and could be, for example, as high as 100 Ohm-cm. The relatively highly doped substrate 2a forms a drain contact region and is contacted by drain electrode D metallisation 20 whilst the relatively lowly doped epitaxial layer 2b forms a drain drift region of the MOSFET 1.
A second region 5 of the opposite conductivity type, p conductivity type in this example, forms a first pn junction 5a with the drain drift region 2b. The second region 5 may be formed by epitaxial deposition of p conductivity type silicon or may be formed by introducing, generally implanting and diffusing, p conductivity type impurities, usually boron ions, into the epitaxial layer 2b. Typically, the second region 5 may have a thickness of lym (micrometre) and a surface dopant concentration of 1O18cm#3 A third region 6 of the one conductivity type, in this example n conductivity type, forms a second pn junction 6a with the second region 5. The third region 6 forms the source region of the
MOSFET.The third region 6 is in this example formed by introducing, generally implanting and diffusing, dopant impurities, for example phosphorous ions, into the one major surface 3 of the semiconductor body 2 via an appropriate conventional mask so that, as illustrated in Figures 3 and 4, the source region 6 has an island-like shape.
The source region 6 may have any desired geometry when viewed in plan, that is when looking down on the one major surface 3, and may be, for example, circular, rectangular (with rounded corners) or hexagonal. It will be appreciated that, although only one source region 6 is shown in Figure 1, where the device is a power
MOSFET then the device may have an array of source regions 6, typically of the order of, for example, 100,000 to 250,000 source regions 6 each providing, as will be described below, a respective one of parallel conductive paths to the common drain drift region 2b via a conduction channel area 30 (shown by dashed lines in
Figure 7) defined in the second region 6 by a respective insulated gate structure 31 (Figure 2) formed in an associated porous silicon region 10.
As indicated above, the insulated gate structure 31 is formed in the porous silicon region 10 by the dielectric coating 12 and the electrically conductive coating 13 (Figures 6 and 7) on the walls 11a of the pores 11. The insulated gate structure 31 overlies and defines the conduction channel area 30 of the MOSFET 1.
The electrically conductive coating 13, which may be formed of doped polycrystalline silicon, extends to form an electrically conductive plug 13a on the one major surface 3 and is, as shown in
Figures 1 and 2, bounded by an insulating layer 19. Metallisation deposited onto the one major surface 3 and patterned using conventional photolithographic and etching techniques defines gate electrode G metallisation 21 over the electrically conductive plug 13a and source electrode S metallisation 22 in a window 19b in the insulating layer 19. As shown, the source electrode S shorts the third and second regions 6 and 5 to inhibit parasitic bipolar action.
Figure 2 illustrates, by way of a cross-sectional view similar to Figure 1, part of a second embodiment of a semiconductor device in accordance with the invention.
The device 1' shown in Figure 2 differs from that shown in
Figure 1 by the fact that a number (only two are shown) of fourth regions 7 of the opposite conductivity type, p conductivity type in this example, are provided, by introduction of impurities using an appropriate mask, adjacent the other major surface 4 of the semiconductor body 2 so as to extend through the drain contact region 2a. The fourth regions 7 are shorted to the drain contact region 2a by the metallisation 20 and are designed to inject minority carriers into the drain drift region 2b of the device during operation so as, in particular, to reduce the on-resistance of the device 1'. The device 1' shown in Figure 2 thus constitutes an insulated gate bipolar transistor (IGBT).As an alternative to the structure shown in Figure 2, the entire substrate 2a may be replaced by a p conductivity type substrate, possibly separated from the drain drift region 2b by a relatively highly doped n conductivity type buffer layer to moderate the minority carrier injection and so inhibit thyristor action. In this example, the metallisations 20, 21 and 22 form the anode, gate and cathode electrodes A,G and C, respectively, of the IGBT.
The formationvof the insulated gate structure 31 by anodisation to form a porous silicon portion 10 and then the provision of first a dielectric coating 12 and then an electrically conductive coating 13 on the walls 11a of the pores provides a conduction channel area 30 (Figure 7) which has a width far greater than could be achieved, with the same semiconductor area, using conventional VMOS or Trenchfet technology.
To give an estimate, where the porous silicon portion 10 is 50% pores (50% porosity), the effective channel width will be
2#r (4razz per cm2 where r is the radius of a pore 11, leading to an effect channel width of about 4x104 cm per square centimetre for a hole radius of 0.1#itn (micrometre).
The provision of a channel width which is an order of magnitude greater than can be achieved using conventional VMOS or
Trenchfet technology should have the advantages of improving the current-handling capability, reduced channel resistance because of the increase in channel width and reduced chip area for a device comparable to a conventional VMOS or Trenchfet device. The precise dimensions of the conduction channel area 30 will depend upon the size of the pores, the width of the porous silicon portion 10 in the second region 5 and the depth of the second region 5.
Where the pores 11 extend through the second region 5 to a depth of about ljim and half the volume of the porous silicon region 10 is made up of pores 11 (50% porosity), then, if L is the total length of the pores 11, in one square cm of the porous silicon portion 10 the volume of voids (pores 11) in one cm2 will be 1x10-4 = Lxr2, the total surface area of the pores 11 will be
2
O.5x1O#4 10-#
L2Xr = mm- .2#r = 10 cm2. Where r is O.2#m then the total
r surface area of the pores 11 = 5cm2 per square centimetre of surface giving a capacitance of about 0.3/1F (microfarads) cm#2 for a 50nm thick silicon oxide dielectric material coating 12.
The porous silicon portion 10 and the insulated gate structure 31 may be formed in the following manner.
As illustrated in Figure 3, the second region 5 is provided by either epitaxial deposition of p conductivity type silicon on or by introduction of p conductivity type impurities into the semiconductor body 2. A mask 40 which is resistant to attack by the anodising solution or etchant (generally an aqueous hydrofluoric acid) to be used to form the porous silicon region is provided on the one major surface 3 so as to expose a surface area 50 of the second region 5 at which the porous silicon region 10 is to be formed. The mask 40 may be formed of, for example, a photosensitive resist or silicon nitride.
The semiconductor body 2 is then placed in an anodising bath containing the anodising solution, which is in this case aqueous hydrofluoric acid, so that the semiconductor body 2 is at the anode of the electrochemical cell.
As discussed in the paper by Herino et al entitled 'Porosity and Pore Size distributions of porous silicon layers' published in
J. Electrochem Soc. Solid State Science and Technology, August 1987 at pages 1994 to 2000 and referred to in the above-mentioned review paper by J.M. Keen, the properties and pore structures of porous silicon are controlled by the type and resistivity of the silicon starting material, the composition of the electrolyte used for the anodising process and the precise anodising conditions, particularly the anodising current density. As discussed in, for example, US-A-4 592 824, EP-A-299 779 and the Keen review paper, pores can be produced with diameters ranging from a few nanometres to a few micrometres.
The smaller the radius of the pores 11, the greater the channel width and capacitance which can theoretically be achieved.
However, the need to be able reproduceably to oxidise the pore walls 11a to provide the dielectric material coating 12 and to introduce the electrically conductive material for forming the electrically conductive coating will in practice place a lower limit on the radius of the pores 11. In this example, the anodising conditions are chosen so as to produce pores 11 with a desired pore radius r in the second region 5 of, for example, 0.5#im and to provide a total volume of pores of about 50% (50% porosity).
As described in a paper by R.P. Holmstrom and J.Y. Chi published in Applied Physics Letters 42(4) 15 February, 1983 at pages 386 to 388, anodic etching of n conductivity type silicon in a hydrofluoric acid electrolyte exhibits a concentration dependent voltage threshold which allows the anodic etching process to be selective for heavily doped silicon and to stop at a lightly doped region. Anodic etching of lowly doped silicon such as the drain drift region 5 occurs only with difficulty and the anodic etching will effectively stop adjacent the pn junction 5a.
After removal of the mask 40 the one major surface 3 may be masked during the introduction of the impurities, generally phosphous ions, so as to produce one or more island-like third regions 6 (one of which is shown in Figure 3) each aligned with a respective porous silicon region 10 (only one of which is shown) as discussed above. Alternatively, as shown in Figure 5, the third region 6' may be formed as a layer extending all the way across the second region 5 by a blanket introduction of n conductivity type impurities.
It may be possible to carry out the anodic etching process before introducing the impurities for forming the second region 5.
This should result, as described in the above-mentioned paper by
Herino, in larger diameter pores 11 for a given set of anodising conditions. The second region 5 may then be formed in a manner similar to that described above for the third region 6 by a blanket (that is without a mask) introduction of p conductivity type impurities. Of course, the introduction of the p conductivity type impurities should be controlled so that the second region 5 does not extend beyond the ends of the pores 11.
As a further possibility it might be possible to form the pores 11 after introduction of the impurities to form the third region 6. However, as in this case the semiconductor body will then contain two pn junctions in series, it may be necessary to facilitate the anodic etching across the pn junction between the second and third regions by, for example, illuminating the area being etched with infra-red radiation.
After the pores 11 and the second and third regions 5 and 6 have been provided, the dielectric material coating 12 is provided on the walls 11a of the pores 11 as illustrated in Figure 6. The dielectric material coating 12 may be provided by thermal oxidation of the silicon of the pore walls lla. The thermal oxidation may be assisted by subjecting the porous silicon region 10 to an aqueous potassium chloride etch as described in a paper entitled 'Porous silicon oxide layer formation by the electrochemical treatment of a porous silicon layer' by Yamana et al published in the Journal of the Electrochemical Society, Volume 137 No. 9 September 1990 at pages 2925 to 2927.Where the pores have a radius of from about O.1#im to about O.5Sm, then the time and temperature of the thermal oxidation in, for example, wet oxygen may be controlled to produce a dielectric material layer having a thickness of about 5Onm.
After formation of the dielectric material coating 12, a dielectric material, e.g. silicon oxide, layer 19 is provided using conventional chemical vapour deposition techniques. As shown in
Figures 1 and 2, a window 19a is opened in the dielectric material layer 19 over the porous silicon portion 10 and then doped polycrystalline silicon is deposited, with any other exposed silicon surface areas (not shown) masked, using a chemical vapour deposition technique so as to fill the pores 11 and provide the electrically conductive coating 13 on the dielectric layer 12. It is not be necessary for the electrically conductive material to fill the pores 11 completely.Also, although it is preferred that the electrically conductive coating 13 be formed so as to have no discontinuities and so as to cover the pore walls 11a to complete the insulated gate structure 31, a small number of discontinuities in the electrically conductive coating 13 should not constitute a problem provided that there is still a sufficient conductive path along the surface 11a of the pores 11 to enable control of the conduction channel area 31 to provide a conductive path between the third region 6 and the first region 2 which is capable of providing the device with the desired current handling capabilities.
Electrically conductive materials other than doped polycrystalline silicon may be used to form the electrically conductive coating 13. Thus, for example, a metal such as nickel, cobalt or copper may be deposited using an electroless deposition technique to form the electrically conductive coating 13. The use of doped polycrystalline silicon has however the advantage that the doped polycrystalline silicon forms a pn junction with the silicon of the second region 5 so that if pinholes arise in the thermal oxide, the conductive coating will not be electrically shorted to the second region 5.
The deposition of the doped polycrystalline silicon is continued until the one major surface 3 is covered by the doped polycrystalline silicon. The surface area of the doped polycrystalline silicon may then be patterned using conventional photolithographic and etching techniques to leave the electrically conductive plug 13a over the porous silicon portion 10 in electrical contact with the remainder of the doped polycrystalline silicon coating 13.
A window l9b is then opened in the dielectric layer 19 where the metallisation 22 is desired and metal then deposited and patterned to provide the gate electrode G metallisation 21 and the source or cathode electrode S or C metallisation 22 which shorts the second and third regions 5 and 6 so as to avoid undesired parasitic bipolar effects. Metallisation 20 is also provided on the other major surface 4 to provide the drain or anode electrode D or A.
Although in the examples described above, the pores 11 extend through the third region 6, it may be possible to provide the third region 6 by epitaxial deposition of doped semiconductor material, usually monocrystalline silicon although polycrystalline silicon could be used, after formation of insulated gate structure 31 in the porous silicon portion 10 so that the third region is not part of the porous silicon portion 10. This would necessitate the later formation of a mesa structure or a groove through the third region 6 to enable electrical contact to the insulated gate structure 31.
In the examples described above, the insulated gate field effect device is a normally off or enhancement mode device, that is there is no conduction channel between the first and third regions 2 and 6 until a gate voltage is applied to the insulated gate structure 31 to form an inversion conduction channel at the conduction channel area 30. However, the present invention may also be applied to insulated gate field effect devices of the normally-on or depletion mode type, that is devices where there is a conductive conduction channel between the first and third regions 2 and 6 until a gate voltage is applied. Where the insulated gate field effect device is a depletion mode device at least the conduction channel area 30 (Figure 8) and generally the entirety of the second region 5 will be of the same conductivity type as the first and third regions 2 and 6. In this case the pores 11 may be formed after provision of the third region 6.
As described above, the present invention may also be used to form high density capacitors which, as will be appreciated from the sample calculations given above, will occupy relative little surface area, in comparison to conventional semiconductor capacitors, for the achieved capacitance values. In such cases, the third region 6 may of course be omitted. The capacitance of such a high density capacitor will, as indicated in the calculations given above, depend upon the thickness of the second region 5 through which the pores 11 extend, the radius of the pores 11, the dielectric constant and thickness of the dielectric coating 12 and the extent of the capacitive structure.Where the capacitor is a discrete component and the second region has a thickness of 10ym or more, then capacitances of 3p F cm~2 or more may be achieved. Such a high density capacitor may be integrated with other components for example with a power semiconductor device to form a snubber capacitor or with a diode of a switched mode power supply circuit to form a filter capacitor.
In the examples given above, the silicon of the second region 5 is monocrystalline before anodisation, however the present invention could also be applied where the silicon is polycrystalline.
Although in the examples given above, the entire semiconductor body 2 is formed of silicon (Si) this need not necessarily be the case and thus, for example, only the porous silicon region need be formed of silicon. The other semiconductor regions of the semiconductor body could be formed of other materials such as germanium (Ge), an Si-Ge alloy, or a III-V compound semiconductor such as gallium arsenide.
The conductivity types given above could of course be reversed.
From reading the present disclosure, other modifications and variations will be apparent to persons skilled in the art. Such modifications and variations may involve other features which are already known in the semiconductor art and which may be used instead of or in addition to features already described herein.
Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
Claims (13)
1. A semiconductor device comprising a semiconductor body having adjacent one major surface a porous silicon portion in which the pores are provided with a dielectric material coating characterised in that an electrically conductive coating is provided in the pores over the dielectric material coating to provide an electrode which is capacitively coupled to the semiconductor body via the dielectric material coating.
2. A semiconductor device according to Claim 1, further characterised in that the dielectric material coating comprises a thermal silicon oxide layer.
3. A semiconductor device according to Claim 1 or 2, further characterised in that the electrically conductive coating comprises doped polycrystalline silicon.
4. A semiconductor device according to Claim 1,2 or 3, characterised in that the dielectric material and electrically conductive coating form the insulated gate structure of an insulated gate field effect device.
5. A semiconductor device according to Claim 4, further characterised in that the semiconductor body has a first region of one conductivity type adjacent the porous silicon portion, the porous silicon portion comprises a second region of the opposite conductivity type forming a first pn junction with the first region, a third region of the one conductivity type spaced from the first region by the second region forms a second pn junction with the second region and the dielectric material and electrically conductive coatings define an insulated gate structure overlying a conduction channel area of the second region for providing a gateable connection between the third and first regions.
6. A semiconductor device according to Claim 5, further characterised in that the semiconductor body has one or more fourth regions of the opposite conductivity type spaced from the second region by the first region and forming a pn junction with the first region for injecting minority charge carriers into the first region.
7. A method of manufacturing a semiconductor device, which method comprises providing a semiconductor body having a crystalline silicon portion adjacent one major surface, anodising the crystalline silicon portion to form a porous silicon portion and providing a dielectric material coating on the walls of the pores, characterised by depositing electrically conductive material into the pores to form on the dielectric material coating an electrically conductive coating which provides an electrode capacitively coupled to the semiconductor body via the dielectric material coating.
8. A method according to Claim 7, further characterised by providing the dielectric material coating by oxidation of the porous silicon.
9. A method according to Claim 7 or 8, further characterised by forming the electrically conductive coating of doped polycrystalline silicon.
10. A method according to Claim 7,8 or 9, further characterised by providing the semiconductor body with a first region of one conductivity type adjacent the porous silicon portion, forming the porous silicon portion as a second region of the opposite conductivity type forming a first pn junction with the first region and providing a third region of the one conductivity type spaced from the first region by the second region to form a second pn junction with the second region so that the dielectric material and electrically conductive coatings within the pores of the porous silicon portion define an insulated gate structure overlying a conduction channel area of the second region for providing a gateable conductive path between the third and first regions.
11. A method according to Claim 10, further characterised by providing the semiconductor body with one or more fourth regions of the opposite conductivity type spaced from the second region by the first region and forming a pn junction with the first region for injecting minority charge carriers into the first region.
12. A method of manufacturing a semiconductor device substantially as hereinbefore described with reference to the accompanying drawings.
13. A semiconductor device substantially as hereinbefore described with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9125824A GB2262186A (en) | 1991-12-04 | 1991-12-04 | A capacitive structure for a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9125824A GB2262186A (en) | 1991-12-04 | 1991-12-04 | A capacitive structure for a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9125824D0 GB9125824D0 (en) | 1992-02-05 |
| GB2262186A true GB2262186A (en) | 1993-06-09 |
Family
ID=10705719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9125824A Withdrawn GB2262186A (en) | 1991-12-04 | 1991-12-04 | A capacitive structure for a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2262186A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998032166A1 (en) * | 1997-01-21 | 1998-07-23 | Siemens Aktiengesellschaft | Method for producing a silicium capacitor |
| FR2897467A1 (en) * | 2006-02-15 | 2007-08-17 | St Microelectronics Crolles 2 | Capacitor, e.g. for metal-insulator-metal capacitor used as decoupling capacitor and filter for voltage-controlled oscillator and memory element, comprises insulating porous material |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1535902A (en) * | 1976-07-02 | 1978-12-13 | Ibm | Moisture sensing devices and their manufacture |
| JPS5413268A (en) * | 1977-07-01 | 1979-01-31 | Oki Electric Ind Co Ltd | Manufacture for semiconductor device |
| JPS5449076A (en) * | 1977-09-26 | 1979-04-18 | Nec Corp | Manufacture of schottky barrier diode |
-
1991
- 1991-12-04 GB GB9125824A patent/GB2262186A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1535902A (en) * | 1976-07-02 | 1978-12-13 | Ibm | Moisture sensing devices and their manufacture |
| JPS5413268A (en) * | 1977-07-01 | 1979-01-31 | Oki Electric Ind Co Ltd | Manufacture for semiconductor device |
| JPS5449076A (en) * | 1977-09-26 | 1979-04-18 | Nec Corp | Manufacture of schottky barrier diode |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998032166A1 (en) * | 1997-01-21 | 1998-07-23 | Siemens Aktiengesellschaft | Method for producing a silicium capacitor |
| US6165835A (en) * | 1997-01-21 | 2000-12-26 | Siemens Aktiengesellschaft | Method for producing a silicon capacitor |
| FR2897467A1 (en) * | 2006-02-15 | 2007-08-17 | St Microelectronics Crolles 2 | Capacitor, e.g. for metal-insulator-metal capacitor used as decoupling capacitor and filter for voltage-controlled oscillator and memory element, comprises insulating porous material |
| US7630191B2 (en) | 2006-02-15 | 2009-12-08 | Stmicroelectronics Crolles 2 Sas | MIM capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9125824D0 (en) | 1992-02-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5323040A (en) | Silicon carbide field effect device | |
| US4546367A (en) | Lateral bidirectional notch FET with extended gate insulator | |
| US20200273981A1 (en) | Power device having super junction and schottky diode | |
| CN110473916B (en) | Preparation method of silicon carbide MOSFET device with p+ region self-alignment process | |
| EP0633611A1 (en) | Insulated gate bipolar transistor | |
| EP0345380A2 (en) | Manufacture of a semiconductor device | |
| US4912541A (en) | Monolithically integrated bidirectional lateral semiconductor device with insulated gate control in both directions and method of fabrication | |
| US20080246055A1 (en) | Semiconductor component including a monocrystalline semiconductor body and method | |
| JPH1093087A (en) | Transverse gate longitudinal drift region transistor | |
| JPH09508492A (en) | Three-terminal gate-controlled semiconductor switching device with rectifying gate | |
| KR100514398B1 (en) | Silicon carbide field controlled bipolar switch | |
| EP0425037A2 (en) | A method of manufacturing a semiconductor device | |
| KR20230059176A (en) | Trench Semiconductor Devices Having Trench Bottom Shield Structures | |
| CN117080269A (en) | Silicon carbide MOSFET device and preparation method thereof | |
| US4571513A (en) | Lateral bidirectional dual notch shielded FET | |
| EP0408129A2 (en) | A thin film field effect transistor | |
| EP0273047B1 (en) | Bidirectional vertical power mos device and fabrication method | |
| WO2001091189A1 (en) | Field effect device | |
| JP2001267589A (en) | SiC SEMICONDUCTOR ELEMENT | |
| US5079179A (en) | Process of making GaAs electrical circuit devices with Langmuir-Blodgett insulator layer | |
| GB2262186A (en) | A capacitive structure for a semiconductor device | |
| CN116230770A (en) | Silicon carbide MOSFET device of Schottky junction assisted depletion ballast resistor and preparation method | |
| Cheng et al. | Fast reverse recovery body diode in high-voltage VDMOSFET using cell-distributed Schottky contacts | |
| KR100518506B1 (en) | Trench gate power mos device and fabricating method therefor | |
| CN112635315B (en) | Preparation method of trench oxide layer and trench gate and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |