EP0963601A1

EP0963601A1 - Method for producing a silicium capacitor

Info

Publication number: EP0963601A1
Application number: EP98905245A
Authority: EP
Inventors: Hermann Wendt; Hans Reisinger; Andreas Spitzer; Reinhard Stengl; Ulrike GRÜNING; Josef Willer; Wolfgang HÖNLEIN; Volker Lehmann
Original assignee: Siemens AG
Current assignee: TDK Electronics AG
Priority date: 1997-01-21
Filing date: 1998-01-12
Publication date: 1999-12-15
Also published as: JP2001508948A; US6165835A; KR20000070287A; WO1998032166A1; TW370705B; DE19701935C1

Abstract

The invention relates to method for producing a silicium capacitor by producing hole structures (2) on a silicium substrate (1). A conductive area (3) is produced in the surface of said structures by doping, to which a dielectric layer (4) and a conducting layer (5) is applied without filling the hole structures (2). In order to compensate the mechanical stress of the silicium substrate (1) caused by the doping of the conductive area (3), a conformal auxiliary layer (6) is formed on the surface of the conducting layer (5), which is subjected to compressive mechanical tension

Description

description

Method of manufacturing a silicon capacitor

A silicon capacitor is known from EP 05 28 281 A2. This comprises an n-doped silicon substrate, the surface of which is structured in a characteristic manner by electrochemical etching in a fluoride-containing, acidic electrolyte in which the substrate is connected as an anode. In electrochemical etching, more or less regularly arranged hole structures are formed on the surface of the substrate. The hole structures have an aspect ratio in the range of 1: 1000. The surface of the hole structures is provided with a dielectric layer and a conductive layer. Conductive layer, dielectric layer and silicon substrate form a capacitor in which specific capacities of up to 100 μV / mrn ^ are achieved due to the surface enlargement caused by the hole structures. In order to increase the conductivity of the substrate, it is proposed to provide an n ⁺ -doped region on the surface of the hole structures.

Silicon capacitors are usually manufactured in silicon wafers. Bending of the silicon wafers is ascertained, which is associated with mechanical stresses by the n ⁺ -doped region on the surface of the hole structures, which are up to 300 μm thick. This bending of the silicon wafer leads to problems in further process steps, such as lithography, wafer thinning and separation, which are necessary for installing the silicon capacitor in a housing.

DE 44 28 195 Cl has proposed a method for producing such a silicon capacitor. To mechanical caused by the doping of the doped area

To compensate for tension in the silicon substrate, the doped area is additionally doped with germanium. The additional doping with germanium leads to an increase in process complexity.

The invention is based on the problem of specifying a method for producing a silicon capacitor which is simpler than the known one.

This problem is solved according to the invention by a method according to claim 1. Further developments of the invention emerge from the remaining claims.

A large number of hole structures are produced in a main surface of a silicon substrate. The perforated structures have a round or polygonal cross-section and side walls essentially perpendicular to the main surface.

A conductive region provided with an electrically active dopant is produced along the surface of the hole structures. The conductive area forms a capacitor electrode in the finished silicon capacitor. It is preferably doped with phosphorus or boron.

A dielectric layer and a conductive layer which do not fill up the hole structures are applied to the surface of the conductive region. An auxiliary layer with an essentially conformal edge covering is formed on the surface of the conductive layer, which is under compressive mechanical stress. Finally the hole structures are filled up.

The conductive region provided with dopant, which is formed along the surface of the hole structures, leads to a concave bending of the silicon substrate if the dopant has a smaller covalent bond radius than silicon. This is the case for phosphorus and boron. The use of the auxiliary layer, which is under a compressive mechanical stress and which is compliant Edge covering is used in the hole structures, causes the silicon substrate to bend in the direction of a convex shape. This compensates for the concave bending of the substrate caused by the conductive area. This avoids problems in the manufacture of the silicon capacitor. The concave bending of the silicon substrate has the disadvantage that in conventional manufacturing devices the substrates are held on supports by vacuum (so-called vacuum chucks). A concave bending of the substrate means that the substrate can no longer be sucked in, so that automated production is not possible. Slightly convex shaped substrates, however, can be sucked onto these carriers, since the substrate edge tends to seal against atmospheric pressure.

A layer of thermal SiO 2 is particularly suitable as an auxiliary layer which is under compressive mechanical stress. The incorporation of oxygen during the formation of SiO 2 by thermal oxidation of silicon leads to a compressive mechanical stress in the layer of thermal SiO 2 on the silicon base. Alternatively, a layer of undoped polysilicon can be used. When a layer of polysilicon is grown, many small crystals grow in the lower part of the layer, which compete for further growth in the course of the layer deposition. As a result, the polysilicon layer is under compressive mechanical stress.

If, after the formation of the perforated structures, the conductive region, the dielectric layer and the conductive layer, the silicon substrate has such a deflection that there is a height difference of up to about 500 μm between the center and the edge of the silicon substrate, this can be concave Compensate for bending with an auxiliary layer of thermal oxide in a layer thickness of 30 to 250 nm. The auxiliary layer made of thermal oxide is under a compressive stress of about 10 ^ N / cm.2. _e j_ use of a Auxiliary layer made of polysilicon requires a layer thickness between 50 nm and 100 nm.

It is conceivable to compensate mechanical stresses in a silicon substrate, which are caused by layers that contract more than silicon, by applying a correspondingly thick silicon nitride layer on the back of the silicon substrate. In the production of a silicon capacitor, however, it has been shown that such silicon nitride layers with manageable thicknesses of approximately 1 μm cannot compensate for the concave bending of the silicon substrate. Estimates have shown that the thickness of the silicon nitride layer on the back of the silicon substrate should be between 20 and 50 µm. However, such layer thicknesses are not technically justifiable.

The hole structures are preferably formed by electrochemical etching in a fluoride-containing acid electrolyte, the main surface being in contact with the electrolyte and a voltage being applied between the electrolyte and the silicon substrate in such a way that the silicon substrate is connected as an anode. A back side of the silicon substrate opposite the main surface is illuminated during the electrochemical etching. As a result, perforated structures with diameters in the range between 0.5 μm and 10 μm and with depths in the range between 50 μm and 500 μm can be formed, the perforated structures each having an aspect ratio in the range between 30 and 300. The aspect ratio is the quotient of depth to diameter. The higher the aspect ratio, the more serious the concave bending of the silicon substrate becomes due to the conductive area that extends along the surface of the hole structures.

Alternatively, the hole structures can be formed by masked or unmasked anisotropic etching. The dielectric layer is preferably a multiple layer with a layer sequence of SiO 2, and SiO 2 formed. Such layers, which are often referred to as ONO layers, can be formed with very low defect densities. This is an essential prerequisite for the production of the silicon capacitor, which has a large surface due to the surface enlargement due to the hole structures.

To produce contacts to the conductive layer and / or the conductive region, which act as capacitor electrodes in the finished silicon capacitor, the surface of the conductive layer is preferably exposed in the region of the main surface. The auxiliary layer remains on the surface of the hole structures. For contacting the conductive area, the surface of the conductive area is also exposed in the area of the main area. Here too, the auxiliary layer remains in the area of the hole structures.

The invention is explained in more detail below on the basis of an exemplary embodiment which is illustrated in the figures.

FIG. 1 shows a section through a silicon substrate after the formation of hole structures, a conductive region along the surface of the hole structures, a dielectric layer, a conductive layer and an auxiliary layer and after filling up the hole structures.

FIG. 2 shows the section through the silicon substrate after exposing the conductive layer in the region of the main surface and exposing the surface of the conductive region to form a contact.

A silicon substrate 1 made of n-doped, single-crystal silicon, which has a resistivity of 5 ohm x cm. points, is provided by electrochemical etching on a main surface 11 with a multiplicity of hole structures 2 (see FIG. 1).

For this purpose, the main surface 11 is brought into contact with an electrolyte. For example, a 6 weight percent hydrofluoric acid (HF) is used as the electrolyte. The silicon substrate 1 is acted on as a anode with a potential of 3 volts. The silicon substrate 1 is illuminated from a rear side opposite the main surface 11. A current density of 10 A / cm ^ is set. During electrochemical etching, minority charge carriers in the n-doped silicon move to the main surface 11 in contact with the electrolyte. A space charge zone is formed on the main surface 11. Since the field strength in the area of depressions in the main surface 11 is greater than outside it, the minority charge carriers preferably move to these points. This leads to a structuring of the main surface 11. The deeper an initially small unevenness becomes due to the etching, the more minority charge carriers move there and the stronger the etching attack at this point.

The perforated structures 2 begin to grow from unevenness in the main surface 11, which are present with a statistical distribution in each surface. In order to achieve a uniform distribution of the hole structures 2, it is advantageous to provide the main surface 11 with unevenness in a targeted manner prior to the electrochemical etching, which unevenness act as a seed for the etching attack in the subsequent electrochemical etching. These bumps can be produced using conventional photolithography, for example.

After approximately 180 minutes of etching time, the perforated structures have a substantially circular diameter of 2 μm at a depth of 175 μm. Then the silicon substrate 1 is rinsed with water.

A conductive region 3 is produced along the surface of the hole structures and is provided with an electrically active dopant. As an electrically active dopant

Example phosphorus with a dopant concentration between 10 ^ 0 cm ^~ 3 _U ^ nd 10 1 cm ^"3 or boron having a dopant concentration between 10 ^ 0 ^~ 3 cm and 10 cm ^ ^1" is used. Thereby, the conductive region 3, an electrical conductivity of about 10 ^-3 _cm. It is therefore suitable as a capacitor electrode.

In order to produce the conductive region 3, a gas phase diffusion is carried out using phosphine or borane at a temperature of 1400 ° Kelvin. Alternatively, the electrically active dopant can also be diffused in by depositing an appropriately doped silicate glass layer and diffusing out of the silicate glass layer. This silicate glass layer must be removed again after the diffusion out.

A dielectric layer 4 and a conductive layer 5 are then applied to the surface of the conductive region 3. The dielectric layer 4 is preferably formed by combined production of SiO 2 and Si3N4 as a multiple layer with a layer sequence SiO2 / Si3N4 SiO2, since this material has a defect density which is sufficiently low for a large-area capacitor. The dielectric layer 4 is produced as a multilayer with a layer sequence SiO 2 / Si3N4 SiO 2 with layer thicknesses of, for example, 5 nm SiO 2, 20 nm Si3N4 and 5 nm SiO 2.

The conductive layer 5 is formed, for example, from n ⁺ -doped polysilicon. It is formed in a layer thickness of, for example, 400 nm. As a result, it takes about 20 to 50

Percent of the usable diameter of the hole structure 2. In situ doping is used to form the conductive layer 5 Polysilicon deposited or undoped polysilicon, which is then doped by diffusion.

An auxiliary layer 6 is subsequently formed, which is under compressive mechanical tension. The auxiliary layer 6 is preferably formed by thermal oxidation at, for example, 900 ° C., 2000 seconds. The auxiliary layer 6 is formed in a layer thickness of 30 to 250 nm, preferably 50 nm. The auxiliary layer 6 is under a compressive voltage of approximately 10 ^ N / cm 4 and thereby compensates for the doping in the conductive region 3 and, if appropriate, the dielectric layer 4 and the conductive layer

5 caused concave bending of the silicon substrate 1.

An n-doped reference substrate is usually used to measure the thickness of the auxiliary layer 6, and an oxide layer is simultaneously formed on its flat surface. Since the oxidation rate on the surface of the n ⁺ -doped conductive layer 5 is greatly increased, the thickness of the auxiliary layer 6 on the surface of the conductive layer 5 is a factor of 2 to 4 thicker than the thickness of the oxide layer on the flat surface of the reference substrate. The thickness of the auxiliary layer

6 on the reference substrate is typically 10 to 60 nm.

Alternatively, the auxiliary layer -6 is formed from undoped polysilicon. In this case it has a thickness of 100 nm.

Subsequently, the remaining space in the hole structures 2 is filled by depositing a polysilicon layer 7. The polysilicon layer 7 is formed in a layer thickness of 800 nm, for example.

In the silicon capacitor, the conductive layer 5 and the conductive region 3 act as capacitor electrodes. It is to form connections to the capacitor electrodes to t μ »μ>

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Claims

Patent claims

1. Process for producing at least one silicon capacitor,

- in which a large number of hole structures (2) are produced in a main surface (11) of a silicon substrate (1),

- where along the surface of the hole structures

(2) a conductive one provided with an electrically active dopant

Area (3) is created,

- on the surface of the conductive area

(3) a dielectric layer (4) and a conductive layer (5) are applied, which do not fill the hole structures (2),

- in which an auxiliary layer (6) with essentially conformal edge coverage is formed on the surface of the conductive layer (5), which is under a compressive mechanical tension,

- in which the hole structures (2) are filled. 2. Method according to claim 1,

a voltage is applied so that the silicon substrate (1) is connected as an anode,

- in which a back side of the silicon substrate (1) opposite the main surface (11) is illuminated during the electrochemical etching.

4. The method according to any one of claims 1 to 3, in which the hole structures (2) are produced with diameters in the range between 0.5 μm and 10 μm and with depths in the range between 50 μm and 500 μm, the hole structures (2) have an aspect ratio in the range between 30 and 300.

5. Method according to one of claims 1 to 4, in which the dielectric layer (4) is formed as a multiple layer with a layer sequence of Siθ2 Si3N4 and Siθ2.

6. Method according to one of claims 1 to 5,

- in which the conductive region (3) is formed with a dopant concentration between 10^0 cm ^~ and 10^1 cm "3 phosphorus or with a dopant concentration between 10^0 cm ^~ 3 and 10^1 cm ^" 3 boron,

- in which the dielectric layer (4) is formed with a thickness between 10 nm and 100 nm,

- in which the conductive layer (5) is formed from doped polysilicon,

- in which the auxiliary layer (6) is formed by thermal oxidation from Siθ2 in a layer thickness between 30 nm and 250 nm,

in which the hole structures (2) are filled with polysilicon.

7. Method according to one of claims 1 to 5,

- in which the conductive region (3) has a dopant concentration between 10^0 c ^~ 3 _U and 10^1 cm ^~ 3 phosphorus or with a dopant concentration between 10^0 _C m ^~ 3 and 10^ ¹ cm ^~ 3 boron is formed,

- in which the dielectric layer is formed with a thickness between 10 nm and 100 nm,

- in which the conductive layer (5) is formed from doped polysilicon,

- in which the auxiliary layer is formed from undoped polysilicon with a layer thickness between 50 nm and 200 nm.

8. The method according to any one of claims 1 to 7, in which, in order to form an electrical connection to the conductive layer (5) in the area of the main surface (11), the auxiliary layer (6) is removed from the surface of the conductive layer (5), while the auxiliary layer (6) remains in the area of the hole structures (2) on the surface of the conductive layer (5).