EP0958596A1

EP0958596A1 - Screening oxide for source and drain regions formed from solid dopant source

Info

Publication number: EP0958596A1
Application number: EP97933371A
Authority: EP
Inventors: Ebrahim Andideh
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 1996-09-24
Filing date: 1997-07-10
Publication date: 1999-11-24
Also published as: IL129151A0; AU3657197A; JP2001501037A; WO1998013861A1; KR20000048595A

Abstract

A screening oxide (9, 22) for use in the formation of source/drain regions (40, 41) in an MOS transistor where the dopant for these regions is obtained from a solid dopant source (16, 35). The silicon based screening oxide (9, 22) (5-100Å thick) is formed between the substrate and for example, an overlying boron doped glass (16, 35) which provides the source of dopant for the source/drain region (40, 41). Dopant is diffused through the oxide screening layer (9, 22). The screening oxide (9, 22) prevents a highly doped film from being formed on the substrate which otherwise prevents the formation of salicides. Additionally, the screening oxide (9, 22) can be used to modulate the depth and concentration of the dopant of the source and drain regions (40, 41).

Description

SCREENING OXIDE FOR SOURCE AND DRAIN REGIONS FORMED FROM SOLID DOPANT SOURCE

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of forming self-aligned source and drain regions for field-effect transistors from solid dopant sources.

2. Related Art

In co-pending application Serial No. 498,028, filed on July 3, 1995, entitled "Low Damage Doping Technique for Self-Aligned Source and Drain Regions", a process is described for forming source and drain regions from a solid dopant source. In one embodiment the dopant from a glass layer is driven into the substrate to form the source and drain regions. One problem that has been encountered with this process is that the dopant from the glass may form a thin film on the surface of the substrate which is not easily removed when the glass layer is etched away. This is particularly a problem where a salicide contact is formed in contact with the source or drain regions. As will be seen, the present invention provides a screening layer that solves the problem of this undesirable film.

Screening layers have been used in connection with ion implantation to, for instance, protect the surface of the silicon during ion implantation. These are relatively thick layers not suited for use with a solid dopant source as described above. SUMMARY OF THE INVENTION

An improved process for forming a semiconductor device on a silicon substrate where a dopant is diffused from a doped layer into the substrate to form source and drain regions is described. A thin oxide screening layer is formed between the doped layer and the substrate. The dopant is diffused through the oxide layer into the substrate to form the source and drain regions.

In one embodiment the oxide layer comprises a silicon based oxide having a thickness of between 5A and lOOA. This layer can be used to modulate the dopant diffusion into the silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a cross sectional elevation view of a section of a substrate showing an n-well isolated from a p-well. Polysilicon gates and a screening oxide layer in accordance with the present invention are also shown.

Figure 2 illustrates the substrate of Figure 1 after the formation of a first doped glass layer over the screening oxide layer.

Figure 3 illustrates the substrate of Figure 2 after a first photoresist layer has been masked and etched, and during an ion implantation step used to form the tip regions for the n-channel transistor.

Figure 4 illustrates the substrate of Figure 3 after the formation of a TEOS layer and a silicon nitride layer.

Figure 5 illustrates the substrate of Figure 4 after the silicon nitride layer has been anisotropically etched to form spacers and after the substrate has been covered with a second screening layer and a second doped glass layer.

Figure 6 illustrates the substrate of Figure 5 after the masking and patterning of a photoresist layer and during an ion implantation step used to form the main portion of the source and drain regions for the n-channel transistor.

Figure 7 illustrates the substrate of Figure 6 after diffusion of the boron dopant from the glass layers through the screening layers to form the source and drain extension regions for the p-channel transistor.

Figure 8 is an enlarged section of the substrate of Figure 7 generally taken at section line 8-8 after etching of the second glass layer and second screening layer.

Figure 9 is a graph used to illustrate the modulating effects on source and drain region sheet resistance from the screening oxide layer of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A method and structure is described for forming low damage, shallow source and drain regions in a field-effect transistor where a solid state dopant source and screening layer are used. In the following description, numerous well-known steps such as masking and etching steps are not discussed in detail in order not to obscure the present invention. In other instances, specific details are set forth such as specific boron dopant concentrations in order to provide a thorough understanding of the present invention. It will be apparent that the present invention may be practiced without using these specific details.

The various layers of materials shown in the drawings are not shown to scale. Rather, the layers have been made visible so that the present invention can be better understood from the drawings. Additionally, only a portion of a substrate showing a single p-channel and n-channel transistor is illustrated. It will be appreciated that in practice the invention is used to fabricate an entire integrated circuit.

While the present invention is not limited to any particular geometry, in one embodiment, it is used for the fabrication of transistors having a sub micron channel length that operate from 2.5 volts or less supply.

Referring now to Figure 1 , a section of a monocrystalline silicon substrate is illustrated having an n-well 21 and a region designated as a p-well. As will be seen, it is not important to the present invention whether both n and p- wells are used. For instance, an n-well may be used for fabricating p-channel transistors with the n- channel transistors being formed directly in the substrate.

The n and p-well of Figure 1 are isolated from one another by a recessed isolation region, specifically trench 10. Additionally, within the n-well 21 there are other isolation trenches 12 for isolating from one another p-channel transistors formed within the n-well. Likewise, there are isolation trenches 13 formed within the p-well to isolate n-channel transistors formed in the p-well from one another. The isolation trenches may be formed using well-known technology. Other isolation technologies such as local oxidation of silicon (LOCOS) may be used instead of trenches

A gate insulative layer (such as a high quality, thermally grown oxide to insulate the gate from the substrate) is formed over the substrate. Following this, a polycrystalline silicon (polysilicon) layer is deposited and the gates for the field-effect transistors are fabricated using ordinary photolithographic and etching techniques. Two such gates insulated from the substrate are shown in Figure 1. Gate 11, formed above the n-well, as will be seen, is used for a p-channel transistor; the other gate 14, formed above the p-well, is used for an n-channel transistor. Numerous steps typically used before the fabrication of the gates are not illustrated, such as cleaning steps, ion implantation steps to adjust voltage threshold, etc.

Following the formation of the gates 11 and 14 a screening oxide layer in accordance with the present invention is formed over the entire substrate. This is shown as oxide layer 9 of Figure 1. This layer may be for instance, an undoped plasma formed oxide layer based on silane chemistry (e.g., SjH4 + N2O) or tctraethyl orthosilicate (TEOS) based chemistry (e.g., TEOS + O2 or O3). The undoped layer may also be formed with chemical vapor deposition (CVD) processes. Other chemistries which provide an undoped silicon-based oxide layer may be used. The oxide layers described above are between 5A and IOOA in thickness. In one embodiment, this undoped oxide layer is formed in the same chamber as that used to form the subsequently deposited doped glass layer. The oxide layer may also be formed in a separate chamber.

The screening oxide layer, as will be discussed later, protects the substrate from for instance, the highly doped boron glass layer subsequently formed for a solid dopant source for the p-channel transistors. The screening oxide layer prevents the formation of a film or skin that cannot readily be removed that would otherwise be formed at the interface between the doped glass layer and the substrate. Additionally, as will be discussed the screening layer aids in modulating the junction depth and dopant concentration of the source and drain regions.

Following the formation of the gates 11 and 14 and the screening layer 9, borosilicate glass (BSG) layer 16 as shown in Figure 2 is deposited over the entire substrate. This layer which may be 10θA-3(X)A thick, in one embodiment has a 2% concentration of a p-type conductivity dopant (boron). Layer 16 is referred hereinafter sometimes as the 2% BSG layer. TEOS or silane based chemistry may be used to deposit the 2% BSG layer at a temperature of 350-6O0°C.

As described in this application, the p-channel transistor is formed using the screening oxide of the present invention while the n-channel transistor is formed using well-known ion implantation. The screening oxide of the present invention may also be used between an n-type solid dopant source and the substrate where the n-channel transistors are formed from such a dopant source.

Figure 3 illustrates the first of two ion implantation step used in the formation of the n-channel transistor. First, a photoresist layer 17 is formed over the substrate 15. This layer is masked and developed with well-known techniques to reveal the substrate regions where the source and drains are formed for the n-channel transistors and additionally, regions where an n-type dopant is used for well tap 20. This is shown in Figure 3 where the photoresist members 17 protect predetermined areas of the substrate while leaving exposed other areas. Next, the exposed portions of glass layer 16 are etched in alignment with the photoresist members 17. This etching step uses a hydrogen fluoride (HF) based solution. As shown in Figure 3 the doped glass layer 16 and screening layer 9 has been etched away. This is not necessary since the ion implantation can occur through the thin screening layer. The substrate is now subjected to ion implantation of an arsenic dopant as shown by the arrows 18. This forms the regions 19 in alignment with the gate 14 and a region 20 between the trenches 12. This arsenic doping implant is relatively light and is used for forming the tip regions of the source and drain regions for the n-channel transistor. The main portions of the source and drain regions for this n-channel transistor are subsequently formed with the second ion implantation step.

Next, as shown in Figure 4, a conformal layer 30 of undoped silicon dioxide is formed by low pressure chemical vapor deposition; other undoped LPCVD oxide films may be used. This layer provides an etchant stop for the spacers formed for the n-channel transistor. The oxide layer 30 may be 5θA-30θA thick.

Now, as shown in Figure 4 a conformal layer 31 of silicon nitride is formed over the TEOS layer 30. (An oxide layer may be used instead of the silicon nitride layer.) This silicon nitride layer is approximately 80θA thick in one embodiment Well-known anisotropic etching is used to etch the silicon nitride layer to form spacers 31 shown on opposite sides of gates 1 1 and 14 of Figure 5. The TEOS layer acts as an etchant step to protect the silicon. The TEOS and BSG regions not covered by the nitride spacers are also etched away. A wet or dry etchant may be used for this purpose. In accordance with the present invention a second screen oxide is now formed over the substrate. This oxide is formed in the same manner as the first screening oxide that is, it is an undoped Sjθ2 having a thickness of 5A to lOOA as shown by layer 22 of Figure 5. If in the prior processing the layer 9 is not removed from the exposed portions of the substrate, then the second screening layer is unnecessary since the second glass layer, which is subsequently formed would be screened from the substrate by layer 9.

Now a second layer 35 of BSG is formed over the second screening oxide. This time, however, the layer has a 6% concentration of boron (6% BSG). This layer in one embodiment is approximately 10θA-60θA thick and is deposited using a TEOS or silane based chemistries at a temperature of 350-600°C.

Better results may be achieved for some processes if a relatively thin cap layer (e.g., IOOA) of undoped glass or silicon nitride (not shown) is formed over the 6% BSG layer. This undoped layer protects the 6% BSG from a subsequent photoresist layer formed over the glass and assures that dopant will not diffuse upward. This layer also prevents moisture from the environment and other process steps from reacting with the boron dopant.

As shown in Figure 6, following the formation of the 6% BSG layer 35, a photoresist layer 40 is deposited, exposed and developed to open generally the same areas that were exposed in Figure 3 for n-channel devices. Specifically, gate 12, the areas adjacent to gate 12 (source and drain regions) and region 20; the remainder of the substrate shown in Figure 6 is protected by the photoresist members 40.

The cap layer over the glass layer 35 (if used) and the 6% BSG layer 35 are then etched in alignment with the photoresist members 40, this is done by HF based chemistry. Again while in Figure 6 layer 22 has been etched at this point in the processing at the regions unprotected by photoresist layer 40. This is not necessary since the ion implantation can occur through layer 22.

The second n-type ion implantation step is now used to implant the arsenic dopant into the regions of the substrate not protected by the photoresist layer 40, spacers 31, or gate 12. The arrows 41 illustrate the implantation of this arsenic dopant. This dopant is used to form the main N+ portions 45 of the source and drain regions for the n-channel transistors. Note that since the spacers 31 are in place, the dopant is implanted in alignment with the spacers and not in alignment with the gate.

Following this, a driving (heating) step, is used. The p-type dopant from the 2% BSG and 6% BSG layers is simultaneously diffused though the screening layer 9 and 22 into the substrate to form both the tip regions, main source and drain regions, and doping of the gate 11 for the p-channel transistor. In one embodiment, the tip region has a depth of 300-700A and the main portion of the p-type region has depth of 1000-2500A. Additionally, the p-type dopant from the BSG layers forms a well tap between the isolation trenches 13. In one embodiment, this drive step employs rapid thermal processing. Specifically, driving at 950°C to 1080°C for 10-30 seconds with ramping up to and down from this temperature at 70°C per second. A standard Halogen lamp band rapid thermal reactor is used.

Well-known processing may be used to complete the fabrication of the integrated circuit shown in Figure 7. The glass layers 16 and 35, and the underlying screening layers to the extent remaining may remain in place for the remainder of the processing and may stay in the completed integrated circuit except where removed for contacts. That is, glass layer 35 may be removed to facilitate a subsequent selective TiSi or CoSi2 layer on gates 1 1 and 12 and regions 41 and 45.

The result of the processing described above is a source and drain region for the p-type transistor having a tip region 40 adjacent to the gate (from the dopant diffused into the substrate from the 2% BSG layer 16) and a more highly doped main portion of the source and drain regions 41 spaced apart from the gate (from the dopant diffused from the 6% BSG layer 35). For the described embodiment the p-type tip region has a dopant concentration of l-5xl0^c "3 while the main portion of the source and drain region has a dopant concentration of 2-5x1 θ20cm^~3. This results directly from the 2% and 6% BSG. Other concentrations of dopants in the glass may be used. For example, layer 16 may have a dopant concentration between 1% to 4% and layer 35 may have a dopant concentration between 5% to 12%.

In Figure 8 a portion of the region 41 of Figure 7 is shown with overlying screening oxide layer 22 and the glass layer 35. An opening has been formed through these layers to allow contact with the underlying region 41. A conductive plug 50 is disposed in the opening permitting contact with the region 41. As previously mentioned, when the screening oxide is not used, the boron doping forms a film at the interface between the layer 35 and the substrate. This dopant-rich thin layer may prevent salicide formation or cause gate to source/drain current leakage. It is chemically difficult to remove this thin skin from the wafer surface. (The salicide formation problem is detected generally by measuring the contact resistance.) This problem is cured with the screening oxide of the present invention. The thin screening oxide prevents the formation of the difficult-to-remove dopant-rich layer found in the prior art. Thus, with the present invention as shown in Figure 8, a salicide is readily formed at interface 51.

Another advantage to the present invention is that the screening layer may be used to control post diffusion substrate dopant concentration and junction depth. This is shown in Figure 8 where sheet resistance is plotted against screening oxide deposition time. The data from Figure 8 was obtained using a TEOS +O3 +(He carrier) chemistry to form the screening oxide. Ignoring initialization times, the oxide forms at the rate of approximately 5-6A per second for the example shown. Thus, at 5 seconds there is approximately 25A of the screening oxide. As can be seen, the thicker the screening oxide, the greater of the sheet resistance of the source/drain region. Thus, the screening oxide thickness can be used to control the characieristics of the source/drain region. For all the data points shown in Figure 8 the uniformity as measured by 4 point probe test were acceptable with no significant difference for any of the data points.

Thus, a screening oxide has been disclosed for use in the fabrication cf source/drain regions where the regions are formed by diffusing a dopant through the screening oxide from a solid dopant source.

Claims

1. An improved process for forming a semiconductor device on a silicon substrate where a dopant is diffused from a doped layer into the substrate, comprising the steps of: forming an oxide layer between the doped glass layer and the substrate; and diffusing the dopant through the oxide layer into the substrate.

2. The process defined by claim 1 wherein the oxide layer is an undoped layer.

3. The process defined by claim 2 wherein the oxide layer is between 5A and lOOA thick.

4. The process defined by claim 1 wherein the oxide layer is a silicon dioxide layer.

5. The process defined by claim 4 wherein the oxide layer is an undoped oxide layer.

6. The process defined by claim 5 wherein the oxide layer is between 5A and lOOA thick.

7. The process defined by claim 1 wherein the oxide layer is an undoped plasma formed layer between 5A and lOOA thick.

8. The process defined by claim 1 wherein the oxide layer is an undoped silane formed layer between 5A and lOOA thick.

9. The process defined by claim 1 wherein the oxide layer is an undoped TEOS formed layer between 5A and lOOA thick.

10. The process defined by claim 1 wherein the oxide layer is formed by a chemical vapor deposition and is between 5A and lOOA thick.

1 1. The process defined by claim 1 wherein the oxide layer is thermally grown to a thickness of between 5A and 100 A thick.

12. A improved process for fabricating an MOS transistor wherein at least a portion of the source and drain regions are formed by diffusing a dopant from a doped layer into the substrate, comprising the steps of: forming a silicon based insulative region of 5A to lOOA thick between the sites of the source and drain regions and the doped layer; forming at least a portion of the source and drain regions by using dopant from the doped layer; and removing at least a portion of the insulative layer so as to expose underlying substrate after the preceding step.

13. The process defined by claim 12 including the formation of a conductive member on, at least part of the underlying substrate.

14. The process defined by claim 13 wherein the conductive member comprises a salicide.

15. In a semiconductor integrated circuit formed on a silicon substrate an improvement comprising: a source region and drain region disposed in the substrate; a doped glass layer disposed generally above at least a portion of the source region and drain region, the glass layer having provided a source of dopant for the source region and drain region; and an oxide layer disposed between the doped glass layer and source region and drain region.

16. The improvement defined by claim 15 wherein the oxide layer is a silicon dioxide layer.

17. The improvement defined by claim 16 wherein the oxide layer is between 5 A and lOOA thick.