EP0952509B1 - Voltage reference circuit - Google Patents

Description

The present invention relates to a reference voltage circuit, in particular a reference voltage circuit according to the preamble of claim 1, which supplies a tunable reference voltage.

Integrated circuits that are not operated from a stabilized supply voltage internally require a reference voltage source. This applies in particular to voltage regulators whose output voltage serves as reference voltage for other integrated circuits or circuit blocks.

In principle, the forward or forward voltage of a diode or, in general, a pn junction, e.g. As the base-emitter voltage of a bipolar transistor, are used as a reference voltage. However, the forward voltage of a pn junction has a negative temperature coefficient, which has a negative effect on many applications. If, for example, by means of a voltage regulator whose output voltage serves as a reference voltage, sensors, A / D converter or similar components are supplied, the output voltage of the voltage regulator must be highly accurate and in particular extremely temperature stable.

Therefore, bandgap or bandgap reference voltage circuits are preferably used as reference voltage sources that provide a temperature-stabilized reference voltage. These known bandgap reference voltage sources are based on an addition of a forward voltage of a current-carrying pn junction and a differential voltage multiplied by a corresponding factor, which is formed from two voltages of two pn junctions through which different current densities flow. Generally, the river voltage has a current-carrying pn junction - as has already been explained before - a negative temperature coefficient. By contrast, the difference between two forward voltages increases proportionally to the absolute temperature and is therefore subject to a positive temperature coefficient. If the factor by which the differential voltage explained above is multiplied is set so as to cancel the negative temperature coefficient of the forward voltage of the pn junction with the positive temperature coefficient of the differential voltage, a temperature-stabilized output voltage can be obtained. In particular, the output voltage of such a reference voltage source, which is obtained by adding the above-described forward voltage of a current-carrying pn junction with the differential voltage also explained above, about 1.25 V, which corresponds approximately to the band gap (bandgap) of silicon. Therefore, such reference voltage sources are referred to as bandgap reference voltage sources.

FIG. 2 shows a generalized circuit diagram of a known bandgap reference voltage source. Via a current source I ₀ , which supplies an impressed current I _bias , a current mirror circuit is connected to a positive supply voltage _terminal V _cc . The current mirror circuit comprises two resistors R3 and bipolar transistors T16-T21. The current mirror circuit generates output currents I _C1 and I _C2 , which are supplied to the npn bipolar transistors T1 and T2 connected according to FIG. The base terminals of the two transistors T1 and T2 are connected to each other, wherein the base voltage U of the transistor T1 is highly multiplied by a voltage divider consisting of two resistors R5 and R4, so that at the resistor R4 a desired output or reference voltage U _ref can be tapped. With the output terminal of this reference voltage circuit, a transistor T10 is coupled, whose task is to regulate the output voltage U _ref to a constant value, if the output of the bandgap shown in Figure 2 - reference voltage source with an uneven load is loaded. Instead of the transistor T10, any desired actuator, for example an operational amplifier or a MOS field-effect transistor, can be used, which can take over the previously described control task.

With the aid of the current mirror T16-T21 shown in FIG. 2, the currents flowing through the transistors T1 and T2 are adjusted, wherein the currents I _c1 and I _{C2 are} usually the same. In BICMOS or BICDMOS circuits, however, the current I _{C1 is} often also set to a multiple value of the current IT2. The transistors T1 and T2 have different emitter areas, the emitter area of the transistor T2 corresponding to a multiple of the emitter area of the transistor T1, so that correspondingly the emitter current density of the transistor T1 corresponds to a multiple of the emitter current density of the transistor T2.

At the common base terminal of the transistors T1 and T2, the sum voltage from the base-emitter voltage of the transistor T1 and the voltage applied to a node between resistors R1 (consisting of the partial resistors R1a and R1b) and R2 voltage is tapped. The first-mentioned base-emitter voltage of the transistor T1 corresponds to the forward voltage of a current-carrying pn junction and therefore has - as has been explained above - a negative temperature coefficient. The voltage drop across the resistor R1 or to the resistors R1a and R1b depends on the difference between the base-emitter voltage of the transistor T1 and the base-emitter voltage of the transistor T2 and, as has also been explained above, a positive temperature coefficient. By appropriate selection of the resistors R1 and R2 as well as the previously mentioned relationship between the emitter areas of the transistors T1 and T2, the bandgap reference voltage source shown in FIG. 2 can be dimensioned such that the differential voltage applied to the resistor R1 is selected from the flux voltages of the two transistors T1 and T2 is subject to a negative temperature coefficient compensating positive temperature coefficient. In this case, the desired temperature-stabilized bandgap reference voltage of approximately 1.25V is applied to the common base terminal of the transistors T1 and T2, which is highly multiplied by the divider with the resistors R4 and R5.

Bandgap reference voltage circuits of the type shown in Figure 2 are used, for example, in BICDMOS technology (bipolar, C and D-MOS technology) for precise voltage regulators. Such reference voltage circuits are specified for a relative error of at most ± 1% in the temperature range of -40 ° C to 150 ° C, so that a corresponding calibration or an adjustment of the reference voltage circuit is provided. In order to keep manufacturing spreads as low as possible, each system is adjusted individually during manufacture to the desired voltage value.

Reference voltage circuits of the type shown in FIG. 2 are frequently used on chips which, in addition to normal switching regulators, also include circuit breakers. This applies, for example, especially for automotive applications. These power transistors are monitored by integrated temperature sensors, which in turn require a temperature-stable voltage reference to be able to safely switch dynamically in the desired high temperature range of 250 ° C (transistor core temperature). Taking into account the thermal gradient of the particular chip used, it can be assumed that the bandgap reference voltage circuit used must be as temperature stable as possible up to a temperature of 200 ° C or a relative error of ± 2.5% in the extended temperature range must not exceed.

However, this is counteracted by thermal barrier leakage currents, which start at around 140 ° C and increase exponentially with increasing temperature. Therefore, there is a need to minimize the influence of the thermal junction leak currents on the reference voltage provided by the reference voltage circuit. As has already been explained above, options for calibrating or balancing the output voltage of the reference voltage circuit are generally provided. In such adjustment circuits, however, leakage currents also occur, which usually exert a great influence on the temperature stability of the reference voltage circuit, especially at high temperatures. This will be explained in more detail below with reference to FIG.

The adjustment of the reference voltage supplied by the reference voltage source is usually carried out by switching the divider ratio R1 shown in Figure 2: R2, which can be realized by correspondingly parallel to be switched resistors. FIG. 3 shows, by way of example, a corresponding matching circuit connected to the resistors R1a and R1b shown in FIG. 2, wherein so-called "zapping" diodes are used as adjustment switches, which break down when a high external voltage is applied and generate a low-resistance connection. FIG. 3 shows such a "zapping" diode in the form of an npn bipolar transistor T22, which can be made to break through by applying a correspondingly high balancing voltage to the terminals Z _1N and Z _GND . In this case, the resistor R1a is short-circuited due to the breakdown of the diode formed in the bipolar transistor T22, and thus the total resistance value of the resistor R1 consisting of the resistors R1a and R1b in FIGS. 2 and 3 is changed. The change in the divider ratio of the resistors R1 and R2 has a direct effect on the difference voltage of the base-emitter voltages of the bipolar transistors T1 and T2 applied to the junction between the resistors R1 and R2 (see FIG. out, so by a corresponding change this. Divider ratio R1: R2 can be set or adjusted at the base of the transistor T1 voltage and thus the output from the reference voltage source reference voltage U _ref .

Since the transistor T22 forming the "zapping" diode has a blocking layer to the substrate (barrier insulation) indicated by a diode D1 in FIG. 3, collector-substrate leakage currents _I.sub.sub22 (or, in the case of diodes not short-circuited) occur at high temperatures Collector-base leakage currents), which falsify the divider ratio R1: R2 and thus the output voltage U _ref . Furthermore, voltage clamping circuits are required for such shunt shunts to protect the circuit from the high voltages encountered during calibration at the balance terminals. Such a voltage clamping circuit is shown in Figure 3 with a diode D3, a transistor T23 and a resistor R13. The collector of the transistor T23 has a barrier layer to the substrate, indicated by a diode D2 in FIG. 3, so that collector-substrate leakage currents Isub23 also occur with respect to this transistor T23, in particular by the high balancing voltages for protecting the balancing circuit provided voltage clamping circuit, the leakage current effect described above is even enhanced.

Thus, the circuit shown in Figure 3 can no longer be operated with the required accuracy from temperatures of about 160 ° C. Another disadvantage of this circuit is the finite resistance of the "zapping" diode after its breakthrough, since this resistor is connected in series with the actual balancing resistor and thus also undesirably falsifies the output voltage.

No. 4,751,454 describes a temperature-independent reference voltage source, the current sources designed as transistors and a bipolar transistor comprising bandgap circuit. The current sources control the bandgap circuit for generating a temperature-independent reference voltage. An adjustment of the bandgap circuit is effected by adjusting the ratio of the emitter currents of the bipolar transistors of the bandgap circuit through the current source transistors, which are each connected in parallel with four identical further transistors.

US 4,325,018 describes a reference network for a reference voltage circuit. In this circuit, an adjustment of a reference voltage provided by a bandgap circuit is made using extrapolated correction values provided by the correction network.

The present invention is therefore an object of the invention to provide a reference voltage circuit, although balanced can be; that is, at which the supplied reference voltage can be adjusted at least within certain limits, wherein nevertheless an operation of the reference voltage circuit is possible even at relatively high temperatures with sufficient accuracy.

This object is achieved according to the present invention by a reference voltage circuit having the features of claim 1. The subclaims describe advantageous and preferred embodiments of the present invention, which in turn contribute to improved temperature stability of the reference voltage circuit.

According to the present invention, the reference voltage circuit is adjusted by changing the collector current of at least one bipolar transistor of the reference voltage supplying circuit part. If the collector currents of the two bipolar transistors of the reference voltage supplying circuit part is changed, the output voltage of the reference voltage circuit can be adjusted from a preset value both up and down.

In particular, according to the preferred embodiment of the present invention, the adjustment is made by warping, ie distorting, the conversion ratio of the current mirror of the reference voltage circuit. By applying appropriate balancing voltages to balancing terminals of the reference voltage circuit, controllable switches, in particular in the form of MOS field-effect transistors, can be activated, so that in the closed state of this switch a certain current is diverted from the collector current paths between the current mirror and the two bipolar transistors. In particular, the reference voltage circuit comprises a plurality of balancing terminals which are connected to controllable switches such that upon application of a balancing voltage to the individual balancing terminals different currents from the previously mentioned collector current paths are branched off, so that different settings of the reference voltage are possible by activating different connections.

For example, measurements on silicon performed on a test circuit according to the invention have a temperature response of the reference voltage of ± 0.72% supplied by the reference voltage circuit in the temperature range of -40 ° C. to +225 ° C., with a comparison of the reference voltage within a range of ± 3% as desired. could be performed. Assuming a basic accuracy after the adjustment of ± 0.5%, the total error to be expected during manufacturing in the temperature range described above is less than ± 1.5%.

The tunable reference voltage source of the present invention is thus particularly suitable for high temperature applications of integrated circuits such. For example, for integrated voltage regulators, A / D converters or measuring circuits, which are produced by means of BICMOS processes. Since with the help of the present invention, all leakage currents can be compensated with the help of a low circuit complexity, the provision of the desired bandgap reference voltage with high accuracy and temperature stability even at working temperatures up to 250 ° C is possible.

• Figur 1 zeigt ein detailliertes Schaltbild eines bevorzugten Ausführungsbeispiels einer erfindungsgemäßen Referenzspannungsschaltung,
• Figur 2 zeigt ein Schaltbild einer bekannten Referenzspannungsschaltung, und
• Figur 3 zeigt ein Schaltbild einer bekannten Abgleichschaltung, die zum Abgleichen der in Figur 2 gezeigten Referenzspannungsschaltung eingesetzt wird.

The invention will be explained in more detail below with reference to a preferred embodiment with reference to the accompanying drawings.

• FIG. 1 shows a detailed circuit diagram of a preferred embodiment of a reference voltage circuit according to the invention,
• Figure 2 shows a circuit diagram of a known reference voltage circuit, and
• FIG. 3 shows a circuit diagram of a known matching circuit which is used for balancing the reference voltage circuit shown in FIG.

In the present invention, the principle of reference voltage generation explained with reference to FIG. 2 is furthermore used, ie the reference voltage is obtained by adding a forward voltage of a current-carrying pn junction with a differential voltage of two different forward voltages from corresponding current-carrying pn junctions. In particular, in accordance with FIG. 2, two bipolar transistors T1 and T2 are used in the voltage part generating the reference voltage, to the collectors of which certain collector currents I _C1 and I _{C2 are} supplied. The base terminals of the two transistors are connected to each other, while the emitters of the two transistors are coupled to one another via a resistor circuit (see Figure 2). As has already been explained with reference to FIG. 2, the reference voltage is tapped at the common base terminal of the bipolar transistors T1 and T2 and optionally multiplied by a voltage divider. The voltage applied to the base of the bipolar transistor T1 is composed of the base-emitter voltage of the bipolar transistor T1 and the voltage applied to the junction between the resistors R1 and R2. The latter voltage is dependent on the difference voltage between the base-emitter voltages of the two bipolar transistors T1 and T2. By suitable dimensioning of the voltage reference circuit can be achieved that the positive temperature coefficient of the differential voltage corresponds to the negative temperature coefficient of the base-emitter voltage of the bipolar transistor T1, so that at the common base of the bipolar transistors T1 and T2, the desired temperature-stabilized bandgap reference voltage with approx , 25V can be tapped.

As has already been explained with reference to FIG. 2, the bipolar transistors T1 and T2 are operated with different current densities. In particular, the emitter area A _{E2 of} the bipolar transistor T2 corresponds to a multiple of the emitter area A _{E1 of} the bipolar transistor T1. Likewise, the collector current I _{C1 of} the bipolar transistor T1 generally corresponds to a multiple of the collector current I _{C2 of} the bipolar transistor T2.

Under the aforementioned conditions, the voltage U tapped at the common base of the bipolar transistors T1 and T2 in the known reference voltage circuit shown in FIG. 2 can generally depend on the resistance ratio R1: R2, the collector current ratio I _C1 : I _C2, and the emitter area ratio A _E2 : A _E1 can be calculated as follows: $$\mathrm{U}\mathrm{=}{\mathrm{U}}_{\mathrm{T}}\frac{R_1}{R_2}\left(1+\frac{I_{C1}}{I_{C2}}\right)\ln \frac{I_{C1}{A}_{\mathit{e}2}}{I_{C2}{A}_{\mathit{e}1}}+U_T\ln \frac{I_{C1}}{I_S}$$

In this case, U _T denotes the temperature voltage and I _s the reverse current of the bipolar transistors. As can be seen from the above equation, the reference voltage can also be calibrated by varying the collector current ratio I _C1 : I _C2 . If it is assumed that the collector current I _{C1 is changed on} the basis of a preset value I _C1 ', the following results: $${\mathrm{I}}_{\mathrm{C}\mathrm{1}}\mathrm{=}{\mathrm{I}}_{\mathrm{C}\mathrm{1}}\mathrm{\text{'}}\left(\mathrm{1}\mathrm{+}\mathrm{k}\right)$$

wobei U' die ursprüngliche, d. h. voreingestellte Referenzspannung bezeichnet und durch folgenden Ausdruck wiedergegeben werden kann: $$\mathrm{Uʹ}\mathrm{=}{\mathrm{U}}_{\mathrm{T}}\frac{R_1}{R_2}\left(1+\frac{I_{C1}ʹ}{I_{C2}}\right)\ln \frac{I_{C1}ʹA_{\mathit{E}2}}{I_{C2}{A}_{\mathit{E}1}}+U_T\ln \frac{I_{C1}ʹ}{I_S}$$

For small adjustment steps (k≤6%), neglecting quadratic terms and using the simplification ln (1 + k) = k can be rewritten as: $$\mathrm{U}=\mathrm{U\; \text{'}}\left(1+k\frac{U_T}{\mathit{U\; \text{'}}}\left(1+\frac{R_1}{R_2}\left(1+\frac{I_{C1}\text{'}}{I_{C2}}\left(1-\ln \frac{I_{C1}{\mathrm{\text{'}A}}_{\mathit{e}2}}{I_{C2}{A}_{\mathit{e}1}}\right)\right)\right)\right)$$

where U 'denotes the original, ie preset reference voltage and can be represented by the following expression: $$\mathrm{U\; \text{'}}\mathrm{=}{\mathrm{U}}_{\mathrm{T}}\frac{R_1}{R_2}\left(1+\frac{I_{C1}\text{'}}{I_{C2}}\right)\ln \frac{I_{C1}\text{'}{A}_{\mathit{e}2}}{I_{C2}{A}_{\mathit{e}1}}+U_T\ln \frac{I_{C1}\text{'}}{I_S}$$

wobei die Konstante C ausgedrückt werden kann durch $$C\mathrm{=}\frac{{\mathrm{U}}_{\mathrm{T}}}{\mathit{Uʹ}}\left(1+\frac{R_1}{R_2}\left(1+\frac{I_{C1}ʹ}{I_{C2}}\left(1+\ln \frac{I_{C1}ʹA_{\mathit{E}2}}{I_{C2}{A}_{\mathit{E}1}}\right)\right)\right)$$

The linear relationship thus applies: $$\mathrm{U}\mathrm{=}\mathrm{U\; \text{'}}\mathrm{(}\mathrm{1}\mathrm{+}\mathrm{kC}\mathrm{)}.$$

where the constant C can be expressed by $$C\mathrm{=}\frac{{\mathrm{U}}_{\mathrm{T}}}{\mathit{U\; \text{'}}}\left(1+\frac{R_1}{R_2}\left(1+\frac{I_{C1}\text{'}}{I_{C2}}\left(1+\ln \frac{I_{C1}\text{'}{A}_{\mathit{e}2}}{I_{C2}{A}_{\mathit{e}1}}\right)\right)\right)$$

The constant C assumes a value of about C = 0.5 at the momentarily realized circuit at room temperature. In order to change the output voltage U by 3%, a change of the collector current I _{C1 of} the bipolar transistor T1 would therefore be required by 6%.

Overall, it can be seen from the above statements that by changing the collector current ratio I _C1 : I _C2 the Reference voltage supplied by the reference voltage circuit can be equalized. This realization makes use of the present invention.

FIG. 1 shows a detailed circuit diagram of a preferred exemplary embodiment of a reference voltage circuit according to the invention, in which the ratio of the current mirror used is distorted by external trimming measures in order to change the collector current ratio I _C1 : I _C2 . In particular, a reference voltage circuit implemented in automotive applications (eg airbag) is shown in FIG.

Also in the case of the reference voltage circuit shown in FIG. 1, a pair of transistors T1 and T2a coupled to one another is present, the emitter area of the transistor T2a being a multiple of the emitter area of the transistor T1. The collectors of these transistors collector currents I _C1 and I _{C2a are} supplied. The emitters of the two bipolar transistors are coupled to one another via a resistor circuit with resistors R1 and R2. The voltage applied to the common base of the bipolar transistors T1 and T2a base voltage is tapped and highly multiplied by a voltage divider consisting of resistors R4 and R5, so that depending on the base voltage U, the desired output or reference voltage U _ref can be output. The voltage present at the common base of the bipolar transistors T1 and T2a operated with different current densities corresponds to the sum voltage from the base-emitter voltage of the transistor T1 and the voltage present at the junction between the resistors R1 and R2, which in turn is based on the difference between the base -Emitter voltage of the transistor T1 and the base-emitter voltage of the transistor T2a depends.

Furthermore, the operating currents of the reference voltage circuit can be adjusted via the resistors R1 and R2. By multiplying or increasing the base voltage U of the bipolar transistor T1 by means of the voltage divider R4, R5, the reference voltage circuit is able to feed itself and the supply voltage penetration is negligible. Overall, the mode of operation of the reference voltage circuit shown in FIG. 1 corresponds to the mode of operation of the known reference voltage circuit shown in FIG.

As has already been explained, however, according to the present invention, at least one of the collector currents I _C1 and I _{C2a is} changed in order to be able to adjust the reference voltage U _ref delivered by the reference voltage circuit as desired. This is done in particular by a change in the mirroring or conversion ratio of the current mirror used in the known reference voltage circuit of Figure 2.

According to Figure 1, however, two current mirror circuits are present. The first current mirror comprises bipolar transistors T3-T5 and essentially corresponds to the current mirror used in FIG. The second current mirror comprises bipolar transistors T6-T8. Furthermore, a further bipolar transistor T2b is provided, which is designed, in particular, identically to the bipolar transistor T2a. The current mirrors with the bipolar transistors T3-T5 and T6-T8 are arranged such that they are connected in parallel to each other via the multiple transistors T2a and T2b. The emitter areas of the two transistors T2a and T2b are the same size, so that the base currents I _C2a and I _C2b supplied by the two current mirrors are identical.

According to the embodiment shown in FIG. 1, the mirroring ratio of the second current mirror with the transistors T6-T8 remains constant even during the adjustment of the reference voltage circuit, ie, by means of a corresponding adjustment, only the mirroring ratio of the first Current mirror circuit with the bipolar transistors T3-T5 acted. This is done as follows.

The output voltage U _ref applied to the output terminal of the reference voltage _circuit can be calibrated or calibrated via balancing terminals Z _P , Z _1N and Z _2N . For this purpose, in turn "zapping" diodes Z1-Z3 are used, which are formed by the bipolar transistors shown in Figure 1 with short-circuited base-collector path and each one of the balancing terminals Zp, Z _1N and Z _2N with the balancing ground terminal Z _{Connect GND} . By applying a certain high tuning voltage to one of these equalizing terminals, the corresponding "zapping" diode is breached, so that a low-resistance connection is produced between the base and the emitter of the corresponding "zapping" diode, which has a corresponding control of that shown in FIG shown controllable switches in the form of p-channel MOS field effect transistors result. In this case, according to FIG. 1, for example, the MOS field-effect transistors M1-M3 and M8 are assigned to the matching terminal Z _P. When applying the required high balancing voltage to a specific one of the balancing terminals associated with this balancing connection MOS field effect transistors are connected in such a way by the respective balancing connection corresponding low impedance connection of the respective "zapping" diode, which is assigned to the respective balancing connection current amount of the collector current Bipolar transistors T1 or T2a is branched off in the form of the branch currents IcalP and IcalN shown in Figure 1, which has a corresponding distortion of the mirror ratio of the current mirror with the bipolar transistors T3-T5 result, so that the reference voltage circuit can be calibrated within certain limits to a to achieve desired output voltage U _ref .

The reference voltage circuit shown in Figure 1 is particularly dimensioned such that by applying a tuning voltage an increase in the output voltage U _ref can be achieved at the balancing terminal Z _P , while a reduction of the output voltage U _ref by various amounts can be brought about by applying a balancing voltage to the balancing terminals Z _1N and Z _2N . In particular, the reference voltage circuit shown in Figure 1 is dimensioned such that the output voltage can be varied within a maximum calibration range of ± 3%. As can be seen from the formula for the constant C described above, such a change of the output voltage requires a change of 6% in the collector current IC1 of the bipolar transistor T1. In particular, the reference voltage circuit shown in Figure 1 is dimensioned such that an increase of the reference voltage U _ref by + 3% is achieved by applying a high tuning voltage between the terminals Z _P and Z _GND . On the other hand, the _{compensation step} achievable via the balancing connection Z _{1N is} -1% and the balancing _step achievable via the balancing connection Z _{2N is} -2%. Through an optionally common control of the balancing connections Z _P , Z _1N and Z _2N , an additive balancing of the output voltage U _ref between -3% and + 3% in 1% steps is possible in this way.

In FIG. 1, the adjustment terminal Zp is connected via a control circuit consisting of a resistor R12, two p-channel MOS field effect transistors M15 and M16 and two inverters to the first controllable MOS field effect transistor M8. This control circuit can be activated via a terminal I _P and connects the gate terminal of the MOS field-effect transistor M8 in a predefined manner with the "zapping" diode Z1. Corresponding control circuits are also provided for the further balancing connections Z _1N and Z _2N , but are not shown in FIG. 1 for the sake of clarity.

Upon activation of the adjustment terminal Z _P as a result of a breakthrough of the "zapping" diode Z1, the MOS field effect transistor M8 is turned on and a certain current I3a via a further bipolar transistor T9 from the second current mirror (bipolar transistors T6-T8) decoupled. This decoupled current I3a is supplied to the MOS field-effect transistors M1-M3 and causes a certain adjustment current IcalP is branched off from the collector current path of the bipolar transistor T2a, which refers to the two MOS field-effect transistors M2 and M3 in the form of the currents shown in FIG Ical1P and Ical2P splits. In this way, the mirroring ratio of the current mirror is defined with the bipolar transistors T3-T5 warped defined and the current density of the bipolar transistor T2a reduced, which accordingly has an increase in the node between the resistors R1 and R2 tapped differential voltage result, so that the desired 3% - Increase of the output voltage U _ref can be achieved.

In an analogous manner, by applying an appropriate balancing voltage to the balancing terminals Z _1N and Z _2N, a predefined current I3b or I3c is coupled via the transistor T9 and fed to the MOS field effect transistors M4 and M5 or M6 and M7, so that a predefined However, in this case, trimming current IcalN is diverted from the collector current path of bipolar transistor T1. This balancing current IcalN is dissipated in the form of the currents Ical1N and Ical2N shown in FIG. 1 via the correspondingly conductive MOS field-effect transistors M5 and M7, respectively, and leads to a defined reduction in the collector current density of the bipolar transistor T1, so that correspondingly at the node between the resistors R1 and R2 applied differential voltage is reduced, which in turn has a corresponding reduction in the output terminal of the reference voltage circuit output reference voltage U _ref result.

On the other hand, with the aid of the MOS field-effect transistors M8-M10, the trimming currents IcalP and IcalN and the out-coupled currents I3a-I3c are switched off, if no trimming voltage is applied to one of the terminals Z _P , Z _1N , Z _2N , so that the influence of the calibration circuit is zero in this case. However, this applies in the high temperature range only if it is ensured that the drain regions of the MOS field effect transistors M2 and M3 correspond to those of the MOS field effect transistors M5 and M7, since then the thermally induced drain-bulk leakage currents compensate each other and IcalP = IcalN ≠ 0, the output voltage U _{ref is} not affected. In particular, with regard to the linearity of the adjustment steps, it is advantageous to dimension the transistors M5 and M2 on the one hand and the transistors M7 and M3 on the other hand accordingly.

For the reasons mentioned above, according to FIG. 1, a dummy transistor T15 is connected to the collector and to the base of the bipolar transistor T1, although the connection of a plurality of dummy transistors T15 connected in accordance with FIG. 1 is also possible. Advantageously, the collector well of the bipolar transistor T1 is designed to be the same size as that of the multiple transistor T2a / b, so that the increased collector-substrate or collector-base generation currents of the larger multiple transistor T2a / b are compensated by the transistors T1 and T15.

In addition, in the preferred embodiment shown in FIG. 1, a structurally identical pnp bipolar transistor pair T13, T14 is provided, with the aid of which the thermal leakage currents of the pnp bipolar transistors T5 and T8 of the two current mirrors are canceled, the base of the pnp bipolar transistors T5 and T8 in each case corresponds to the Epiwanne. In addition, in order to eliminate the influence of the process-induced current amplification fluctuations on the base currents of these pnp bipolar transistors, all these bipolar transistors are advantageously operated via the currents I5a-I5c shown in Figure 1 with approximately the same current density. As can be seen in FIG. 1, these currents I5a-I5c are likewise derived from the current IC2b via a circuit with p-channel MOS field effect transistors M11-M14 via a current I4, which automatically effects a suitable adjustment of the base voltage of the bipolar transistors T13 and T14 with the voltage drops on the components T11, R11 and T12 shown in FIG. The collector voltages of the bipolar transistors T4 and T7 are thus lower than the base voltages of a diode current voltage, which compensates for the early effects of the two current mirror circuits at the operating point of the reference voltage circuit. Furthermore, a possible saturation of the pnp bipolar transistors T4 and T7 and of the npn bipolar transistor T1 can be avoided in this way.

Finally, the n-epi wells of the individual p-type diffusion resistors are preferably connected to the positive supply voltage V _cc in order to prevent the influence of the well leakage currents at the base diffusion resistances, which is not negligible at high temperatures, on the function of the reference voltage circuit.

The resistors R6-R11, which are also shown in FIG. 1, serve in particular for presetting the two current mirrors, while the bipolar transistor T10 essentially corresponds to the transistor T10 already shown in FIG. 2 and is provided as an actuator for the output terminal of the reference voltage _{circuit, by} itself the output voltage U _ref To be controlled constantly under load with uneven load.

LIST OF REFERENCE NUMBERS

T1-T23

bipolar transistor

M1-M16

MOS field effect transistor

R1-R13

resistance

D1-D3

diode

Z1-Z3

"Zapping" diode

I ₀

power source

V _cc

supply voltage

I _P , Z _P , E _1N , Z _2N , Z _GND

control terminal

Claims (20)

1. Reference voltage circuit,
   having a bipolar transistor circuit (T1, T2a, T2b), which supplies a reference voltage (U_ref) derived from a summation voltage formed from a first voltage and a second voltage, the first voltage being derived from the forward voltage of a pn junction through which current flows, and the second voltage being derived from the difference voltage between two forward voltages of corresponding pn junctions through which current flows,
   characterized by calibration means (Z1-Z3, M1-M10) for calibrating the reference voltage (U_ref) which is supplied by the bipolar transistor circuit (T1, T2a, T2b) and which, for calibration, changes the ratio of the collector currents (IC1, IC2a) of bipolar transistors (T1, T2a) of the bipolar transistor circuit.
2. Reference voltage circuit according to Claim 1, characterized in that the bipolar transistor circuit comprises a first bipolar transistor (T1) and a second bipolar transistor (T2a), in that a first collector current (IC1) is fed to the collector of the first bipolar transistor (T1) and a second collector current (IC2a) is fed to the collector of the second bipolar transistor (T2a), the emitter area of the second bipolar transistor (T2a) being a multiple of the emitter area of the first bipolar transistor (T1), so that different current densities flow through the first bipolar transistor (T1) and through the second bipolar transistor (T2a), in that the base of the first bipolar transistor (T1) is connected to the base of the second bipolar transistor (T2a), in that the emitter of the first bipolar transistor (T1) is coupled to the emitter of the second bipolar transistor (T2a) via a resistor circuit (R1, R2) in such a way that the reference voltage (U_ref) can be picked off at the base of the first bipolar transistor, the first voltage corresponding to the base-emitter voltage of the first bipolar transistor and the second voltage depending on the difference between the base-emitter voltages of the first and second bipolar transistors.
3. Reference voltage circuit according to Claim 2,
   characterized
   in that the calibration means (Z1-Z3, M1-M10) tap a first calibration current (IcalN) from the first collector current (IC1) of the first bipolar transistor (T1) and/or a second calibration current (IcalP) from the second collector current (IC2a) of the second bipolar transistor (T2a).
4. Reference voltage circuit according to Claim 3,
   characterized
   in that the calibration means (Z1-Z3, M1-M10) comprise a plurality of terminals which are coupled to the collectors of the first and second bipolar transistors (T1, T2a) via a control circuit having controllable switches (M1-M10),
   in which case, when a corresponding calibration voltage is applied to one of the terminals, another first or second calibration current (IcalN, IcalP) is in each case tapped from the first or second collector current (IC1, IC2a).
5. Reference voltage circuit according to Claim 4,
   characterized
   in that the calibration means (Z1-Z3, M1-M10) comprise three terminals.
6. Reference voltage circuit according to Claim 4 or 5,
   characterized
   in that the terminals of the calibration means (Z1-Z3, M1-M10) are coupled to diodes (Z1-Z3) which break down upon application of the corresponding calibration voltage in the reverse direction and thereby drive corresponding controllable switches (M1-M10) of the control circuit of the calibration means.
7. Reference voltage circuit according to Claim 6,
   characterized
   in that the controllable switches (M1-M10) are realized by MOS field-effect transistors.
8. Reference voltage circuit according to one of the preceding claims,
   characterized
   in that a current mirror circuit (T3-T5) is provided for generating the collector currents (IC1, IC2a) of the bipolar transistors (T1, T2a).
9. Reference voltage circuit according to Claim 8 and one of Claims 2 to 7,
   characterized
   in that the bipolar transistor circuit comprises a third bipolar transistor (T2b), which is essentially identical to the second bipolar transistor (T2a), and
   in that a further current mirror circuit (T6-T8) is coupled to the third bipolar transistor (T2b) in such a way that the current mirror circuit (T3-T5) and the further current mirror circuit (T6-T8) are connected in parallel via the second bipolar transistor (T2a) and the third bipolar transistor (T2b), the base and the emitter of the second bipolar transistor (T2a) being connected to the base and to the emitter, respectively, of the third bipolar transistor (T2b).
10. Reference voltage circuit according to Claim 9,
    characterized
    in that the emitter areas of the second and third bipolar transistors (T2a, T2b) are equal in magnitude, so that the basic currents (I_c2a, I_c2b) supplied by the two current mirror circuits (T3-T5; T6-T8) are equal in magnitude.
11. Reference voltage circuit according to Claim 9 or 10 and one of Claims 4 to 7,
    characterized
    in that the terminals of the calibration means (Z1-Z3, M1-M10) are coupled to the further current mirror circuit (T6-T8) via controllable switches (M8-M10) of the control circuit (M1-M10),
    in which case, when a calibration voltage is applied to one of the terminals, a controllable switch (M8-M10) assigned to said terminal taps off a control current (I3a-Ic3), which, for its part, leads to activation of a controllable switch (M2, M3, M5, M7) which is connected downstream of the corresponding controllable switch (M8-M10) and via which the respective calibration current (IcalN, IcalP) is tapped from the first and/or second collector current (IC1, IC2a).
12. Reference voltage circuit according to Claim 11,
    characterized
    in that the first calibration current (IcalN) is passed via two controllable switches (M5, M7) connected in parallel,
    in which case the controllable switches (M5, M7) connected in parallel can be activated by different control currents (I3b, 13c) tapped from the second current mirror circuit (T6-T8).
13. Reference voltage circuit according to Claim 12,
    characterized
    in that the second calibration current (IcalP) is passed via two controllable switches (M2, M3) connected in parallel, both of which switches can be activated by the same control current (I3a) tapped from the further current mirror circuit (T6-T8).
14. Reference voltage circuit according to Claims 12 and 13,
    characterized
    in that the drain terminals of the controllable switches (M5, M7) provided for the first calibration current (IcalN) and the controllable switches (M2, M3) provided for the second calibration current (IcalP) are connected to one another.
15. Reference voltage circuit according to Claim 13 or 14,
    characterized
    in that in each case one of the controllable switches (M5, M7) provided for the first calibration current (IcalN) is designed identically to one of the controllable switches (M2, M3) provided for the second calibration current (IcalP).
16. Reference voltage circuit according to one of Claims 9 to 15,
    characterized
    in that the base of a fourth bipolar transistor (T5) is connected to the base of the first bipolar transistor (T1) and the emitter and also collector of said fourth bipolar transistor are connected to the collector of the first bipolar transistor (T1).
17. Reference voltage circuit according to one of Claims 9 to 16,
    characterized
    in that the first bipolar transistor (T1) has a collector well which is designed to be essentially exactly the same size as the collector well of the second and third bipolar transistors (T2a, T2b).
18. Reference voltage circuit according to one of Claims 9 to 17,
    characterized
    in that the current mirror circuit (T3-T5) and the further current mirror circuit (T6-T8) each comprise two bipolar transistors (T3, T4; T6, T7) coupled to a corresponding output of the respective current mirror circuit and also one pnp bipolar transistor (T5, T8) connected to a common base terminal of said two bipolar transistors (T3, T4; T6, T7), and
    in that at least one further pnp bipolar transistor (T13, T14) is connected in parallel with the pnp bipolar transistors (T5, T8), the current mirror circuits (T3-T5 ; T6-T8) being configured in such a way that the pnp bipolar transistors (T5, T8, T13, T14) are operated with identical current densities.
19. Reference voltage circuit according to one of the preceding claims,
    characterized
    in that n-type epitaxial wells of the bipolar transistors of the reference voltage circuit are connected to a positive supply voltage terminal Vcc.
20. Reference voltage circuit according to one of the preceding claims,
    characterized
    in that the common base terminals of the first and second transistors (T1, T2a) are connected to a voltage divider circuit (R4, R5).

Images