DE3034939A1 - SIGNAL CONVERTER CIRCUIT - Google Patents

Description

Dipl.-Ing. H. MITSCHERLICH D-8000 MDNCHEN

Dipi.-Ing. K. GUNSCHMANN SteinsdcSrfstraßeiO

Dr. re r. not. W. KÖRBER * ^ ⁽⁰⁸⁹ > * ^{29 66} Dipl.-Ing. J. SCHMIDT-EVERS
PATENT LAWYERS

September 16, 198o

SONY CORPORATION

7-35 Kitashinagawa 6-chome

Shinagawa-ku

Tokyo / Japan

Signal converter circuit

The invention relates generally to a signal converter circuit, and in particular a signal converter circuit for converting a single-ended or unbalanced input signal into a differential output signal.

So far, signal converter circuits with, for example, a differential amplifier design for converting an asymmetrical Input signal into a differential output signal common practice. Such a signal converter circuit contains a pair of transistors that form a differential amplifier forms. A DC bias is applied to the bases of the transistors and one of the transistor bases is connected to ground or ground. Earth to remove any AC influence. Next is the base of the transistor that is not connected to ground A signal voltage is applied and is used by the collectors of the two transistors derived a differential output signal. However, since a bias circuit is used in such Differential amplifier is necessary, the circuit design becomes quite complicated and can reduce the tension

13Q0U / 1274

- 9 source for the transistors cannot be used effectively.

Another conventional circuit for overcoming the problems of the circuit just discussed for effective use the voltage source without using a bias circuit includes a first transistor whose base with Ground is connected via a pair of series-connected diodes through which a constant current flows. A second transistor is connected on the base side to the emitter of the first transistor and to ground via a diode, and is further there supplied with a signal current. In this circuit there are differential output currents at the collectors of the two Generated transistors. However, in order for this circuit to work properly, the one must be supplied to the pair of series diodes Constant current must be greater than the signal current. If this condition is not met, they will be sent to the collectors of the transistors generated differential output currents distorted. Further, in such a circuit, the constant current cannot be effective in satisfying the condition can be increased if the constant current is much larger than the signal current.

A third conventional circuit for overcoming the problem of the above circuit generates regardless of the relationship of the constant current and the signal current no distorted output signals and can be with a, comparatively, low voltage source be used. In such a circuit, a constant current flows out through a first path two diodes connected in series and, through a second path, a diode and the collector-emitter path of a series-connected one Transistor. The signal current becomes the connection point between the two diodes of the first path, the base of the transistor in the second path and fed to a second transistor. The collector of the first transistor is also connected to the base of a third transistor and differential output currents are applied to the collectors of the

1300-U / 1274

second and third transistor generated. In this circuit, the output currents are sent to the collectors of the second and third transistor is not distorted regardless of the relationship between the constant current and the signal current. Further is since this circuit does not require a bias circuit, the structure of the circuit is relatively simple, and only a low voltage source is required. However, the differential output currents influenced by the base current of the first transistor and the base currents of the diodes, if the latter are made up of transistors whose collectors are connected to the respective base. That means that the differential output currents due to an undesired shift or Offset current, which is a function of such base currents, influenced. This also applies if the the above circuit is modified so that a bias voltage source between the first and the second signal path and Ground is arranged and a constant current source between the emitters of the second and the third transistor and Ground is connected.

It is therefore the object of the invention to provide a signal converter circuit while avoiding the disadvantages mentioned the differential output currents can be generated which are not influenced by the base currents of any transistors used in the circuit.

According to a feature of the invention, the transducer circuit includes a current source for generating a constant current, an input signal generator for generating an input signal current, a first device that a first differential current depending on the constant current and the Input signal current generates a second device that generates a second differential current as a function of the constant current

and generating the input signal stream, wherein at least one of the first and second devices comprises a transistor has an input that is connected to a current at this input

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is supplied, an output device for generating differential output signals dependent on the first and the second differential current and a suppression device for eliminating the effect of the current at the input of the transistor on the differential output signal.

The invention thus specifies a signal converter circuit whose gain factor (gain) can be changed at least a constant current source can be controlled- Furthermore, the invention provides a signal converter circuit that the need the use of a bias source eliminated. Finally, the invention provides a signal converter circuit that effectively a (comparatively) low voltage source used for the transistors of the circuit.

The invention is explained in more detail with reference to the exemplary embodiments shown in the drawing. Show it a circuit diagram of a conventional signal converter circuit,

a circuit diagram of another already developed signal converter circuit,

a circuit diagram of part of the circuit according to FIG. 2,

a development of the circuit diagram according to FIG. 2, a circuit diagram of a signal converter circuit according to an embodiment of the invention, a circuit diagram of part of the circuit according to Fig. 5 to explain their mode of operation, a circuit diagram of part of the circuit according to FIG. 5 - to explain its mode of operation, a circuit diagram of a further embodiment of a signal converter circuit according to FIG Invention,

9 is a circuit diagram of another embodiment a signal converter circuit according to the invention.

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§034939

Fig. 1 initially shows a signal converter circuit of conventional design. The conventional signal converter circuit includes a first and a second diode 1 and 2, which are connected in series, in the forward or forward direction _t between a constant voltage source, which generates a constant current I_, and ground (or earth). A voltage drop is generated across the series connection of diodes 1 and 2 as a result of the current flowing through them from the constant current source, the generated voltage being applied to the base of an NPN transistor 3. The emitter of the transistor 3 is connected to ground via a diode 4 in the forward direction and to the base of a second NPN transistor 5s whose emitter is connected to ground. It should be mentioned, however, that the diodes 1, 2 and 4 are preferably constructed from NPN transistors whose bases are connected to the respective collectors. The diodes 1, 2 and 4 and the transistors 3 and 5 can therefore be formed as an integrated circuit on a common semiconductor chip in which, for example, the emitter area is the same for each of the elements.

A signal current i is the connection point between the

Diode 4 and the transistors 3 and 5 supplied. Hence arises a voltage drop across the diode 4 as a result of the Signal or signal current i and the current through the transistor 3j being such a voltage to the base of the transistor 5 is created. If the signal current i is equal to zero, the constant current I flows through the series combination the diodes 1 and 2, the series combination of the collector-emitter path of the transistor 3 and the diode 4 and through the collector-emitter path of transistor 5 · Es it should be noted, however, that although the collector and Emitter currents of transistor 3 are not exactly the same, the difference between them is essentially negligible, so that the current flowing through the collector-emitter path of the transistor 3 can be assumed to be approximately I_.

13ÖÖU / 1274

Similarly, the same position applies to the transistor 5. If, however, the signal current i differs from zero, the current flow through the collector-emitter path of the transistors 3 and 5 changes. Emitter current through transistor 3 on I - X ₁ as a result of adding the signal current i at the junction between transistor 3 and diode 4. That is, the current flowing through diode 4 is essentially equal to (I "- I ₁ + i) is.

vj J. S

The base current through transistor 5 is in comparison relatively small. However, since the base-emitter voltage drops across the transistor 5 and across the diode 4 in transistor design are the same, the current through the emitter branch of the transistor 5 flows, be equal to the current that flows through the diode 4. Therefore, since the collector and Emitter currents of the tranistor 5 are essentially the same, such a collector current actually (I_ - i + i T-

κ) 1 p

Assuming that the forward voltage drop (voltage drops in the forward direction) across the diodes _{1, 2 and 4 V R} "., V" and V__. and with a base-emitter voltage drop of transistor 3 of V """results in:

^V BE1 ^{+ V} BE2 = ^V BE3

However, the relationship between voltage and current for a PN junction of a semiconductor device results as follows:

V - ^ In -i- '(2)

with I = reverse saturation current,

s - ■

q = electron charge,

k = B.oltzmann constant,

T = absolute temperature.

By combining equations (1) and (2) and the mentioned current values for diodes 1, 2 and 4 and transistor 3 »

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- Ik -

if the signal current i is not zero, the result is:

kT, ¹ O ¹ O, kTr ^(l Q- ⁱ l ⁾ , ^ Q- ¹ I- ¹ V ₁

- ( m - + in ^ -) = - [i ⁿ ^ j ~ ^{+ ln} Τ J "'·

Simplifying equation (3) gives:

^[ 0 ^{+ 1} S - / * V

With L lyi, equation (5) is simplified to:

X ₁ = ^ s_ (6).

This means that the collector current of transistor 3 (I _Q

- (i / 2)), and that the collector current of transistor 5 (Iq +

(i / 2)). It can therefore be seen that a differential Output current from the collector currents of the transistors 3 and 5 can be derived. However, if the condition I p ^ i

υ s

is not satisfied, the currents generated at the collectors of transistors 3 and 5 are distorted, so that no differential Output current can be derived precisely from such currents. In such a case, the constant current can also be used I_ cannot be effectively increased so that it meets the above condition I ^ i.

KJ S

FIG. 2 shows a previously proposed signal converter circuit (P29 4l 32I.9) ^for overcoming the difficulties explained which occur in the circuit according to FIG. The circuit of FIG. 2 is relatively simple in construction, does not produce any distortion in the differential output currents, and can be used with a low voltage source. In such a circuit, a current source 8 generates a constant current 21. A series connection of two diodes 6 and 7, the

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both are switched in the forward direction, is connected between the current source 8 and ground, and another Series connection of a diode 10 in the forward direction and the collector-emitter path of an NPN transistor 9 is connected in parallel to the first series connection or to the first current path between the current source 8 and ground. Additionally the connection point between the diodes 6 and 7 is supplied with a signal current i from a signal current source 11

and is also connected to the base of transistor 9. This connection point is also to the base of a second NPN transistor 12 connected, the emitter of which is connected to ground, the collector of transistor 9 to the base of a third NPN transistor 13 is connected, the emitter of which is also connected to ground. It should be mentioned, however, that the diodes 6, 7 and 10 are preferably formed from NPN transistors whose bases are connected to the respective collectors as shown in FIG. To this Way, the diodes 6, 7 and 10 and the transistors 9j 12 and 13 as an integrated circuit on a common semiconductor plate be formed, for example, the emitter areas of each of the elements are the same.

Theoretically, when the signal current i is equal to zero, a current I «flows through both the diode 6 and the diode 10 from the constant current source 8. When the signal current i is not equal to zero, differential output currents (I _Q + (i / 2 )) and (I - (i / 2)) are generated as the collector currents for transistor 12 and transistor I3, respectively. With such an arrangement, the collector currents of the transistors 12 and 13 are not distorted, even if the condition I _Q ^ i is not met. Furthermore, unlike other conventional differential amplifier circuits, the circuit according to FIG. 1 does not require a bias circuit, so that the circuit is very much simplified in construction and also effectively uses the voltage from a voltage source for the transistors 12 and I3, so that only a (comparatively) low voltage source

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(not shown) is required. In addition, several output transistors can have their bases in common with those of transistors 12 and 13 are connected to be used to achieve multiple differential output signals without reducing the signal current i.

As already explained, the diodes 6, 7 and 10 are preferably formed by transistors, the bases of which correspond to the respective Collectors are connected as shown in FIG. Consequently have the base currents passing through such Transistor design diodes 6,7,10 and transistor 9 flow, an effect on the value of the differential currents, generated at the collectors of transistors 12 and 13 will. For example, although the same current I “is theoretical in the same way flows through the diodes 6 and 10, if the signal current i is equal to zero, actually the current, which flows through diodes 6 and 10, differently as a result of the base currents flowing through diodes 6,7 and 10 and through the transistor 9 flow. This results further from the following investigation with reference to FIG.

As shown, there each of the diodes 6, 7 and 10 is formed from a transistor, the collector and base of which are connected to one another, as has been explained above. It is initially assumed that the current flowing through the diode 7 and in particular its emitter branch is equal to I ". Assuming that all transistors have the same structure, the base-emitter voltage V _ of the diode 7 is equal to the base-emitter voltage V _R " _{q of} the transistor 9 and therefore the current through the emitter branch of the transistor is also I _n It should be mentioned that the base currents for the diodes 6, 7 and 10 and the transistor 9 are small compared to their collector and emitter currents and can therefore be assumed to be _{I x for practical purposes.} Therefore, the collector currents of the diode 7 and the transistor 9 are the same (! _-! "), There

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the collector current of a transistor is equal to the sum of its base and emitter currents - The current flowing through the emitter branch of the diode 6 is therefore (I "+ I _D ) and the current flowing through the emitter branch of the diode 10 is (I" - I _R ) . Therefore, the current flowing through the series connection of the diodes 6 and 7 from the current source 8 is equal to (I "+ I _R ) and the current flowing to the series connection of the diode 10 and the transistor is equal (I ₀ - I ß), _{see above} that an offset current

of 2I_ between those flowing through diodes 6 and 10 JbS

Streams is generated. It should therefore be noted that the currents generated in the collectors of transistors 12 and 13 have an undesirable offset current which is a function of the base current of the diodes 6, 7 and 10 and the transistor 9 is.

FIG. K shows a further development of the proposed circuit according to FIG. 2, in which transistors 15 and 16 form a differential amplifier and correspond to transistors 12 and 13 according to FIG. A constant current source 17 which generates a constant current 2I ^ is connected in common between the emitters of transistors 15 and 16 and ground, and a bias voltage source 14 is connected between the commonly connected emitters of diode 7 and transistor 9 and ground. This latter bias voltage source 14 ensures the operation of the constant current source 17 for the differential amplifier comprising the transistors 15 and 16. With this arrangement, the differential current flows through the diodes 6 and 7 are applied to the bases of the transistors 15 and 16, respectively. However, as explained with reference to FIG. 2, an offset current which is a function of the base current of the diodes 6, 7 and 10 and of the transistor 9 is generated at the collectors of the transistors 15 and 16. If the signal current i is equal to zero, the theoretical collector currents on transistors 15 and 16 should be equal to I ₁ . However, because of such an offset current A1, the currents at the collectors of the transistors 15 and 16 are shifted by such an offset current.

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Specifically, as shown in Fig. H , as a result of such an offset current AI, the current flow through the collector of the transistor 15 is (I. - Δ I) and the current flow through the collector of the transistor 16 is (I ₁ + Al ).

If the base-emitter voltages of diodes 6 and 10 and transistors 15 and 16 are V _ßE6 , V ^ ₀ , ^ ₁₅ or V _ßEl6 , the following equation results:

^V BE6 ^{+ V} BE15 ^{= V} BE1O ^{+ V} BEl6 ⁽⁷⁾ *

By combining equation (7) with equation (2) and substituting the current values through diodes 6 and 10 and the Transistors I5 and l6 at i = 0 results in:

^{q 1} S ¹ S q ¹ S ¹ S

The following equations result from equation (8):

(I ₀ + i _B ) (I ₁ - Δι) = (I ₀ - ig) (I ₁ + Δΐ) (9)

¹ R · ¹ I.

ΔΙ = -Λ = (10).

It can therefore be seen that the offset current AI is a function of the base current I _n through the diodes 6 and 10 and such an offset current Δ I is generated in the differential output direct currents at the collectors of the transistors 15 and 16. Such an offset current ΔI is of course undesirable. Further, as will be explained with reference to the embodiments of the invention, the gain of the signal converter circuit can be controlled by changing the values of I. and I. In the circuit according to FIG. 4, however, such a change in the gain factor also changes the value of the offset current ΔI.

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An exemplary embodiment of a signal converter circuit according to the invention is explained below with reference to FIG. 5, elements which correspond to those which have been explained with reference to the previously presented circuits according to FIGS. 2-k have the same reference symbols. As shown, a first series circuit of the diodes 6 and 7 and the collector-emitter path of a transistor 18 is connected between the current source 8, which generates a constant current of 21, and ground. In particular, the emitter of transistor 18 is connected to ground, the collector of transistor 18 is connected to the cathode of diode 7, the anode of diode 7 is connected to the cathode of diode 6 and the anode of diode 6 is connected to constant current source 8 , which in turn is connected to a voltage source + Vcc. A second series circuit comprising the diode 10, the collector-emitter path of the NPN transistor 9 and a diode 19 is connected in parallel to the first series circuit between the constant current source 8 and ground. In this second series connection, the anode of the diode 10 is connected to the constant current source 8, its cathode is connected to the collector of the transistor 9, the emitter of the transistor 9 is connected to the anode of the diode 19 and the cathode of the diode 19 is connected to ground . Furthermore, the connection point between the diodes 6 and 7 is connected to the base of the transistor 9. This connection point is also supplied with a signal current i and is in particular provided with a voltage source 21 which supplies a signal voltage v. generated, connected via a capacitor 20 and a resistor R. The signal voltage v. is converted into a signal stream i

i s

by the resistance R ^ and the input impedance Z. of the circuit, seen from the voltage source 21, implemented. Further the connection point between the transistor 9 and the diode 19 is connected to the base of the transistor l8. the The circuit of FIG. 5 further includes a differential amplifier from two NPN transistors 15 and l6, which are identical Way as the identically labeled transistors according to FIG.

130014/1274

3034938

are closed. In particular, their emitters are connected to ground via a constant current source 17, which has a constant generated current 21., the collector of transistor 15 is direct connected to the voltage source + V and is the collector gate of the transistor 16 through a load resistor R with the

Lt

Voltage source + V connected, creating an output terminal

c c

22 from the collector of transistor 16 generates a differential output signal. In addition, the base of the transistor 15 to the connection point between the diodes 6 and 7 is connected and the base of the transistor is l6 connected to the collector of the transistor 9, as has been previously explained with reference to the circuit of FIG. K. It turns out that the constant current source 17 can be operated without the provision of a special bias voltage source, as is required in the circuit according to FIG. 4, as a result of the voltage drop which occurs at the junction of the diodes 6 and 7 due to the base-emitter voltage drops (V + is generated via the transistor 9 and the diode I9. It can also be seen that, as in the aforementioned proposed circuits, the diodes 6,7,10 and I9 are preferably formed from transistors whose bases are connected to the respective collectors , whereby the diodes 6, 7, 10 and 19 and the transistors 9 ₅ 15 16 and 18 can be formed as an integrated circuit on a common semiconductor plate, their emitters preferably being selected to have the same areas.

With reference to FIG. 7, it is first shown that the base currents through the transistors of the diodes 6, 7, 10 and I9 and through the transistors 9 and 18 are essentially equal to a current value I _R. The above assumption is based on the fact that all the transistors used have the same current amplification factor h_, and that the value of the current amplification factor h is very much greater than one. Feiter the following investigation is based on the fact that for each tran-

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sistör the collector current I "= h" · Ι _π and the emitter

C re B

current I "= (1 + h") I ", where I _{n is} the base current for each transistor.

From Fig. 7 it can be seen that the emitter of the diode 10 is direct is connected to the collector of the transistor 9, so that the emitter current of the diode 10 is equal to the collector current of the Transistor 9 is, according to:

¹ BlO = ^h fe ¹ B ₉

It turns out, however, that the value of h is very much greater than one, so that the emitter current of the transistor 10 can be set approximately to h "- I _-1 . For one

I © Jj XlJ

Such a case results in Id _{1 o} ** = """RQ * ^ * ^a further the base-emitter voltage drops across the transistors 18 and 19 are the same, the emitter current of the transistor l8 is the same as that of the diode I ₉ , according to:

⁽¹ + ¹ W ¹ Bl ₉ ^{= (1 + h} fe ⁾
From equation (12) it follows that I _R1 o

When the currents at the connection points between the emitter of transistor 9 and the base of transistor 18 are added, the following equation results:

¹ Bl ₉ ^{+ 1} BlS = ^{(1 + h} fe ^{} 1} B ₉

By inserting equation (12) into equation (I3) and transforming it, the relationship between I " _q and according to:

(2 + h)

¹ B ₉ ⁼ TT-ThTT

Since h is much larger than 2, it follows from the equation

x G (Ik) that I _R1 Q * = I _RQ . The collector current of the tran-

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_ ₂₂ _ 3034839

sistor 18 is equal to the emitter current of diode 7, so that:

(i ₊ h _fe ) i _B7 = _hfe i _Bl8 (15).

Since h is much larger than 1, I__ * = * Ig-iQ * = * - "- rq * If the currents at the connection point between the emitter of diode 6, the collector of diode 7 and the base of transistor 9 are added it follows that the base currents I _n "and I_ _n for the diode 7 and the transistor 9 einö / B9

cancel other out so that the following equation results:

^{+ h} fe ^{) 1} BG = ^h fe ¹ B ₇

Therefore, since h is much greater than 1, Ig / - ^ - "- 37 * It follows that the base currents of all transistors used for diodes 6, 7, 10 and I9 and transistors 9 and 18 are used are essentially equal to I _ß .

When the signal current i is equal to zero, the currents flowing from the current source 8 to the diodes 6 and 10 are both equal to I n. That is, the base currents through the diodes 6, 7, 10 and 19 and the transistors 9 and 18 have no effect on the current supplied to the diodes 6 and 10, as is the case with the proposed circuits according to FIGS was the case. This can easily be explained using the same investigation as in FIG. 3, in which it is assumed that the current through the emitter branch of transistor 18 is equal to I ₀ . Thus, it is found that the differential output currents produced by the transducer circuit of Figure 5 do not have any offset current which is a function of the base current of the transistors used in the circuit.

6 it is now shown that differential currents (I ₀ - (i _g / 2)) and (I ₀ + (i _g / 2)) through the diodes 6 and 10, respectively

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flow when the signal current i is not equal to zero,

these currents are not influenced by the base currents through the transistors of the circuit. The signal stream As explained above, i is determined by the input voltage v.

| S 3.

generated by the source 21, which in the signal stream i through

the resistance R and an input impedance Z. viewed from the signal source and seen in the circuit according to FIG. 5, is implemented. Such a signal stream i is given to the connec-

connection point between the diodes 6 and 7 supplied.

Assuming that the signal current i is fed from a signal current source 11 to the connection point of the diodes 6 and 7 (Fig. 6), the addition of such a current at the connection point results in that the constant current I _n flowing through the diode 6 becomes (I - i.) is reduced. Furthermore, as a result of such a signal current, the base current of the transistor 9 is increased to (I "+ ig). The current flowing through the diode 7 can be calculated from these current values as (I "- i. + I Io - i). Since the base current of the transistors is the same, that which flows through the base of the transistor 18 is obtained

Current to I_ + i_. For the bipolar junction transistor 18, Jd is Jd

the emitter current equals the base current plus the collector current. Consequently, since the collector current of the transistor is equal to the current flowing through the diode 7, the emitter current flowing through the transistor 18 is equal to (I _n - I ₁ + i). The same current must therefore flow through the diode 19 because the base-emitter path of the transistor 18 is parallel to the diode 19. This results in the emitter current of the transistor

9 arithmetically to (I "- i. + I + I_ + χ _π ) by adding the

UIsBB

Currents at the connection point between the emitter of the transistor 9 and the base of the transistor 18. This means that the collector current of transistor 9 is equal to (I _n - i. + I)

OX S

is. However, the total current through the diodes 6 and

10 flows, be equal to the current 2I _n that is supplied, so that the following relationship applies:

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- 2k -

(I ₀ - I ₁ ) ₊ (I ₀ - X _{1 +} i _s ) = 2I ₀ (I ₇ ).

It follows from equation (I7) that I ₁ = 1/2.

J- S

Consequently, the differential currents flowing through diodes 6 and 10 are (I _n - (i / 2)) and (I + (i / 2)), respectively, such differential currents not being influenced by undesired base currents caused by the transistors in the circuit according to FIG. 5 flow, as is the case with the proposed circuits according to FIGS. 2 and k .

It should be noted that if the differential currents fed to the bases of transistors I5 and I6 of the next stage are, the emitter current of the transistor 9 and the current flowing through the diode 7 through such base currents are influenced so that they differ slightly from the currents shown in FIG. However, the differential Output currents that appear at the collectors of transistors I5 and 16 are not affected to any great extent, if at all, by such minor changes in currents through the diode 7 and the emitter of the transistor 9-

It can also be seen that the diode 7 hex of the circuit according to FIG. 5 can be omitted and the resulting circuit operates essentially identically to the circuit according to FIG. In such a case, the potential at the base of transistor 9 is equal to the potential at its collector, but the potential at the base of transistor 18 is different from that at its collector, the latter difference being the base-emitter voltage drop across the transistor 9 corresponds. In such a case, the transistors 9 and 18 do not operate under the same conditions as in the circuit of FIG. 5> although the current relationships of FIG are the same as in the circuit according to Fig. 5-

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According to FIG. 5, the following equation results: ^V BE6 ^{+ V} BE15 * ^V BE10 ^{+ V} BE16

^(I o - J. ,
2 ¹ S ' kT ( • ι S. * x> S. 1 1 . I. . , O ⁺ 2 ^X £ kT {
In - ¹ X I.
S. q ^{: i} i ⁺ I. I.
S.

where V _R _, -, V ",? and V., - correspond to the base-emitter voltage drops across diodes 6 and 10 and transistors 15 and 16, respectively. Assuming that the collector currents of the transistors 15 and 16 change to (I ₁ + i) and (I ₁ - i), respectively, as a result of the generation of the signal current

■ i- be.

i gives the combination of equations (2) and (18)

following equation:
kT

kT _Ί

_ln

Equation (19) can be simplified to:

^(I 0 - I ¹ S) ^(I 1 ^{+ 1} ^ = ^(I O ⁺ 1 ¹ Si ^(I 1 - ^± _x ^{) (20)}

¹ X = II ₀ * b ⁽²¹⁾

From the above it follows that the differential output currents, which are generated at the collectors of transistors 15 and 16, only from the constant currents I_ and I. and the signal current i depend and do not depend on the base currents of the transistors of the signal converter circuit according to FIG .

As a result, there may be a voltage change v_ in the output signal voltage are detected at the output terminal 22, which results to:

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The input impedance Z. when looking into the signal converter circuit from the resistor R ₁ results according to:

kT 1 ¹ S _ kT 1

^{q Is} ° ⁺ 1 ¹ S ^{q 2 (} ν 1 ν

If I _n is much larger than i, the expression for Z. can be simplified according to:

Accordingly, the following simplified expressions can be used for the Signal current i and the output voltage V are obtained:

v.
¹ (25)

R. 1
1 ⁺ 2 r
e ^v o ^{= R} L 2 (R ₁ + ^r e) P,

τ ^ v. (26)

¹ O ^X

From equations (25) and (26) it follows that the gain factor control- for the circuit according to FIG. 5 by changing either one or bezud constant current values I and I can be done.

As a result, the signal converter circuit shown in FIG. 5 generates differential output currents which do not have any Contain offset current which is a function of the base currents of the transistors used therein. Next generated the circuit according to FIG. 5 differential output currents, which contain essentially no distortion. In addition, it can be seen that there is no bias voltage source in the Signal converter circuit according to Fig. 5 is required because this circuit does not convert a signal voltage into a signal stream implemented like the conventional signal converter circuits with differential amplifier construction. Therefore the circuit has

1300U / 127A

measured the invention relatively simple structure, with their Gain control can be satisfactorily performed by means of a low voltage source + Vcc can. Furthermore, since the input signal used in the invention is only processed as a stream, the dynamic range of the circuit can be made larger and its frequency characteristic can be improved will. It can also be seen from equation (26) that the effect of the input impedance on the gain of the Circuit according to the invention can be reduced, thereby reducing the gain of the circuit in simpler Way can be controlled.

Fig. 8 shows a signal converting circuit according to another Embodiment of the invention, wherein elements which correspond to those of the circuit according to FIG. 5 are denoted by the same reference numerals. In the circuit according to FIG an NPN transistor 25 is connected on the base side to the connection point between the diodes 6 and 7 and on the emitter side connected to ground via a constant current source 23, the one Constant current I "generated. A second NPN Trans! Sturgeon 27 is on the base side connected to the emitter of transistor 25, its collector-emitter path in series with the collector-emitter path of an NPN transistor 30 between the voltage source + Vcc and ground is connected. the The base of the transistor 30 is connected to a bias voltage source 29 connected, which generates a predetermined voltage, the collector of the transistor 27 to the base of the transistor 15 is connected instead of the base of the transistor 15 connected to the connection point between diodes 6 and 7 is the same as in the circuit according to FIG. 5 · In Way, an identical circuit is used with transistor l6. In particular, an NPN transistor 26 is on the base side connected to the connection point between the transistor 9 and the diode 10, which is why the other differential

1300U / 1274

Electricity is supplied there. The emitter of transistor 26 is connected to ground via a constant current source 2k which generates the same constant current I_. The collector-emitter path of a further NPN transistor 28 is connected in series with the collector-emitter path of a transistor 31 between the voltage source + Vcc and ground and is connected on the base to the emitter of the transistor 26. The base of the transistor 3I is also supplied with the predetermined voltage from the bias voltage source 29, the collector of the transistor 28 being connected to the base of the transistor 16 for driving it. The remaining components of the circuit according to FIG. 8 are identical to those of the circuit according to FIG. 5 and are therefore not explained again.

It is assumed that the differential currents which are generated at the collectors of transistors 27 and 28, I.

and I _o , respectively, and that the base-emitter voltages of the transistors 2 ₅ , 26,2 ₇ and 28 V ^^ V ^ ₆ , V ^ ₃₇ and T ^ ₈ , respectively, where the following equation can be derived:

^V BE6 ^{+ V} BE25 ^{+ V} BE27 = ^V BE1O ^{+ V} BE26 ^{+ V} BE28 ⁽²⁷⁾ *

By substituting the above mentioned current values and combining equations (2) and (28), equation (28) can be converted into exactly same way as equation (18) to equation (20) can be simplified as follows:

^(I 0 - I ¹ S) V ¹ Xl = ^(I 0 ⁺ Ι ⁱ s ^{) X} 2 ■ ¹ X ₂ ⁽²⁸⁾ ·

By further simplifying equation (28), the respective values for I ₁ and I _{2 result} as follows:

1300U / 1274

It therefore follows from equations (29) and (30) j that the collector currents of transistors 27 and 28 of the circuit according to FIG. 8 are the differential currents, which are fed to the differential amplifier, which consists of the transistors I5 and I6. Therefore, an output voltage v_ obtained from output terminal 22 in the same manner as explained with reference to the circuit according to FIG. 5 has been.

Fig. 9 shows a signal converting circuit according to another Embodiment of the invention, elements which correspond to those which have been explained with reference to FIG. 5 have the same reference numerals. In this embodiment, the emitter of transistor l8 and the cathode of diode I9 connected together at a common junction, being a bias source 32 between this common connection point and ground connected. The circuit of FIG. 9 further includes a constant current source composed of an NPN transistor 33> the collector side with the emitters of the transistors I5 and l6 is connected, the emitter side via a resistor

is

3 * t connected to ground and the basissei tig connected to ground via a first series connection of a diode 35 and a resistor 36 and a second series connection in parallel with the first series connection of a resistor and a voltage source. Resistors 3 ^ and 36 are used to maintain a suitable current balancing relationship between transistor 33 and diode 3 ^. It can be seen that the use of the bias voltage source 32 enables the aforementioned current source of FIG. 9 to be used with the differential amplifier composed of the transistors 15 and 16. A further development of the circuit according to FIG. 9 can use a resistor with a relatively high resistance value in parallel with the first and second

the second series connection between the base of the transistor

1300U / 1274

33 and be mass. It can also be seen that the circuits of FIGS. 8 and 9 produce the same results as the circuit Reach according to FIG. 5, so that the differential output currents do not contain any offset current, which is a function of the base currents of the transistors used in the circuits are used.

Of course, other embodiments are also possible.

1300U / 1274

Claims (1)

Expectations; Signal converter circuit, with a current source for generating a constant current, an input signal generator means for generating an input signal stream, a first device for generating a first differential current as a function of the constant current and the input signal current, second means for generating a second differential current as a function of the constant current and the input signal stream, wherein at least one of the first and second devices is a semiconductor device having an input which is supplied with a current at the input, and an output device for generating differential output signals as a function of the first and second differential currents,
marked by a removal device (18,19) for removing the Effect on the differential output signals of the current at the input of the semiconductor device (6,7,9,10). 1300U / 1274 2. Signal converter circuit according to claim 1, characterized in that the removal device a second semiconductor device which is connected between the first and the second device and a reference potential. 3- signal converter circuit according to claim 2, characterized in that that the second semiconductor device has a first transistor (18) between the first device (6,7) and the reference potential and a first diode (19) between the second device (9 ₅ 10) and the reference potential. 4. Signal converter circuit according to claim 3> characterized, that the first transistor (18) is a bipolar NPN junction transistor is connected to the emitter side to the reference potential and the collector side to the first device (6,7) is, and that the first diode (19) on the cathode side with the reference potential and on the anode side with the second Device (9,10) and the base of the first transistor (l8) is connected. 5- signal converter circuit according to claim 4, characterized in that that the first device has a second diode (6) which is connected on the anode side to the current source (8) and on the cathode side with the input signal generator device (20, 21, R.) and the collector of the first transistor (18) is connected, and that the second device is a third diode (10) has, which is connected on the anode side to the current source (8), and a second transistor (9) j the collector side with the cathode of the third diode (10), on the emitter side with the base of the first transistor (18) and the The anode of the first diode (19) and the base side with the cathode 130014/1274 the second diode (6), the collector of the first transistor (18) and the input signal generator device (20, 21, R) is connected. 6. Signal converter circuit according to claim 5j characterized, that each of the first, second and third diodes is formed by a bipolar NPN junction transistor, the base of which is connected to the respective collector. 7. Signal converter circuit according to one of claims 1-6, characterized in that that the output device is a differential amplifier with a first and a second transistor (15, 16), the first transistor (15) having the input side the first device (6,7) and the second transistor (16) connected on the input side to the second device (9 »10) are. 8. signal converter circuit according to claim 7, characterized, that the first and the second transistor (15, 16) are bipolar NPN junction transistors, and that the differential amplifier further comprises a second constant current source (17) connected between the emitters of the first and second Transistor (15,16) and a reference potential is connected. 9. Signal converter circuit according to claim 7 j characterized, that the differential amplifier further includes a second constant current source for biasing the first and second transistors, and that a bias source (32) is connected to the removal device (18,19). 10. Signal converter circuit according to claim 9j characterized, 130 & U / 1274 3034933 that the second constant current source contains a transistor (33), the collector side with the first and the second The transistor (15, 16) is connected on the emitter side to a reference potential and on the base side to a second bias voltage source. 11. Signal converter circuit according to one of claims 1-10, characterized, that the first device (6,7) and the second device (9,10) between the power source (8) and the removal device (18,19) are connected, and that both the first device (6,7) and the second device (9) 10) are further supplied with the input signal stream for generating the first and the second differential Current. 12. Signal converter circuit according to claim 11, characterized, that the first device has a first diode device (6,7) which is connected to the current source (8) and the input signal generator device (20,21, R.) for generating the first differential current, and that the second device is a series circuit comprises a first transistor device (9) and a second diode device (10), the series circuit being connected to the current source (8) and the input signal _{generator device (20, 21, R 1} ) for generating the second differential current. 13. Signal converter circuit according to claim 12, characterized, that the first diode device contains a first diode (6) which is connected on the anode side to the current source (8) and on the cathode side is connected to the input signal generator device (20, 21, R.) and the removal device (18, 19), that the second diode device is a second diode (10) 130014/1274 has, which is connected on the anode side to the current source (8), and that the transistor device is a bipolar Has NPN junction transistor (9) on the collector side with the cathode of the second diode (10), on the base side with the cathode of the first diode (6) and the input signal generator device (20, 21, R.) and the emitter side connected to the removal device (18, 19) is. Ik. Signal converter circuit according to claim 13 »characterized in that that first and second diode (6,10) by bipolar NPN junction transistors are formed with the bases of the transistors connected to the respective collectors. 15. Signal converter circuit according to claim I3 or 14, characterized, that the first diode device (6,7) has a third diode (7), the anode side with the cathode of the first Diode (6), the input signal generator device (20,21, R.) and the base of the transistor (9) and the cathode side is connected to the removal device (18, 19). 16. Signal converter circuit according to one of claims 12-15, characterized in that that the first device further comprises a second transistor device (25,27,30) which is supplied with a second constant current and has an input which is connected to the first diode means for generating a third differential current, and that the second device further comprises a third transistor device (26,28,31), which with a third constant current is supplied and has an input connected to the series circuit for generating a fourth differential current. 1300U / 1274 -G- 17 signal converter circuit according to claim 16, characterized, that the first and third differential currents are equal are, and that the second and fourth are differential Electricity are the same. 18. Signal converter circuit according to claim l6 or I7, characterized, that the second transistor device (25,27,30) one first transistor (25) having an input which is connected to the first diode device (6,7), and with an output circuit supplied with the second constant current and a second transistor (27) an input which is connected to the output circuit of the third transistor (25), and to an output circuit, which is connected to the output device (15, 16), and that the third transistor design (26,28,31) a third transistor (26) with an input which is connected to the series circuit (9,10), and an output circuit supplied with the third constant current and a fourth transistor (28) one input that connects to the output circuit of the third Transistor (26) is connected, and to an output circuit which is connected to the output device (15,16) is, has. 19 signal converter circuit according to claim l8, characterized, that the second transistor device (25,27,30) continues a fifth transistor (30) with an input that is connected to is supplied with a predetermined voltage, and with an output circuit connected in series with the output circuit of the second transistor (27) is connected between the first and second reference potential, and that the third transistor device (26,28,31) further a sixth transistor (3I) with an input which corresponds to the predetermined 1300U / 127 * Voltage is supplied, and with an output circuit in series with the output circuit of the fourth transistor (28) is connected between the first and the second reference potential, has. 20. Signal converter circuit according to claim I9, characterized, that each transistor of the second and third transistor means is a bipolar NPN junction transistor, wherein the base side of the first transistor (25) is connected to the first diode device (6,7), and to the collector side is connected to the first reference potential and on the emitter side is supplied with the second constant current, the second transistor (27) on the base side with the emitter of the first The transistor (25) is connected, the emitter side is connected to the second reference potential and the collector side is connected to the output device (15, 16), the fifth transistor (30) on the base side to the predetermined Voltage is supplied, is connected to the first reference potential on the collector side and to the emitter side Collector of the second transistor (27) is connected, the third transistor (26) on the base side with the series circuit (9) 10) is connected, on the collector side to the first reference potential is connected, and the emitter side is supplied with the third constant current, the fourth transistor (28) is connected on the base side to the emitter of the third transistor (26), is connected on the emitter side to the second reference potential and on the collector side to the output device (15,16) is connected, and the sixth transistor (31) on the base side with the predetermined voltage is supplied, is connected on the collector side to the first reference potential and on the emitter side to the collector of the fourth Transistor (28) is connected. 130014/1274