Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/36—Means for starting or stopping converters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/16—Conversion of dc power input into dc power output without intermediate conversion into ac by dynamic converters
  • H02M3/18—Conversion of dc power input into dc power output without intermediate conversion into ac by dynamic converters using capacitors or batteries which are alternately charged and discharged, e.g. charged in parallel and discharged in series
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
  • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
  • H02M3/073—Charge pumps of the Schenkel-type
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
  • H02M1/007—Plural converter units in cascade

Definitions

• This invention relates generally to charge pumps and, more specifically, to a progressive start-up charge pump that eliminates the start-up problems of p-channel charge pump stages by starting the charge pump one stage at a time.
• charge pump stages were implemented using low threshold native devices. However, the implementation of charge pump stages using low threshold devices was not adequate. The gamma of the low threshold devices was too high and at low power supply voltages, the number of stages needed for the charge pump to reach desired levels was prohibitive.
• the improved multiple stage charge pump is a progressive start-up charge pump wherein the charge pump is started one stage at a time starting with the output stage and working back towards the first stage.
• the output of each stage is guaranteed to be at a higher potential than the input to the stage. This will ensure that none of the vertical pnp devices get activated during start-up of the progressive start-up charge pump.
• a progressive start-up charge pump has a plurality of charge pump stage means for generating a desired output voltage for the progressive start-up charge pump.
• Each of the plurality of charge pump stage means are implemented using p-channel devices.
• Each of the plurality of charge pump stage means has a voltage input node and a voltage output node and are coupled together such that each of the plurality of charge pump stage means are coupled to a successive charge pump stage means in a cascade mode.
• Enabling means are coupled to each of the plurality of charge pump stage means.
• the enabling means are used for individually starting each of the plurality of charge pump stage means one charge pump stage means at a time starting with the last charge pump stage means and successively turning on a directly previous charge pump stage means until the first charge pump stage means is started.
• the enabling means are further used to ensure that the voltage output node is at a greater potential than the corresponding voltage input node for each of the plurality of charge pump stage means.
• a method of providing a progressive start-up charge pump comprises the steps of: providing a plurality of charge pump stage means for generating a desired output voltage for the progressive start-up charge pump wherein each of the plurality of charge pump stage means is implemented using p-channel devices, each of the plurality of charge pump stage means has a voltage input node and a voltage output node such that each of the plurality of charge pump stage means are coupled to a successive charge pump stage means in a cascade mode; and providing enabling means coupled to each of the plurality of charge pump stage means for individually starting each of the plurality of charge pump stage means one charge pump stage means at a time starting with a last charge pump stage means and successively turning on a directly previous charge pump stage means until the first of the plurality of charge pump stage means is started and for ensuring that the voltage output node is at a greater potential than the voltage input node for each of the plurality of charge pump stage means.
• Figure 1 is a simplified functional block diagram of the progressive start-up multiple stage charge pump of the present invention.
• Figure 2 is a simplified functional block diagram of an enabling circuit used to charge each stage of the progressive start-up multiple stage charge pump depicted in Figure 1.
• Figure 3 is an electrical schematic of an individual stage of the progressive start-up multiple stage charge pump
• charge pump 10 has a plurality of charge pump stages 12. Although only four charge pump stages 12 are shown, additional or fewer stages could be used depending on the desired output voltage required by the charge pump
• Each of the charge pump stages 12 has a voltage input 12A and a voltage output 12B.
• the charge pump stages 12 are coupled together in cascade such that the voltage output 12B is coupled to a voltage input 12A of a directly successive charge pump stage 12.
• the first charge pump stage has a voltage input coupled to a diode connect transistor 16 while the voltage output 12B of the last charge pump stage is used to output the desired output voltage level for the charge pump 10.
• Each of the charge pump stages 12 is coupled to a corresponding charge pump enable circuit 14.
• the charge pump enable circuits 14 each have a charge clock output 14C and a transfer clock output 14A.
• the charge clock output 14C and the transfer clock output 14A of each charge pump enable circuit 14 is coupled respectively to a charge clock input 12C and a transfer clock input 12D of a corresponding charge pump stage 12.
• Each charge pump enable circuit 14 also has an enable clock input 14B.
• the charge pump enable circuits 14 are all coupled together in a cascade mode such that the transfer clock output 14A of a charge pump enable circuit 14 is coupled to an enable clock input 14B of a directly previous charge pump enable circuit 1 .
• the charge pump enable circuits 14 are used to start each of the plurality of charge pump stages 12.
• the charge pump enable circuits 14 are coupled to a plurality of signal lines 18.
• the signal lines 18 are used to control each of the charge pump enable circuits 14 such that charge pump enable circuits 14 will active each of the charge pump stages 12 one stage at a time.
• Each of the charge pump stages 12 are activated individually starting with the last charge pump stage and successively turning on a directly previous charge pump stage until the first charge pump stage is started.
• the plurality of signal lines 18 includes a pump enable signal line 20.
• the pump enable signal line 20 is coupled to a pump enable input 14D of each charge pump enable circuit 14.
• the pump enable signal line 20 sends a reset signal which is used to turn off the charge pump 10.
• the plurality of signal lines 18 also includes a first charge clock line 22 and a second charge clock line 26.
• the first charge clock signal line 22 is coupled to an enable clock input 14B of the last charge pump enable circuit and to charge clock inputs 14E of the penult charge pump enable circuit and alternate charge pump enable circuits after the penult charge pump enable circuit.
• the first charge clock signal line 22 is used to send an enable clock signal to the enable clock input 14B of the last charge pump enable circuit and for raising the voltage level at the voltage input 12A of the penult charge pump stage and alternate charge pump stages after the penult charge pump stage.
• the second charge clock signal line 26 is coupled to the charge clock input 14E of the last charge pump enable circuit and alternate charge pump enable circuits after the last charge pump enable circuit.
• the second charge clock signal line 26 is used for raising the voltage level at the voltage input 12A of the last charge pump stage and alternate charge pump stages after the last charge pump stage.
• the plurality of signal lines 18 also includes a first transfer clock line 24 and a second transfer clock line 28.
• the first transfer clock signal line 24 is coupled to a transfer clock input 14E of the penult charge pump enable circuit and alternate charge pump enable circuits after the penult charge pump enable circuit.
• the first transfer clock signal line 24 is used to send a transfer clock signal to the penult charge pump enable circuit and alternate charge pump enable circuits after the penult charge pump enable circuit to allow a charge to be transfer from the voltage input 12A to a voltage output 12B of the penult charge pump stage and alternate charge pump stages after the penult charge pump stage.
• the second transfer clock signal line 28 is coupled to a transfer clock input 14E of the last charge pump enable circuit and alternate charge pump enable circuits after the last charge pump enable circuit.
• the second transfer clock signal line 28 is used to send a transfer clock signal to the last charge pump enable circuit and alternate charge pump enable circuits after the last charge pump enable circuit to allow a charge to be transfer from the voltage input 12A to a voltage output 12B of the last charge pump stage and alternate charge pump stages after the last charge pump stage.
• the charge pump enable circuit 12 has a flip flop 30 which has an enable clock input 14B and a pump enable input 14D.
• the output 32 of the flip flop is coupled to an input 36B of an AND gate 36 while the inverted output 34 of the flip flop 30 is coupled to an input 38A of an OR gate 38.
• a second input 36A of the AND gate 36 is coupled to one of the charge clock signal lines 22 or 26 depending on where the charge pump enable circuit 14 is positioned in the charge pump 10.
• a second input 38B of the OR gate 38 is coupled to one of the transfer clock signal lines 24 or 28 depending on where the charge pump enable circuit 14 is positioned in the charge pump 10.
• the charge pump stage 12 is shown in detail.
• the charge pump stage 12 is implemented using pmos devices.
• the charge pump stage 12 is a standard charge pump stage 12 which is known to those skilled in the art. Thus, the operation of the charge pump stage 12 will not be described in detail.
• the charge pump stage 12 has a first pmos transistor 40 having a gate, a drain, and a source terminal. The drain terminal is coupled to the voltage input node 12A, the source is coupled to the voltage output node 12B. A well of the first pmos transistor 40 is coupled to the source terminal and thus the voltage output node 12B.
• a second pmos transistor 42 is also provided and also has a gate, a drain, and a source terminal.
• the drain terminal of the second pmos transistor 42 is coupled to the voltage output node 12B.
• the gate of the second pmos transistor 42 is coupled to the voltage input node 12A.
• a first capacitor bank 44 is provided and is coupled to the voltage input node 12A and to the charge clock input 12C. The first capacitor bank 44 is used for storing a charge to raise the voltage level of the voltage input node 12A.
• a second capacitor bank 46 is provided and is coupled to the gate of the first pmos transistor 40. The second capacitor bank 46 is used for turning on the first pmos transistor 40 so that a charge may be transferred from the voltage input node 12A to the voltage output node 12B.
• the operation of the charge pump 10 will be described in detail .
• the pump enable signal line 20 goes low the charge pump 10 is activated and ready for a progressive start-up.
• the first charge clock signal line 22 will go high which will go to the enable clock input 14B of the last charge pump enable circuit. This will activate the clock of the flip flop 30 of the last charge pump enable circuit.
• the OR gate 38 of the last charge pump enable circuit will output a transfer clock signal which will activate the pmos transistor 40 of the last charge pump stage. This will allow the voltage at the voltage input 12A to be at the same potential as the voltage at the voltage output 12B for the last charge pump stage.
• the low transfer clock signal will also activate the clock of the flip flop 30 of the directly previous charge pump enable circuit.
• the second transfer clock signal line 28 is brought low which will turn off the first pmos transistor 40 of the last charge pump stage.
• the second charge clock signal line 26 is then brought low which will pull the voltage input 12A down but not the voltage output 12B of the last charge pump stage. Thus the voltage output 12B is raised to a predetermined voltage level .
• the same process is then repeated for the penult charge pump stage using the first charge clock signal line 22 and the first transfer clock signal line 24. After the last two charge pump stages have been activated, the second to last charge pump stage will be activated.
• the second to last charge pump stage must be activated in tandem with the last charge pump stage. This will ensure that the voltage input nodes will not be at a higher potential than the voltage output nodes for each of the charge pump stages. The entire process is continuously repeated in alternating couples until the first charge pump stage has been activated.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Dc-Dc Converters (AREA)
• Control Of Electrical Variables (AREA)
• Read Only Memory (AREA)

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• 1997
  • 1997-11-29 KR KR1019997002025A patent/KR20000068537A/ko not_active Application Discontinuation
  • 1997-11-29 EP EP97949816A patent/EP0925635A4/de not_active Withdrawn
  • 1997-11-29 WO PCT/US1997/023066 patent/WO1999003192A1/en not_active Application Discontinuation
  • 1997-11-29 JP JP11508610A patent/JP2001500300A/ja active Pending
• 1998
  • 1998-02-16 TW TW087102071A patent/TW432768B/zh not_active IP Right Cessation

Non-Patent Citations (2)

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