Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/34—DC amplifiers in which all stages are DC-coupled
  • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
  • H03F3/345—DC amplifiers in which all stages are DC-coupled with semiconductor devices only with field-effect devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H11/00—Networks using active elements
  • H03H11/02—Multiple-port networks
  • H03H11/04—Frequency selective two-port networks
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H11/00—Networks using active elements
  • H03H11/02—Multiple-port networks
  • H03H11/04—Frequency selective two-port networks
  • H03H11/0422—Frequency selective two-port networks using transconductance amplifiers, e.g. gmC filters
  • H03H11/0427—Filters using a single transconductance amplifier; Filters derived from a single transconductor filter, e.g. by element substitution, cascading, parallel connection
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/331—Sigma delta modulation being used in an amplifying circuit

Definitions

• the present invention relates to a method for continuous-time filtering in digital CMOS process and a device for continuous- time filtering in digital CMOS process .
• US-A-4 , 839, 542 there are disclosed active transconductance .filters, which belong to a filter type which is called a transconductance-capacitance (gm-C) filter.
• the basic idea is to create poles by using linear capacitors and transconductors.
• current mirrors are used as active loads for the transconductors and current mirrors are not utilized to create poles for any filtering purposes .
• the invention relates preferably to the design of continuous- time filters for sampled data systems in digital CMOS processes.
• a digital CMOS process neither resistors nor linear capacitors are available. Therefore it is not possible or simply not practical to design continuous-time filters using traditional methods.
• the pole frequency is therefore determined by the transconductance of an MOS transistor and the capacitance seen at its gate.
• a generalized method of designing continuous-time filters in digital CMOS process and methods of cascading have been proposed to reduce the spread of the pole frequencies.
• Fig. 1 " is a circuit showing a basic current mirror as a single- pole filter.
• Fig. ' 2 is a graph showing SPICE simulation results of fig. 1, wherein cascode current mirrors and cascode current sources are used and the capacitor is realized by NMOS transistors.
• Fig. 3 a and b are circuits showing cascading techniques according to the invention.
• Fig. 4 is a graph showing SPICE simulation results of fig. 3b, wherein cascode current mirrors and cascode current sources are used and the capacitors are realized by NMOS transistors.
• the capacitor C 0 1 can be realized by a gate capacitor on chip, or realized by an off-chip capacitor, if the cut-off frequency of the filter is required to be very low.
• a scaling factor can also be realized within this filter.
• the pole frequency of the single-pole filter shown in fig. 1 is given by
• g m0 is the transconductance of the diode-connected transistor M 0 2 and C p0 represents all the parasitics at the gate of transistor M 0 2.
• the nonlinearities in the transconductances do not introduce distortion in the output current as long as the transconductances of M 0 2 and M x 3 are matched or constantly rationed.
• nonlinearities in the capacitance can introduce error in the output current .
• the gate capacitance is highly nonlinear across the whole operation region, in a current mirror configuration as shown in fig. 1, the gate voltage change is quite limited, making the transistors operate in a well specified region all the time. Therefore, the gate capacitance does not vary dramatically and the linearity is acceptable. When external capacitors are used, linearity can also be guaranteed.
• the transconductance of a transistor is dependent of the drain current, i.e.,
• ⁇ n is the channel charge mobility
• C ox is the unit gate capacitance
• W/L is the transistor size
• i D is the drain current. Therefore, when the drain current in transistor M 0 2 changes accommodating input current I 0 , the transconductance g ra0 changes, making the pole frequency change.
• the SPICE simulation results when the input current changes between ⁇ 0 , 5 I bias0 .
• circuit of fig. 1 is a single-pole system, having 20 dB/dec frequency roll-off. And the change in the 3-dB frequency is well in line with the prediction given by the equation of transconductance. The change in the pole frequency also introduces distortion, when the input signal frequency approaches the cut-off frequency, in that a different input amplitude experiences a different attenuation.
• the simulated total harmonic distortion is about -50 dB, when the input is a 100 Khz sinusoidal with amplitude equal to one- fourth of the bias current. When the input frequency decreases to 10 Khz, the total harmonic distortion is less than -70 dB . When the input frequency is larger than the cut-off frequency, the total harmonic distortion is attenuated by the filter itself .
• the change in the drain current is needed to be as small as possible.
• One way to do so is to limit the input current compared with the bias current. This is very power consuming.
• proper cascading realizing higher-order filters can reduce the variation in the pole frequencies.
• cascading of current mirrors can be used.
• a single- pole system only gives a 20-dB/dec roll-off. In many applications, sharper cut-off is needed.
• Cascading two single- pole systems realizes a two-pole system having a 40-dB/dec roll- off. Sharper cut-off can be realized by cascading more stages. There are two possibilities of cascading as shown in fig. 3a and b.
• the use of cascading shown in fig. 3a results in lower power consumption due to the use of the p-type branch.
• the n-type branch "1" consists of n-type transistors M0 6 and Ml 7, capacitor C 0 8 and bias current IbiasO 9 for transistor M0 6.
• the p-type branch "2" consists of p-type transistors M2 10 and M3 11 capacitor C 1 12 and bias current Ibiasl 13 for M3 11.
• the n-type branch is similar to the one shown in fig. 1 except that the bias current for Ml 7 is omitted due to the use of the p- type branch.
• Transistors Ml 7 and M2 10 bias each other.
• the p- type branch is the same as the n-type except p-type transistors are used.
• this kind of cascading influences the pole frequencies.
• input current I 0 is positive
• the drain current in M 0 6 increases making its transconductance to increase. Therefore, the pole frequency determined by the transconductance of M 0 6 and capacitor C 0 8 will increase.
• the drain current in M 2 10 equal to the drain current of M 7, increases as well making its transconductance to increase. Therefore, the pole frequency determined by the transconductance of M 2 10 and the capacitance of C ⁇ 12 will increase as well .
• the combined effect is that the pole frequencies vary more rapidly as the input current varies.
• the cascading technique shown in fig. 3 b results in more power consumption due to an extra n-type branch. It consists of two n- type branches "1" and "2" , which are exactly the same as the one shown in fig. 1.
• it has a big advantage stabilizing the pole frequencies.
• input current I 0 is positive
• the drain current in M0 6 increases making its transconductance increase. Therefore, the pole frequency determined by g m0 /C 0 will increase.
• the drain current in M 2 10 decreases making its transconductance decrease. Therefore, the pole frequency determined by will decrease.
• the combined effect is that the variations in the two pole frequencies tend to reduce the total variation.
• the circuit of fig. 3b is a two-pole system, having 40-dB/dec frequency roll-off. And the change in the variation in the 3-dB frequency is reduced considerably.
• the simulated total harmonic distortion is less than - 60 dB, when the input is a 100 Khz sinusoidal with amplitude equal to one-fourth of the bias current.
• the total harmonic distortion is less than -80 dB.
• the total harmonic distortion is attenuated by the filter itself.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Networks Using Active Elements (AREA)
• Amplifiers (AREA)

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• 1996
  • 1996-07-19 SE SE9602824A patent/SE508697C2/sv not_active IP Right Cessation
• 1997
  • 1997-06-16 TW TW086108310A patent/TW349264B/zh not_active IP Right Cessation
  • 1997-06-27 CA CA002260915A patent/CA2260915A1/en not_active Abandoned
  • 1997-06-27 AU AU35637/97A patent/AU3563797A/en not_active Abandoned
  • 1997-06-27 KR KR1019980710778A patent/KR20000065251A/ko not_active Application Discontinuation
  • 1997-06-27 WO PCT/SE1997/001169 patent/WO1998004038A1/en not_active Application Discontinuation
  • 1997-06-27 CN CN97196552A patent/CN1108658C/zh not_active Expired - Fee Related
  • 1997-06-27 EP EP97932096A patent/EP0913029A1/en not_active Withdrawn
  • 1997-06-27 JP JP10506853A patent/JP2000514980A/ja active Pending
• 2000
  • 2000-01-22 HK HK00100431A patent/HK1021595A1/xx not_active IP Right Cessation

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