EP0868837A1 - Nouveau procede de formation de fines lignes de circuit - Google Patents

Nouveau procede de formation de fines lignes de circuit

Info

Publication number
EP0868837A1
EP0868837A1 EP97924540A EP97924540A EP0868837A1 EP 0868837 A1 EP0868837 A1 EP 0868837A1 EP 97924540 A EP97924540 A EP 97924540A EP 97924540 A EP97924540 A EP 97924540A EP 0868837 A1 EP0868837 A1 EP 0868837A1
Authority
EP
European Patent Office
Prior art keywords
copper foil
copper
substrate
circuit lines
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97924540A
Other languages
German (de)
English (en)
Inventor
John F. Fatcheric
Derek C. Carbin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
AlliedSignal Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AlliedSignal Inc filed Critical AlliedSignal Inc
Publication of EP0868837A1 publication Critical patent/EP0868837A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0307—Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0726—Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Definitions

  • This invention relates generally to methods for producing printed circuit boards. In particular, it relates to a new method of forming very fine circuit lines.
  • thin copper foil is laminated to an insulating substrate, most often a glass reinforced epoxy resin prepreg, and then that laminate is further processed to convert the copper foil into a circuit pattern by selectively removing portions ofthe copper by chemical etching.
  • etching is generally satisfactory, but its limitations become apparent whenever finer (narrower) circuit lines are required.
  • the copper foil may be treated prior to lamination in order to enhance its ability to bond to the insulating substrate.
  • references herein to copper foil shall be construed as referring interchangeably to both treated and untreated copper foil.
  • the etchants do not create vertical sides of the circuit lines. Instead, they tend to etch away too much copper at the top of the line by undercutting the resist and less at the bottom ofthe line, leaving a somewhat rapezoidal-shaped circuit line. As a result, the minimum width of the circuit lines is limited by the need to allow for such non-uniform etching.
  • This problem was discussed in US 5,437,914 and it was shown that the shape of the etched circuit lines was affected by the shape ofthe grain structure of the copper foil. Improved accuracy of etching was to be obtained according to the '914 patent by laminating the copper foil to the substrate with the "shiny" side down, which is contrary to the conventional practice. An improved etching factor was obtained, indicating that the sides ofthe circuit lines were more nearly vertical.
  • the present invention solves the etching problem in a completely different manner. No etching away ofthe copper foil is used in creating the circuit lines, but instead the circuit lines are electrodeposited onto very thin conductive layers within trenches defined by a resist.
  • the method is particularly advantageous when used to make the outer circuit layers of multilayer circuit boards, but also may be used for inner layers or one- and two-sided circuit boards.
  • the invention is a new method of forming very narrow circuit lines on a non-conductive substrate by applying copper over a thin conductive layer in regions defined by a cured photo resist. This is made possible by applying a thin layer of a conductive metal, metals, or alloys to the non- conductive substrate.
  • the conductive metal, metals, or alloys are applied to a sheet of copper foil and then the copper foil is laminated to a substrate, with the conductive metal layer between the copper and the substrate. If the copper foil is treated to enhance its ability to bond to the substrate, the conductive metals may be applied to the copper foil either before or after such treatment.
  • the copper foil is etched away, leaving the thin conductive metals in place.
  • a photoresist is then applied, imaged, and cured.
  • the uncured resist is removed, thus defining the region or "trench" in which the circuit lines are wanted. Since the conductive layer is now exposed, it is possible to selectively apply the circuit lines in those regions.
  • the cured photoresist is removed and the conductive metal layer which has been exposed is removed by chemical etching, leaving the finished circuit.
  • the copper foil and conductive metals may be applied to the respective surfaces by any conventional method including, but not limited to, electrolytic deposition, chemical vapor deposition, electroless deposition and sputtering.
  • electroless copper plating is used to cover the conductive metal layer before electrodepositing the circuit lines.
  • Figure 1 is a block diagram ofthe process ofthe invention applied to multi ⁇ layer circuit boards.
  • Figure 2 is a block diagram of the prior art process for multi-layer circuit boards.
  • Figure 3 illustrates cross-sectional view of conventional circuit lines compared with those ofthe invention in multi-layer circuit boards.
  • the invention comprises a new process of forming a printed circuit board and the board which results from that process.
  • the process employs conventional procedures, but has significant advantages, particularly in that the circuit lines are more accurately defined than in conventional processing. Thus, finer circuit lines can be produced, which can be more densely packed on the board.
  • the process of the present invention is clearly different from conventional circuit board processing in which the circuit lines are formed by selectively etching copper away. As explained above, chemical etching has inherent limitations which become particularly troublesome as circuit lines become narrower and their pitch closer.
  • the new process of the invention deposits the circuit lines directly into spaces created by the use of a photoresist, which leaves open trenches to be filled by electrodeposition of copper. This is made possible by the conductive layer which remains on the surface of the substrate once the covering copper foil carrier has been removed.
  • the process of the invention is also different from that of the Ohmega process in which the layer at the surface of the substrate serves as a resistor.
  • the process is shown in the block diagram of Figure 1 as applied to the outer layers of a multi-layer board.
  • copper foil is passed through a bath of soluble compounds of the conductive metals and they are electrodeposited to a thickness of about 0.2 to 5 ⁇ m on one surface of the foil, either the matte or shiny side.
  • the copper foil may be given a treatment (such as nodular copper) to improve its adhesion to the insulating substrate.
  • the metals or alloys may be tin, nickel, tin-zinc, zinc-nickel, tin-copper and others, provided that they are resistant to the etchant used to remove copper during a subsequent step.
  • the conditions of the electrodeposition process are typical of those used commercially to provide protective metal coatings on copper foil.
  • the coated copper foil is laminated to an insulating substrate, such as the commonly used glass reinforced epoxy resins, using conventional techniques and with the conductive metals next to the substrate.
  • the next step is to etch away the copper foil, leaving the thin layer of conductive metal embedded in the surface of the substrate.
  • the etchant is selected from those which will remove copper, but not the metals of the conductive layer to a significant extent.
  • An example of such etchants is ammoniacal cupric chloride.
  • Thin copper foils have been applied in the past from aluminum supporting layers, with the aluminum being etched away in a similar manner.
  • the copper is electrodeposited using conventional procedures such as are often used to plate copper onto the outside of multilayer circuit boards. It is possible to do this when the thin layer of metals embedded in the surface of the substrate is sufficiently conductive. If not, electroless plating of copper can be used to facilitate the electrodeposition of the circuit lines.
  • the copper can be built up in thickness as desired, up to the height ofthe photoresist which defines the shape ofthe trenches. Conventional electrodeposition conditions will be used.
  • the steps subsequent to applying the conductive metal to the laminate may be performed in whatever method is feasible for the operator
  • the invention has particular value in making the outer layers of multi-layer circuit boards
  • Multilayer circuit boards generally have holes connecting outer with inner layers which are electroless plated with copper and then the circuit lines are formed by electroplating
  • the typical procedure is shown in the block diagram of Figure 2 Copper foil is laminated with an intervening layer of prepreg to the inner circuit layers, but is not etched away Electroless plating is used to deposit copper over the foil and down the holes which connect the layers Then, a resist is applied and the copper circuit lines are electrodeposited At this point, the excess copper foil must be removed by etching However, the circuit lines and the plated holes must be protected by a step of electrodepositing a resistant metal, such as tin Then the resist can be removed and the exposed copper foil etched.
  • a resistant metal such as tin
  • Figure 3 illustrates the circuit lines formed in the outer layers of multi-layer circuit boards by conventional etching processes, compared to the essentially rectangular line formed using the process ofthe invention
  • the circuit lines of the prior art are severely undercut by the need to etch away copper foil after the circuit lines are formed (the top being protected by the tin coating)
  • the process of the invention makes possible more accurate production of circuit lines and thus, the circuit designer does not have to compensate for the inaccuracy inherent in the formation of circuit lines by etching This means the resulting circuit can be smaller and more compact
  • the process uses techniques which are familiar to circuit board manufacturers and does not involve large changes in technology In fact, it is expected that the production processes will be simplified when the process of the invention is adopted

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un nouveau procédé de formation de lignes de circuit sur un substrat, qui consiste à appliquer un ou des métaux conducteurs au moyen d'une feuille de cuivre utilisée comme support. La feuille de cuivre est éliminée par attaque, laissant les métaux conducteurs encastrés dans la surface du substrat. Un agent photorésistant est utilisé pour mettre à nu les canaux formant le circuit désiré, et du cuivre est appliqué sur les métaux conducteurs mis à nu. Ce procédé est notamment approprié pour fabriquer les couches externes des cartes de circuits multicouches.
EP97924540A 1996-05-01 1997-05-01 Nouveau procede de formation de fines lignes de circuit Withdrawn EP0868837A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US846380 1986-03-31
US1666596P 1996-05-01 1996-05-01
US16665P 1996-05-01
US84638097A 1997-04-30 1997-04-30
PCT/US1997/007191 WO1997041713A1 (fr) 1996-05-01 1997-05-01 Nouveau procede de formation de fines lignes de circuit

Publications (1)

Publication Number Publication Date
EP0868837A1 true EP0868837A1 (fr) 1998-10-07

Family

ID=26688922

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97924540A Withdrawn EP0868837A1 (fr) 1996-05-01 1997-05-01 Nouveau procede de formation de fines lignes de circuit

Country Status (3)

Country Link
EP (1) EP0868837A1 (fr)
AU (1) AU2993997A (fr)
WO (1) WO1997041713A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6117300A (en) * 1996-05-01 2000-09-12 Honeywell International Inc. Method for forming conductive traces and printed circuits made thereby
US6884944B1 (en) 1998-01-14 2005-04-26 Mitsui Mining & Smelting Co., Ltd. Multi-layer printed wiring boards having blind vias
TW469228B (en) * 1998-01-14 2001-12-21 Mitsui Mining & Smelting Co Method for producing multi-layer printed wiring boards having blind vias
EP0948247B1 (fr) * 1998-04-01 2005-08-31 Mitsui Mining & Smelting Co., Ltd. Procédé de fabrication de panneau à circuit imprimé multicouche
KR100855528B1 (ko) 1998-09-03 2008-09-01 이비덴 가부시키가이샤 다층프린트배선판 및 그 제조방법
SG90037A1 (en) * 1999-01-29 2002-07-23 Mitsui Mining & Smelting Co Method for producing multi-layer printed wiring boards having blind vias
LU90376B1 (en) * 1999-03-23 2000-09-25 Circuit Foil Luxembourg Trading Sarl Method for manufacturing a multilayer printed circuit board and composite foil for use therein
AU4108300A (en) * 1999-03-23 2000-10-09 Circuit Foil Luxembourg Trading S.A R.L. Method for manufacturing a multilayer printed circuit board and composite foil for use therein
JP4486196B2 (ja) * 1999-12-08 2010-06-23 イビデン株式会社 多層プリント配線板用片面回路基板およびその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS648694A (en) * 1987-06-30 1989-01-12 Hitachi Chemical Co Ltd Manufacture of insulating substrate with thin nickel layer
JPH01124286A (ja) * 1987-11-09 1989-05-17 Hitachi Chem Co Ltd プリント配線板の製造法
US5017271A (en) * 1990-08-24 1991-05-21 Gould Inc. Method for printed circuit board pattern making using selectively etchable metal layers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9741713A1 *

Also Published As

Publication number Publication date
WO1997041713A1 (fr) 1997-11-06
AU2993997A (en) 1997-11-19

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