EP0836173B1

EP0836173B1 - Multiplex driving method of a matrix type liquid crystal electro-optical device

Info

Publication number: EP0836173B1
Application number: EP97120078A
Authority: EP
Inventors: Akihiko Ito; Shoichi Iino
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 1992-05-08
Filing date: 1993-05-10
Publication date: 2002-04-10
Anticipated expiration: 2013-05-10
Also published as: DE69326740D1; EP0598913A1; JP2000347163A; JP3508115B2; EP0836173A3; EP0598913A4; JP3391334B2; TW280874B; DE69331812D1; EP0836173A2; EP0598913B1; DE69326740T2; DE69331812T2; WO1993023844A1

Description

Field of the invention

The present invention relates to a multiplex driving method and a drive circuit of a matrix type liquid crystal electro-optical device such as a liquid crystal display panel, for example. The present invention further relates to a liquid crystal display device.

Description of the prior art

Multiplex driving based on the amplitude selective addressing scheme is one known driving method for liquid crystal devices such as those referred to above.

Prior art example 1

Fig. 19 is an applied voltage waveform diagram showing one example of a prior art driving method of multiplex driving a simple matrix type liquid crystal electro-optical device as shown in Fig. 20 by means of an amplitude selective addressing scheme; Fig. 19 (a) and (b) are the voltage waveforms applied to row electrodes X₁, X₂, respectively, Fig. 19 (c) is the voltage waveform applied to column electrode Y₁, and Fig. 19 (d) is the voltage waveform applied to the pixel at the intersection of row electrode X₁ and column electrode Y₁.
This example sequentially selects row electrodes X₁, X₂,..., X_n, one at a time, and depending on whether each pixel on the selected row electrode is ON or OFF applies a corresponding column voltage waveform to each of the column electrodes Y₁, Y₂,..., Y_m.
When the display is driven by selecting one row electrode at a time as described above, however, a good display cannot be obtained without using a relatively high drive voltage.

Prior art example 2

As a means of reducing the drive voltage, a method of sequentially selecting groups of row electrodes with each group comprising a plurality of simultaneously selected row electrodes has been previously proposed (see A Generalized Addressing Technique for RMS Responding Matrix LCDs, 1988 International Display Research Conference, pp. 80 to 85).
Fig. 21 is an applied voltage waveform diagram showing an example of this prior art driving method of simultaneously selecting and driving plural row electrodes, Fig. 21 (a) being the row voltage waveforms applied to the row electrodes X₁, X₂, and X₃, (b) the row voltage waveforms applied to row electrodes X₄, X₅, and X₆, (c) the column voltage waveform applied to column electrode Y₁, and (d) the voltage waveform applied to the pixel at the intersection of row electrode X₁ and column electrode Y₁.
This example simultaneously selects three sequential row electrodes (or lines) at a time for a display pattern as shown in Fig. 20. Specifically, three row electrodes X₁, X₂, and X₃ are first selected by row voltages as shown in Fig. 21 (a) applied to these row electrodes X₁, X₂, and X₃, and a specified column voltage is simultaneously applied to each of the column electrodes Y1 to Y_m as described in more detail below. Next, row electrodes X₄, X₅, and X₆ in Fig. 20 are selected by row voltages such as shown in Fig. 21 (b) applied as described above, and a column voltage is simultaneously applied to each of the column electrodes Y₁ to Y_m. One frame is completed when all row electrodes X₁ to X_n have been selected, and this operation is then repeated.
If the number of simultaneously selected row electrodes in this method is h, then 2^h row select patterns are used for the row electrode voltage waveforms. In this example, h = 3, so 2^h = 2³ = 8 row select patterns are used.
The row select patterns, i.e., when a positive pulse of a voltage waveform applied to a row electrode is defined as an ON state and a negative pulse as an OFF state, the voltage ON/OFF patterns applied to the three simultaneously selected row electrodes X₁, X₂, and X₃ are shown in the following table using values of 1 and 0 to represent an ON state and an OFF state, respectively.

X₁ 0 0 0 0 1 1 1 1

X₂ 0 0 1 1 0 0 1 1

X₃ 0 1 0 1 0 1 0 1
The voltage waveforms generated based on these values for application to the row electrodes are shown in Fig. 22 (a). The waveforms shown in Fig. 22 (a), however, contain several different frequency components, which can result in display ununiformity when applied.
Waveforms modified by reordering the row select patterns in the array shown above to reduce the differences in the frequency components are shown in Fig. 22 (b). The prior art example shown in Fig. 21 also uses these waveforms.
However, the column voltages applied to each of the column electrodes Y₁ to Y_m have the same number of patterns as the row voltages, and the voltage level of each pulse in the column voltage waveform has a value corresponding to the ON/OFF states of the selected row electrodes. In this case as mentioned above, for example, an ON state is when the row voltage waveform applied to any of the simultaneously selected row electrodes X1, X2, and X3 is a positive pulse and an OFF state is when it is a negative pulse. For each column electrode, the ON/OFF states of the display data (the display data pattern) for the pixels formed at the intersections of the column electrode and each of the simultaneously selected row electrodes, are compared pixel by pixel or bit by bit with the ON/OFF states of the selected row electrodes, and the level of the column voltage waveform is set according to the number of mismatches.
In other words, in Fig. 21, pulse voltages -V_Y2, -V_Y1, V_Y1, and V_Y2 are applied when the number of mismatches is 0, 1, 2, and 3, respectively. Note that the voltage ratio of V_Y1 to V_Y2 is V_Y1:V_Y2 = 1:3.
Specifically, if V_X1 corresponds to ON and -V_X1 to OFF in the voltage waveforms applied to row electrodes X1, X2, and X3 in Fig. 21 , and ON and OFF pixels are represented with a solid and a white dot, respectively, in Fig. 20, the pixels at the intersections of row electrodes X₁, X₂, and X₃ and column electrode Y₁ are ON-ON-OFF, respectively, and the initial row select pattern of the voltage applied to these row electrodes X₁, X₂, and X₃ is OFF-OFF-OFF. Because the number of mismatches between the display data pattern, i.e. the ON/OFF pattern of the pixels, and the row select pattern is two if they are compared in sequence, voltage V_Y1 as shown in Fig. 21 (c) is applied as the first pulse to the column electrode Y₁.
The second row select pattern of the voltage applied to the row electrodes X₁, X₂, and X₃ is OFF-OFF-ON; because each of these is a mismatch when compared sequentially with the previous ON-ON-OFF display data pattern and the number of mismatches is therefore three, voltage V_Y2 is applied as the second pulse to column electrode Y₁. Similarly, V_Y1 is applied as the third pulse, -V_Y1 as the fourth pulse, and the following pulses are, in sequence, -V_Y2, V_Y1, -V_Y1, - V_Y1.
The next group of three row electrodes X₄ to X₆ are then selected, and when the voltages shown in Fig. 21 (b) are applied to these row electrodes X₄ to X₆, a column voltage of the voltage level corresponding to the number of mismatches between the ON/OFF states of the pixels at the intersections of row electrodes X₄ to X₆ and the column electrode, i.e. the display data pattern, and the ON/OFF states of the voltages applied to the row electrodes X₄ to X₆, i.e. the row select pattern, is applied as shown in Fig. 21 (c).
Note that while the values 1 and 0 are used for the positive and negative selection pulses, respectively, of the row voltage waveforms, and 1 and 0 are used for the ON and OFF display data states of pixels, respectively, and the column voltage waveform is set according to the number of mismatches, the values of 1 and 0 can be exchanged for each other and further the column voltage waveform can also be set according the number of matches or according to the difference between the number of matches and the number of mismatches.
As described above, this method of simultaneously selecting and driving plural sequential row electrodes allows to reduce the drive voltage while achieving the same on/off contrast ratio as the single line selection method explained with reference to Fig. 19.
The general conditions, summary, and procedure of this method of simultaneously selecting and driving plural row electrodes and sequentially selecting groups of such simultaneously selected row electrodes are described in order below.

A. Conditions

(a) N row electrodes are divided into N/h groups.
(b) Each group comprises h address lines each corresponding to one row electrode.
(c) The display data pattern of each column electrode at any given time is represented by an h bit word:
d_k·h+1, d_k-h+2, ..., d_k·h+h; d_k·h+1 = 0 or 1
where O ≤ k (N/h)-1 and k is the group number. In other words, the display data for one column electrode can be defined as
d₁, d₂,..., d_h group 0
d_h+1, d_h+2,..., d_h+h group 1
d_N-h+1, d_N-h+2,..., d_N-h+h group N/h-1.
(d) The row select pattern is an h bit word of a cycle 2^h:
a_k·h+1, a_k·h+2,..., a_k·h+h; a_k·h+j = 0 or 1.

B. Summary

(1) One group is selected at a time with the row electrodes forming the group being simultaneously selected.
(2) One h-bit word is selected as the row select pattern determining the voltages to be applied to the simultaneously selected row electrodes.
(3) The row voltage is -Vr for logic 0 (representing the OFF state) of the row select pattern, +Vr for logic 1 (representing the ON state), and 0 V for unselected row electrodes.
(4) For each column electrode the h-bit word of the row select pattern of the selected group is compared bit by bit with the h-bit word of the respective display data pattern.
(5) The number of bit mismatches i between the h-bit word representing the row select pattern and that representing the display data pattern is determined.
(6) The voltage applied to the column electrode is V_(i) where i is the number of mismatches. (One predetermined voltage is selected according to the number of mismatches.)
(7) Based on this method, the column voltages are determined (simultaneously and in parallel).
(8) The row and column voltages thus determined are applied to the row and column electrodes, respectively, of the display matrix for the time duration Δt_o only (where Δt_o is the minimum pulse width).
(9) A new row select pattern is selected and steps (4) to (6) are recalculated, and the next column voltage is determined. This voltage is also applied for Δt_o only.
(10) A cycle is completed when all the N/h groups have been selected once, each with all the 2^h row select patterns. 1 cycle = Δt·2h·(N/h).

C. Analysis

The possible row electrode select patterns when there are i mismatches are considered below.
The number of h-bit row-select patterns which differ from an h-bit display data pattern in i bits is given by hCi = h!/{i!(h-i)!} = Ci.
For example, if h = 3 and the row select pattern is (0,0,0), the following data pattern variations are possible.

No. of mismatches Data pattern (column electrode) Ci

i = 0 (0,0,0) 1 pattern

i = 1 (0,0,1) (0,1,0) (1,0,0) 3 patterns

i = 2 (1,1,0) (1,0,1) (0,1,1) 3 patterns

i = 3 (1,1,1) 1 pattern
The number of Ci is determined by the number of bits in one word, and not by the row select pattern.
The level V_pixel of the momentary voltage applied to the pixel is defined as Vpixel = (Vcolumn - Vrow) or (Vrow - Vcolumn) where V_row is the row voltage and V_column is the column voltage.
assuming that V_row = ±Vr and Vcolumn = V_(i), then Vpixel = +Vr - V(i) or -Vr - V(i). assuming that V_row = ±Vr and Vcolumn = ±V_(i), then Vpixel = Vr - V(i), Vr + V(i), -Vr - V(i), or -Vr + V(i).
In other words, Vpixel = |Vr - V(i)| or |Vr + V(i)|.
Thus, the specific voltage level applied to a pixel is -(Vr + V_(i)) or (Vr - V_(i)) for a selected line (row electrode), and V_(i) for unselected lines (row electrodes).
(The result will be as described in the above mentioned paper if V_(i) is bipolar.)
In general, it is preferable in terms of achieving a high contrast ratio that the voltage applied to a given pixel be as high as possible with ON pixels and as low as possible with OFF pixels. Thus,

when ON,: |Vr + V_(i)| works favorably for ON pixels,
|Vr - V_(i) I works unfavorably for ON pixels;
when OFF,: |Vr - V_(i)| works favorably for OFF pixels,
|Vr + V_(i)| works unfavorably for OFF pixels,

As mentioned above, the number of h-bit row select patterns which differ from an h-bit display data pattern in i bits is Ci = hCi = (h!} / {i!(h-i)!} where, if i is the number of mismatches, this is the number of cases in which i bits will mismatch in a select pattern of h bits. Because the number of mismatches is i in each of the Ci row select patterns, the total number of mismatches is i · Ci.
Because these mismatches are distributed through h bits, the average number of mismatches Bi per pixel (per one bit) is Bi = i · Ci/h (number/pixel).
In addition, if the column voltage V_(i) level increases with the increase in the number i of mismatches, then Vpixel = Vrow - Vcolumn will decrease with the increase in the number of mismatches.
If a mismatch is considered to work unfavorably for the target ON pixel, the number of mismatches will provide the number of unfavorable voltages (column voltages).
Therefore, the number of unfavorable voltages per pixel (on average) is Bi = i · Ci/h.
However, because i/h of Ci is unfavorable, the remainder, i.e., Ai = {(h-i)/h} · Ci works favorably. In addition, {(h-i)/h} Ci + (i/h) · Ci = (h/h)Ci = Ci, and Ai = Ci - Bi = {(h-1)!}/{i · (h-i-1)!} where h · + 1.
Summarizing the above, we obtain VON(rms) = {(S1 + S2 + S3)/S4}1/2 VOFF(rms) = {(S5 + S6 + S3)/S4}1/2
Note also that:

S4 = 2h·(N/h)
In addition, Vr/V(o) = N1/2/h row selection voltage V(i)/V(o) = (h-2i)/h = {1-(2i/h)} column voltage,
and R = (VON/VOFF)max = {(N1/2 + 1)/(N1/2 - 1)}1/2.
When plural sequential row electrodes are simultaneously selected and driven as in prior art example (2) described above, however, the pulse width applied to the row electrodes and column electrode gets narrower as the number of simultaneously selected row electrodes increases, and picture quality deteriorates as crosstalk increases due to waveform rounding. This problem is particularly noticeable when this driving method is applied to gray scale displays using pulse width modulation.
US-A-5,075,683 discloses a method and device for controlling a matrix screen displaying grey levels using time modulation. Single rows of the matrix configuration are successively selected, each for one line or selection period. The selection period is divided into subperiods and, depending on the respective grey scale level, a column voltage is or is not applied in each subperiod. In other words, grey levels are displayed by changing the time during which within each selection period a certain voltage is applied.
The object of the present invention is to provide a driving method and a drive circuit of a matrix type liquid crystal device, and a liquid crystal display device capable of achieving a good gray scale display even when simultaneously selecting and driving plural row electrodes.

Disclosure of the invention

This object is achieved with a driving method, a driving circuit and a display device, respectively, as claimed.
By using the driving method according to the invention, there is little crosstalk, etc., generated and a good gray scale display can be achieved even when simultaneously selecting plural row electrodes for multiplex driving.

Brief Description Of The Drawings

Fig. 1: is a voltage waveform diagram showing a first embodiment of a driving method,
Fig. 2: is a diagram showing display data and the basic configuration of a matrix type liquid crystal device,
Fig. 3: is a diagram used to describe the row voltage waveforms applied to the row electrodes,
Fig. 4: is a block diagram of a first embodiment of a drive circuit,
Fig. 5: is a block diagram of the row electrode driver,
Fig. 6: is a block diagram of the column electrode driver,
Fig. 7: is a voltage waveform diagram showing an alternative embodiment of a driving method,
Fig. 8: is used to describe the display data and operation when driving is performed while using a virtual electrode,
Fig. 9: is a voltage waveform diagram showing an alternative embodiment of a driving method,
Fig. 10: is a diagram used to describe a gray scale display achieved by means of pulse width modulation,
Fig. 11: is a voltage waveform diagram showing an alternative embodiment of a driving method,
Fig. 12: is a voltage waveform diagram showing an alternative embodiment of a driving method,
Fig. 13: is a diagram similar to that of Fig. 2 which is used to describe the display data and location of the virtual electrodes,
Fig. 14: is a voltage waveform diagram showing an alternative embodiment of a driving method,
Fig. 15: is a voltage waveform diagram showing an embodiment of a driving method according to the present invention,
Fig. 16: is a diagram used to describe the display data and location of the virtual electrodes,
Fig. 17: is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention,
Fig. 18: is a diagram used to describe the display data and location of the virtual electrodes,
Fig. 19: shows voltage waveforms of one prior art driving method for a liquid crystal device, etc.,
Fig. 20: is a diagram used to describe the display pattern,
Fig. 21: shows voltage waveforms of another prior art driving method for a liquid crystal device, etc.,
Fig. 22: is a diagram used to describe the voltage waveform applied to the row electrodes.

Embodiment 1

Fig. 1 is an applied voltage waveform diagram used to describe a first embodiment of a driving method, Fig. 1 (a) being the voltage waveforms applied to row electrodes X₁, X₂, and X₃, (b) being the voltage waveforms applied to row electrodes X₄, X₅, and X₆, (c) being the voltage waveform applied to column electrode Y₁, and (d) being the (composite) voltage waveform applied to the pixel at the intersection of row electrode X₁ and column electrode Y₁.
The present embodiment simultaneously selects three sequential row electrodes to achieve the display as shown in Fig. 2.
While the type waveforms shown in Fig. 22 (a) or (b) can be used as the voltage waveforms applied to the simultaneously selected row electrodes, a type of waveforms as shown in Fig. 1 (a) is used in this embodiment.
The problem when voltage waveforms as shown in Fig. 22 (a) or (b) are used is that each pulse width becomes narrower. Particularly when the number of simultaneously selected row electrodes increases, there is an exponential increase in the number of row select patterns and each pulse width necessarily becomes narrower, leading to a possible rounding (waveform distortion) of the waveform actually applied to a pixel, and even possibly to crosstalk due to such rounding. In this embodiment and in the embodiments achieving a gray scale display by pulse width modulation as described below, the pulse width would be even narrower, resulting in crosstalk.
In the present embodiment, therefore, the voltage waveforms applied to the row electrodes are set as described below so that the pulse width is wider.
The voltage waveforms applied to the row electrodes are decided based on the conditions that:
(1) each row electrode must be identifiable,
(2) the frequency components of the voltage waveforms applied to the row electrodes must not differ significantly, and
(3) the AC drive of the liquid crystal must be ensured, i.e. there must be no DC component in the waveform when averaged over one or plural frames.
In other words, the pattern of the applied voltages is appropriately determined from a natural binary, Walsh, Hadamard, or other systems of orthogonal functions considering the above conditions.
Of these conditions, the first is absolute. To satisfy this condition the voltage waveforms applied to each row electrode are generated so that they are orthogonal to each other.
The applied voltage waveforms shown in Figs. 3 (a) and (b) were determined considering the above conditions. The applied voltage waveforms in Fig. 3 (a) contain different frequency components, namely
X₁: 4·Δt_o
X₂: 4·Δt_o, 2·Δt_o
X₃: 2·Δt_o.
The applied voltage waveforms in Fig. 3 (b) contain different frequency components, namely
X₁: 4·Δt_o, 2·Δt_o
X₂: 4·Δt_o, 2·Δt_o
X₃: 6·Δt_o, 2·Δt_o.
While the shortest pulse width in the waveforms shown in Fig. 22 (a) and (b) is Δt_o, the narrowest pulse width in the waveforms in Fig. 3 (a) and (b) is 2Δt_o, an increase by a factor of 2. It is thus possible, by increasing the pulse width, to reduce the effects of waveform rounding, decrease crosstalk, and increase the number of simultaneously selected row electrodes.
It is to be noted that the waveforms shown in Fig. 3 (a) and (b) are one example and can be changed as appropriate, and that the row electrode selection sequence and sequence of the row select patterns applied to the row electrodes can also be changed using the properties of the systems of orthogonal functions.
The row voltage waveforms shown in Fig. 1 (a) and (b) form the voltage waveforms applied to the three simultaneously selected row electrodes based on the waveform in Fig. 3 (b). In addition, in this embodiment, the selection period is divided into four separate selection subperiods t₁, t₂, t₃, t₄ in each frame.
Each of the selection subperiods t₁, t₂, t₃, t₄ divided as described above is subdivided into plural intervals as shown in Fig. 1 (c), and in each of these intervals a weighted voltage is applied to the column electrodes Y1 to Y_m to obtain a desired display.
In other words, in this embodiment, subperiod t₁ is subdivided into two equal intervals a and b. As shown in Fig. 2, the display data for each pixel are composed of two bits representing a binary code for a gray scale display with four gradations. A column voltage specifically weighted for each bit based on the display data shown in Fig. 2 is applied, during interval a for the high or most significant bit and during interval b for the low or least significant bit as shown in Fig. 1.
Specifically, if voltage V_X1 applied to a row electrode represents the ON states and -V_X1 the OFF state, and the display data value 0 represents OFF and 1 ON, and the ON/OFF states of the simultaneously selected row electrodes and the ON/OFF state of the display data are compared bit by bit to calculate the number of mismatches, the voltages applied for the high bit when the number of mismatches is 3, 2, 1, and 0, respectively, are V_Y4, V_Y2, -V_Y2, and -V_Y4, and the voltages applied for the low bit when the number of mismatches is 3, 2, 1, and 0, respectively, are V_Y3, V_Y1, -V_Y1, and -V_Y3. Note that the relationship between each of the voltage levels is 2·VY1 = VY2 2·VY3 = VY4 2·VY1 = VY3 - VY1 2·VY2 = VY4 - VY2.
For example, during subperiod t₁ in Fig. 1 (c), the selected pulses applied to row electrodes X₁, X₂, and X₃ are ON, ON, OFF, respectively, and the display data for the pixels at the intersections of column electrode Y₁ and row electrodes X₁, X₂, and X₃ are (00), (01), (10), i.e. the high bits represent OFF, OFF, ON. Comparison shows the number of mismatches is three, and voltage V_Y4 is therefore applied to the column electrode Y₁ in interval a. Since the low bits represent OFF, ON, OFF, the number of mismatches compared with the row select pattern is one, and voltage - V_Y1 is therefore applied in interval b.
Thus for each of the column electrodes Y1 to Y_m, the display data for the pixels on the row electrodes X₁, X₂, and X₃ is compared with the selected pulses applied to the row electrodes (the row select pattern), and a column voltage corresponding to the number of mismatches is applied.
Next, row electrodes X₄, X₅, and X₆ are simultaneously selected and the corresponding column electrode waveforms are applied to the column electrodes. When the sequence of simultaneously selecting the row electrodes, three at a time, and applying the corresponding column electrode waveforms to the column electrodes until all row electrodes X₁ to X_n have been scanned is completed, the operation returns to the first group of row electrodes X₁, X₂, and X₃ and the specified voltages are sequentially applied following the above sequence in subperiods t₂, t₃, and t₄. When all row electrodes X₁ to X_n have been scanned in each of the four subperiods t₁ to t₄, the next frame starts and the process is repeated. Note that the polarity of the applied voltage is reversed every frame in this embodiment for a so-called alternating current drive scheme.
A good gray scale display with minimal crosstalk can thus be achieved by driving as described above.
It is to be noted that the sequence of the row voltage waveforms applied to the row electrodes in the above subperiods t₁ to t₄ can be changed for all frames or in single frames, and the waveforms shown in Fig. 3 (a) or other waveforms satisfying the conditions described above can be used as the row voltage waveforms applied to the row electrodes. Moreover, two kinds of waveforms can be alternately used for each group of simultaneously selected row electrodes, for example the kind of waveforms shown in Fig. 3 (a) for row electrodes X₁ to X₃ and the kind of waveforms shown in Fig. 3 (b) for row electrodes X₄ to X₆, or a sequence of three or more kinds of waveforms can be used alternately. In addition, it is also possible to combine reordering the waveforms in subperiods t₁ to t₄ with reordering the waveforms for the groups of simultaneously selected row electrodes.
While the subperiods t₁ to t₄ can be separate in each frame period as in the above embodiment, or can be consecutive in each frame, if the subperiods of the selection period are separate, i.e. distributed within one frame as in the present embodiment, the period during which a row electrode continuously stays unselected becomes shorter and the contrast can be improved. In this case, while the selection period is divided into four subperiods t₁ to t₄ in the above embodiment, any number of divisions can be used; further, each of the subperiods t1 to t4 can be subdivided into two intervals as explained above, or it can be subdivided into more than two intervals allowing more gradations.
In addition, three row electrodes, sequential in position, are selected at a time in the above embodiment, but the number of the selected row electrodes can be any appropriate number and the row electrodes forming a group of simultaneously selected row electrodes do not necessarily need to be sequential in position.
The above modifications can also be applied to the alternative embodiments described below.
A drive circuit executing the driving method described above is described based on Figs. 4 to Fig. 6.
Fig. 4 is a block diagram showing one example of a drive circuit. In this figure 1 is a row electrode driver, 2 is a column electrode driver, 3 is a frame memory, 4 is an arithmetic operation circuit, 5 is a row data generating circuit, and 6 is a latch.
Fig. 5 is a block diagram of the row electrode driver, Fig. 6 is a block diagram of the column electrode driver, and in Fig. 5 and Fig. 6, 11 and 21 are shift registers, 12 and 22 are latches, 13 and 33 are decoders, and 14 and 24 are level shifters.
In this configuration, each row electrode waveform is generated based on a scan data signal S3 indicating a positive selection, negative selection, or no selection, the scan data signal being generated from the row data generating circuit 5 and sent to the row electrode driver 1.
In the row electrode driver 1, as shown in Fig. 5, the scan data signal S3 from the row data generating circuit 5 is sent to the shift register 11 at the scan shift clock signal S5, and after the data for each of the row electrodes in one scanning period have been entered into the shift register, the data are latched in the latch 12 at latch signal S6 , the data expressing the state of each row electrode are then decoded by decoder 13, and the decoded outputs are used, via level shifter 14, to switch on one of three analog switches 15 provided for each output, and voltage V_X1, -V_X1, or 0 is selected and output to the respective row electrode when the selection is positive, negative, or no selection, respectively.
For the column electrode waveforms, the display data signal S1 for the three simultaneously selected row electrodes X₁, X₂, and X₃ is read from frame memory 3, and the display data signal S1 and scanning data signal S3, latched in latch 6, are converted by the arithmetic operation circuit 4. This data conversion is performed as described above, and the converted data are transferred to the column electrode driver 2 as column data signal.
In the column electrode driver 2, as shown in Fig. 6, the column data signal S2 from the arithmetic operation circuit 4 is sent to shift register 21 at shift clock signal S7, and after the data for each column electrode in one scanning period have been input, the data are latched in latch 22 at the latch signal S8, the data expressing the state of each column electrode are then decoded by decoder 23 whose outputs are used, via level shifter 24, to switch on one of the eight analog switches 25 provided for each output, and one of the eight voltages V_Y4, V_Y3, V_Y2, V_Y1, -V_Y1,-V_Y2, -V_Y3, and -V_Y4 is output to each column electrode.
A driving method as described above can thus be simply and reliably achieved by using a drive circuit as described above.
If a display apparatus comprising a display device as described above comprises a drive circuit as described above to execute the driving method as described above, a display apparatus capable of achieving a good gray scale display with minimal crosstalk generated can be achieved.

Embodiment 2

In the first embodiment one of four voltages is selected according to the display data and applied to the column electrodes for each bit of the display data, but by providing a virtual electrode the number of voltage levels applied to the column electrodes can be reduced.
Fig. 7 is a voltage waveform diagram for an embodiment that is capable of driving by a reduced number of voltage levels applied to the column electrodes by providing a virtual row electrode in each group of simultaneously selected row electrodes, and Fig. 8 illustrates the basis for reducing the number of voltage levels applied to the column electrodes by providing a virtual electrode.
This embodiment provides, for example, virtual row electrodes X_n+1, X_n+2,... each after a corresponding group of simultaneously selected row electrodes as shown in Fig. 8, such that virtual row electrode X_n+1 is selected simultaneously with row electrodes X₁, X₂, and X₃, for example. The number of mismatches is calculated as in the first embodiment assuming voltage V_X1 is applied to the row electrode in each ON state, -V_X1 is applied in each OFF state, and the display data value 0 represents OFF and 1 ON. In this case, the number of mismatches is always 1 or 3 by appropriately changing the ON/OFF state of the virtual row electrode.
When the number of mismatches between the row select pattern and the high bits of the display data pattern is 1, -V_Y2 is selected, and when the number of mismatches is 3, V_Y2 is selected; when the number of mismatches between the row select pattern and the low bits of the display data pattern is 1, -V_Y1 selected, and when the number of mismatches is 3, V_Y1 is selected. Note that the relationship between each of the voltage levels is 2·V_Y1 = V_Y2.
The display shown in Fig. 2 is achieved by the waveforms in Fig. 7 applying the above principle. During subperiod t₁, the selected pulses applied to row electrodes X₁, X₂, X₃ and virtual row electrode X_n+1 are ON, ON, OFF, ON, respectively, the display data for the pixels at the intersections of column electrode Y₁ and row electrodes X₁, X₂, X₃ and virtual row electrode X_n+1 are (00), (01), (10), (11), and the high bits represent OFF, OFF, ON, ON. Sequential comparison shows the number of mismatches is three; conversion data S2 is therefore generated according to this number of mismatches, and voltage V_Y2 is therefore applied to the column electrode Y₁ in interval a.
The low bits represent OFF, ON, OFF, ON, and the number of mismatches if compared with the row select pattern is one; conversion data S2 is therefore generated according to this number of mismatches, and voltage -V_Y1 is therefore applied in period b.
Thus, the display data for the pixels on the row electrodes X₁, X₂, X₃ and virtual electrode X_n+1, i.e. the display data pattern, is compared with the selected pulses applied to the row electrodes, i.e. the row select pattern, for each of the column electrodes Y1 to Y_m, and a column voltage corresponding to the number of mismatches is applied.
Next, row electrodes X₄, X₅, X₆ and virtual row electrode X_n+2 are simultaneously selected and the corresponding column electrode waveforms are applied to the column electrodes. When the sequence of simultaneously selecting the row electrodes, three row electrodes at a time plus one virtual row electrode, and applying the corresponding column electrode waveforms to the column electrodes until all row electrodes to X₁ to X_n have been scanned is completed, the operation returns to the first group of row electrodes X₁, X₂, and X₃ and sequential scanning using the row select pattern shown in t₂ continues. One frame period is completed by scanning four times with the row select patterns shown in t₁, t₂, t₃, and t₄, and the same operation is repeated in the next frame.
By thus providing virtual electrodes as above, the number of voltage levels applied to the column electrodes can be made less than that of the first embodiment.
The principle of reducing the number of voltage levels applied to the column electrodes by providing virtual electrodes as described above can also be applied to each of the embodiments described below.
In addition, the same drive circuit as that used in the first embodiment can be used in the present embodiment and each of the embodiments described below. In this case, the arithmetic operation circuit 4 in Fig. 4 is adapted to execute data processing according to each of the embodiments, the voltage levels of the row electrode driver in Fig. 5 and the column electrode driver in Fig. 6 are provided according to each embodiment, and one of the voltage levels is selected by analog switches 15, 25.
In this embodiment, for example, the arithmetic operation circuit 4 in Fig. 4 and the row electrode driver in Fig. 5 are the same as those of the first embodiment, but while eight voltage levels V_Y4, V_Y3, V_Y2, V_Y1, -V_Y1, -V_Y2, -V_Y3, and -V_Y4 are provided in the column electrode driver of the first embodiment in Fig. 6, it is sufficient to provide four voltage levels V_Y2, V_Y1, -V_Y1, and -V_Y2 in the present embodiment.

Embodiment 3

The above embodiment achieves a gray scale display by changing the voltage value according to the display data, but a gray scale display can also be achieved by changing the pulse width.
Fig. 9 is an applied voltage waveform diagram of an embodiment achieving a gray scale display by changing the pulse width.
The general procedure for achieving a gray scale display by means of pulse width modulation is described first.
In general, the period Δt of each pulse is divided into f subperiods of unequal duration to achieve a gray scale display by means of pulse width modulation. Δtg = 2g-1/(2f - 1), g = 1, ..., f where f is the bit number of the binary coded gradation number.
For example, if f = 2, there are 2² = 4 gradations, and the period is divided into two subperiods: Δt1 = (1/3)Δto Δt2 = (2/3)Δto as shown in Fig. 10.
The display data is then represented by f bits: d1 = (d1.f, d1,f-1,..., d1.1) d2 = (d2.f, d2,f-1,..., d2,1) ... dh = (dh,f, dh,f-1,..., dh,1) ...
The row select pattern and the display data pattern are then compared bit by bit, separately for each bit position of the display data, at an interval of Δt_g.
For example, when f = 2, d1 = (d1,2, d1,1) d2 = (d2,2, d2,1) ...
The low or least significant bits (d_1,1, d_2.1,...) of the display data pattern (d₁, d₂,...) and the bits of the row select pattern are first compared and column voltage waveforms corresponding to the result is applied for display for subperiod Δt₁.
The next to least significant bits d_1,2, d_2.2,... and the row select pattern are then compared and corresponding column voltage waveforms applied for subperiod Δt₂.
If f > 2, this is sequentially repeated as above for each bit position.
Fig. 9 based on the present embodiment achieves a four gradation gray scale display as shown in Fig. 2 using pulse width modulation as described above.
In this example, the row voltage waveforms applied to the row electrodes X₁ to X_n are the same as in the prior art example illustrated in Fig. 21, and the pulse widths of the column voltage waveforms applied to the corresponding column electrodes Y₁ to Y_m are modulated according to the gray scale display as above.
In other words, each pulse width Δt is divided into three equal parts, and a gray scale display with four gradations 0 to 3 is expressed using the 2-bit binary display data expressions (○○), (01), (10), (11). The signal voltage level of two of the three pulse width parts is determined based on the number of mismatches between the ON/OFF state of the simultaneously selected row electrodes and the high bit states of the display data pattern. The signal voltage level of the remaining one part is determined based on the number of mismatches between the ON/OFF state of the row electrodes and the low bit states. Variations in the brightness of the gray scale display can be corrected by equally reducing the three parts.
Specifically, if in Fig. 9 an ON state is achieved by applying voltage V_X1 to the row electrode and an OFF state by applying voltage -V_X1, the first pulses applied to the row electrodes X₁, X₂, and X₃ generate an OFF state for all three row electrodes. Because a low bit value of 0 indicates an OFF state and a low bit value of 1 an ON state in the display data for the row electrodes X₁, X₂, and X3 in Fig. 2, the corresponding states are OFF, ON, OFF. The number of mismatches is therefore one, and the voltage pulse during pulse width part Δt₁ is -V_Y1. Because the high bit states are OFF, OFF, ON, the number of mismatches is one, and the voltage pulse during pulse width part Δt₂ is -V_Y1. It is thus sufficient to obtain the voltage pulse applied to the column electrodes by a comparison executed each selection pulse width part Δt.
In this embodiment, the voltage for the high bit is applied during the latter two of the three pulse width parts, and the voltage for the low bit is applied during the first of the three pulse width parts.

Embodiment 4

The selection period can also be divided into plural separate selection subperiods each frame as described in the first embodiment above to drive a gray scale display.
An example of such application is shown in Fig. 11. The voltage waveforms of eight row select patterns (blocks) applied to the row electrodes and column electrodes in the embodiment shown in Fig. 9 are divided into eight equal selection subperiods one for each row select pattern.
When the liquid crystal device is driven by dividing the selection period into plural separate selection subperiods in one frame as described above, the contrast can be improved as in the previous embodiment.

Embodiment 5

The four voltage levels V_Y2, V_Y1, -V_Y1, and -V_Y2 are used as the column electrode voltage levels in the third and fourth embodiments above, but this number of voltage levels can be further reduced by providing virtual row electrodes as in the second embodiment.
Fig. 12 shows an example that makes use of the virtual electrodes of the third embodiment to reduce the number of voltage levels applied to a column electrode, and is driven by dividing the selection period in to plural separate selection subperiods within each frame as in the fourth embodiment.
Reducing the number of voltage levels by providing virtual electrodes has already been described in the second embodiment, but is described further below, including the general method.
First, of the h row electrodes in each group, e column electrodes are operated as virtual row electrodes (virtual lines). By controlling the data matching/mismatching of these virtual row electrodes, the overall number of matches/mismatches can be controlled, and the number of drive voltage levels for the column electrodes can be reduced.
If the number of mismatches is Mi and Vc is an appropriate constant, the voltage V_column applied to the column electrode is defined as
or simply Vcolumn = V(i), where 0 ≤ i ≤ h.
In any event, V_column has h + 1 levels.
The case where the number of groups h = 4 and the number of virtual row electrodes e = 1 is considered by way of example below.

As in the previous embodiment, the number of levels when h = 3 is four (-V_Y2, -V_Y1, V_Y1, V_Y2). If the number of mismatches is controlled using the virtual row electrodes to be an even number, the resulting voltage levels are shown in the following table.

Original voltage level	Original number of mismatches	Virtual row electrode	Number of mismatches after correction	Voltage level after correction
-V_Y2	0	Match	0	V_a
-V_Y1	1	Mismatch	2	V_b
V_Y1	2	Match	2	V_b
V_Y2	3	Mismatch	4	V_d

As shown in the above table, the original four voltage levels can be reduced to three. If the number of mismatches is controlled to be odd, the number of mismatches after correction will change in the above table to 1, 1, 3, 3 (from the top), and there will be only two voltage levels (Va, Va, Vb, Vb from the top) after correction.

If the number of groups h = 4 and the number of unreduced voltage levels is therefore five (-V_Y2, -V_Y1, 0, V_Y1, V_Y2), controlling the number of mismatches to be an even number using the virtual row electrode results in the voltage levels shown in the following table.

Original voltage level	Original number of mismatches	Virtual row electrode	Number of mismatches after correction	Voltage level after correction
-V_Y2	0	Match	0	V_a
-V_Y1	1	Mismatch	2	V_b
0	2	Match	2	V_b
V_Y2	3	Mismatch	4	V_d
V_Y2	4	Match	4	V_d

The original number of voltage levels can thus be reduced from five to three. Note that the voltage levels can also be set by controlling the number of mismatches to be odd.
It is not always necessary to physically provide these virtual row electrodes because they are not normally used for display. When they are provided, however, the virtual row electrodes can be provided in an area not affecting the display. When provided in a liquid crystal display device, for example, the virtual row electrodes X_n+1,..., are provided outside the display area R as defined in Fig. 13. Alternatively, any extra row electrodes outside the normal display area R can also be used as virtual row electrodes.
The number of voltage levels can be further reduced by increasing the number e of virtual row electrodes. In the above example the number of mismatches is controlled to be divisible by two when e = 1, but if e = 2, the same result can be obtained by controlling the number of mismatches to be divisible by three. It is also possible to divide by three to leave a remainder of one or two.
The maximum reduction possible with the above method is 1/(e + 1), or 1/2 when e = 1 (except for 0 V).
The present embodiment as shown in Fig. 12 simultaneously selects three row electrodes and one virtual electrode to reduce the number of voltage levels applied to the column electrodes, and drives by dividing the selection period into plural separate subperiods in each frame.
As shown in Fig. 12 and Fig. 14, the present embodiment divides the selection period into four separate subperiods a frame, and the number of mismatches between the row select pattern and the display data pattern is counted bit by bit for four row electrodes, including the virtual row electrode, in each of the four subperiods to adjust the number of mismatches to an odd number. The number of mismatches is thus either 1 or 3, and the voltage level of the column voltage waveform is therefore one of two levels, V_Y1 or -V_Y1.
Considering the display shown in Fig. 13, the virtual row electrode X_n+1, even though shown outside of the display area R, is part of the first group of simultaneously selected row electrodes including the first three selected row electrodes X₁, X₂, and X₃ and the virtual row electrode X_n+1 as shown in Fig. 8. Again, it is not essential for the virtual row electrode to be actually existent, but when it exists, it is preferably provided outside the display area R.
If a positive voltage applied to a row electrode is represented by ON and a negative voltage by OFF, each of the selection subperiods Δt is subdivided into three intervals, and the display data for the pixels on the simultaneously selected row electrodes X₁, X₂, and X₃ is (00), (01), (10) as shown in Fig. 13, then the display data for the virtual row electrode is (11) as shown in Fig. 8.
As explained earlier, the number of mismatches between the row select pattern and the display data pattern is then counted separately for each bit position (high and low in case of 2-bit display data) to determine either voltage level V_Y1 or -V_Y1, and the voltages for the high bits are applied for the latter two of the three intervals and the voltage for the low bit is applied for the first one interval. Note that, as in the third embodiment, it is also possible to apply the voltages for the high bits in the first two intervals and to apply the voltages for the low bits in the last one interval.
It is therefore sufficient to determine the pulse width of voltage V_Y1 or -V_Y1 by a per bit comparison with the display data, and the present embodiment can reduce the number of voltage levels applied to the column electrodes, specifically to two in the above embodiment, by always setting the number of mismatches between the display data pattern and the row select pattern to 1, 3, or some other odd number. Note that an even number of mismatches can be alternatively used.
Note also that while the above embodiment has been described for a gray scale display with four gradations, a display with a larger number of gradations is also possible. For example, eight gradations can be achieved by using 3-bit display data and subdividing each selection period or subperiod into three intervals the width of each weighted according to the position of a corresponding one of the display data bits. A display with 16 gradations can be achieved by using 4-bit display data and subdividing each selection period or subperiod into four correspondingly weighted intervals. Thus, different numbers of gradations of a gray scale display are possible by adapting the number of intervals each selection period or subperiod is subdivided into.

Embodiment 6

The above described fifth embodiment employs the type of voltage waveforms shown in Fig. 22 (bl. However, providing virtual row electrodes as in the fifth embodiment above to reduce the number of voltage levels applied to the column electrodes while also using pulse width modulation to achieve a gray scale display can also be applied to the case wherein the same type of row voltage waveforms as in the first embodiment is applied to the simultaneously selected row electrodes, and an example of this is shown in Fig. 14.
The voltage waveforms applied to the simultaneously selected row electrodes are the same as that of the first embodiment shown in Fig. 1, and each of the selection subperiods t₁ to t₄, t₅ to t₈ is subdivided into three intervals. When the display data for the pixels on the simultaneously selected row electrodes X₁, X₂, and X₃ are (00), (01), (10) as shown in Fig. 13, the data of the virtual row electrode may be (11) as shown in Fig. 8. The number of mismatches is then counted bit by bit in the same way as explained above to determine the voltage level, and either V_Y1 or -V_Y1 is applied as the voltage for the high bits in two of the three intervals and the voltage for the low bits in one interval.
It is thus possible to obtain the same effects as with the fifth embodiment.
It is to be noted that the selection subperiods t₁ to t₄ may be provided consecutively (forming one continuous selection period) or separately in each frame F. The same is true of selection subperiods t₅ to t₈.

Embodiment 7

In accordance with the present invention, driving a gray scale display by means of a so-called frame rate control modulation is performed in addition to dividing the selection period and reducing the number of applied voltage levels as described above, and Fig. 15 shows an embodiment wherein the number of voltage levels applied to the column electrodes is reduced using three sequential row electrodes and one virtual row electrode similarly to the sixth embodiment, the selection period is divided into plural separate subperiods each frame, and a gray scale display is achieved by means of frame rate control modulation.
Note that while the waveforms shown in Fig. 3 (b) are used as the voltage waveforms applied to the simultaneously selected row electrodes in this embodiment, the waveforms shown in Fig. 3 (a) or Fig. 22 (a) or (b) can also be used.
A gray scale display based on frame rate control modulation turns pixels ON in some frames and OFF in other frames during any given picture period, and in the example shown in Fig. 16, a gradation between on and off is displayed by applying an ON voltage during one frame F1 and an OFF voltage during another frame F2 assuming a picture period comprising two frames.
In this embodiment, the brightness difference between frames F1 and F2 is reduced and flicker becomes less noticeable because the selection period is divided into four separate subperiods each frame.
For example, in a gray scale display using plural frame periods as one block or picture period, the position of the selection pulses, i.e. the row select pattern, can be changed within the plural frames, and the difference between frames can be reduced by interchanging the row select patterns of subperiods t₃ and t₇, for example, in Fig. 15.
While a gray scale display is achieved by turning pixels ON in one of two frames and OFF in the other frame in the above embodiment, a picture period may be defined to have a block of more frames, for example 7 (15) frames, to achieve 8 (16) gradations by changing the number of ON and OFF frames within the block. Thus, a display with the desired number of gradations is possible depending on the number of frames of one block.

Embodiment 8

In accordance with the present invention, driving a gray scale display by means of frame rate control modulation is also possible in addition to dividing the selection period into separate subperiods and reducing the number of applied voltage levels as in the fifth embodiment above, and Fig. 17 shows an embodiment in which the number of voltage levels applied to the column electrodes is reduced using three sequential row electrodes and one virtual row electrode similarly to the fifth embodiment the selection period is divided into plural subperiods each frame, and a gray scale display is achieved by means of frame rate control modulation in combination with pulse width control.
By displaying plural gradations during plural frame periods with in a given picture period, intermediate gradations between the gradations of the plural frames can be displayed.
For example, by displaying (00) during the first frame F1 period of a 2-frame picture period and (01) during the next frame F2 period as shown in Fig. 18, a gradation actually between (00) and (01) can be displayed.
Display flicker can be reduced and a multiple gray scale display can be achieved by thus dividing the selection period and reducing the number of applied voltage levels, and combining pulse width modulation with frame rate control modulation for the gray scale display. Note also that the order of the row select patterns can be changed as in the sixth embodiment above.
While the fifth to eighth embodiments above have been described assuming the use of a virtual row electrode, it should be noted that a gray scale display can still be achieved by means of frame rate control modulation or by a combination of frame rate control modulation and pulse width modulation even when no virtual row electrode is used.

Claims

A method of multiplex driving a matrix type liquid crystal electro-optical device comprising a liquid crystal layer provided between a first substrate carrying row electrodes (X1, X2,...) and a second substrate carrying column electrodes (Y₁, Y₂,...) said row and column electrodes defining a matrix of pixels, said method comprising:

dividing said row electrodes into groups (X₁, X₂, X₃; X₄, X₅, X₆; X₁, X₂, X₃, X_n+1; X₄, X₅, X₆, X_n+2)

simultaneously selecting, during a selection period, the row electrodes of one group by applying a respective row voltage waveform to each of them while applying a non-selection voltage to the row electrodes of all other groups, and sequentially selecting each group, wherein said row voltage waveforms are composed of a plurality of row select pulses defining a corresponding plurality of row select patterns, and

applying a respective column voltage to each column electrode said column voltage determined in response to each row select pattern and display data,

characterized in that

said selection period is divided into plural subperiods (t₁ - t₈) and, when a frame is defined as the time period equal to said selection period times the number of row electrode groups and a picture period comprises a certain number of frames, said column voltages are modulated during said picture period such as to obtain a gray scale display.
The method according to claim 1 wherein said subperiods (t₁ - t₈) of each selection period form a continuous period.
The method according to claim 1, wherein said subperiods are separated in time such that when the groups of row electrodes (X₁, X₂, X₃; X₄, X₅, X₆; X₁, X₂, X₃, X_n+1; X₄, X₅, X₆, X_n+2) are sequentially selected, each is selected for the duration of a subperiod, this being repeated for each of the other subperiods.
The method according to any one of the preceding claims wherein each group of simultaneously selected row electrodes (X1, X2,...) comprises at least one virtual row electrode (X_n+1)and the display state of imaginary pixels corresponding to the virtual row electrode is set in accordance with the row select pattern and the display data corresponding to the real row electrodes such as to reduce the number of required column voltage levels.
The method according to any one of the preceding claims wherein the order of said row select patterns is changed among the groups within each frame or is changed among the frames.
The method of claim according to any one of the preceding claims wherein the polarity of the voltages applied to the row electrodes (X1, X2,...) and to the column electrodes (Y₁, Y₂,...) is reversed every frame or within each frame.