EP0598913A1

EP0598913A1 - Method and circuit for driving liquid crystal device, etc., and display device

Info

Publication number: EP0598913A1
Application number: EP93911979A
Authority: EP
Inventors: Akihiko Seiko Epson Corporation Ito; Shoichi Seiko Epson Corporation Iino
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 1992-05-08
Filing date: 1993-05-10
Publication date: 1994-06-01
Anticipated expiration: 2013-05-10
Also published as: EP0598913A4; EP0598913B1; DE69326740T2; TW280874B; DE69331812D1; EP0836173A2; WO1993023844A1; EP0836173A3; DE69326740D1; JP3508115B2; DE69331812T2; EP0836173B1; JP3391334B2; JP2000347163A

Abstract

In a method of driving a liquid crystal device, etc., and a display device, particularly those for gradation dispaly, the present invention aims at providing a driving method of a liquid crystal device, etc., and a display device capable of satisfactorily effecting gradation display without causing insufficient contrast, flickers, cross-talk, etc. When effecting multiplex driving of a liquid crystal device, etc., having a liquid crystal layer sandwiched between a substrate having scanning electrodes X₁, X₂,... and a substrate having signal electrodes X₁, Y₂,..., the present invention simultaneously selects sequentially a plurality of scanning electrodes, divides the selection period into a plurality of periods, and applies a weighted voltage, which is weighted in accordance with desired display data, in each of the divided selection periods so as to effect gradation display.

Description

[Field of the invention]

The present invention relates to a drive method, drive circuit, and display apparatus for liquid crystal cells in a liquid crystal display panel, for example.

[Description of the prior art]

Multiplex driving based on the amplitude selective addressing scheme is one known drive method for liquid crystal cells as described above.

(Prior art example 1)

Fig. 45 is an applied voltage waveform diagram showing one example of a prior art drive method for multiplex driving liquid crystal elements in a simple matrix as shown in Fig. 46 by means of an amplitude selective addressing scheme; Fig. 45 (a) and (b) are the voltage waveforms applied to row electrodes X₁, X₂, respectively, Fig. 45 (c) is the voltage waveform applied to column electrode Y₁, and Fig. 45 (d) is the voltage waveform applied to the pixel at the intersection of row electrode X₁ and column electrode Y₁.
This example sequentially selects row electrodes X₁, X₂ ... X_n one line at a time, and depending whether each pixel on the selected row electrode is ON or OFF applies a corresponding column voltage waveform is applied to each of the column electrodes Y₁, Y₂ ... Y_m to drive.
When the display is driven by selecting one row electrode at a time as described above, however, a good display cannot be obtained without using a relatively high drive voltage.

(Prior art example 2)

As a means of reducing the drive voltage, a method for simultaneously selecting a plurality of row electrodes at one time and in sequence and drives has been previously proposed (see A Generalized Addressing Technique for RMS Responding Matrix LCDs, 1988 International Display Research Conference, pp. 80 ∼ 85).
Fig. 47 is an applied voltage waveform showing an example of the prior art drive method for simultaneously selecting and driving sequentially plural row electrodes, Fig. 47 (a) being the row voltage waveform applied to the row electrodes X₁, X₂, and X₃, (b) the row voltage waveform applied to row electrodes row electrodes X₄, X₅, and X₆, (c) being the column voltage waveform applied to column electrode Y₁, and (d) being the voltage waveform applied to the pixel at the intersection of row electrode X₁ and column electrode Y₁.
This example simultaneously selects the row electrodes three sequential lines at a time for a display as shown in Fig. 46. Specifically, three row electrodes X₁, X₂, and X₃ are first selected, a row voltage as shown in Fig. 47 (a) is applied to these row electrodes X₁, X₂, and X₃, and a specified column electrode is simultaneously applied to each of the column electrodes Y1 ∼ Y_m as described later below. Next, row electrodes X₄, X₅, and X₆ in Fig. 46 are selected and a row voltage such as shown in Fig. 47 (b) is applied as described above, and a column voltage is simultaneously applied to each of the column electrodes Y₁ ∼ Y_m. One frame is completed when all row electrodes X₁ ∼ X_n are selected, and this operation is then repeated.
If the number of simultaneously selected row electrodes in this method is h, then 2^h row select patterns are used for the row electrode voltage waveforms. In this example, h = 3, so 2^h = 2³ = 8 row select pattern waveforms are used.
The voltage on/off patterns applied to the three simultaneously selected row electrodes X₁, X₂, and X₃ are shown in the following table using values of 1 and 0 for on and off pixel states, respectively.

X₁ 0 0 0 0 1 1 1 1

X₂ 0 0 1 1 0 0 1 1

X₃ 0 1 0 1 0 1 0 1
The voltage waveforms generated based on these values for application to the row electrodes are shown in Fig. 48 (a). The waveform shown in Fig. 48 (a), however, contains dispersions in the frequency component, which can result in display ununiformity when applied.
The waveform modified by reordering the array to eliminate the bias in the frequency component is shown in Fig. 48 (b). The prior art example shown in Fig. 47 also uses this waveform.
However, the column voltages applied to each of the column electrodes Y₁ ∼ Y_m have the same number of row select patterns as the row voltages, and the voltage level of each pulse applies a voltage with a value corresponding to the on/off states of the selected row electrodes. In this case, for example, an ON state is when the row voltage waveform applied to the simultaneously selected row electrodes X₁, X₂, and X₃ is a positive pulse and an OFF state is when a negative pulse, the ON/OFF states of the display data are compared bit by bit, and the level of the column voltage waveform is set according to the number of mismatches.
In other words, in Fig. 47, pulse voltages -V_Y2, -V_Y1, V_Y1, and V_Y2 are applied when the number of mismatches is 0, 1, 2, and 3, respectively. Note that the voltage ratio of V_Y1 to V_Y2 is V_Y1:V_Y2 = 1:3.
Specifically, if V_X1 is the voltage when the pixel is ON and -V_X1 is the voltage when OFF in the voltage waveform applied to row electrodes X₁, X₂, and X₃ in Fig. 47, and ON and OFF pixels are represented with a solid and white dot, respectively, in Fig. 46, the pixels at the intersection of row electrodes X₁, X₂, and X₃ and column electrode Y₁ are ON-ON-OFF, respectively, and the initial row select pattern of the voltage applied to these row electrodes X₁, X₂, and X₃ is OFF-OFF-OFF. Because the number of mismatches is two comparing these both in sequence, voltage V_Y1 as shown in Fig. 47 (c) is applied as the first row select pattern for the column electrode Y₁.
The second row select pattern of the voltage applied to the row electrodes X₁, X₂, and X₃ is OFF-OFF-ON; because each of these is a mismatch when compared sequentially with the previous ON-ON-OFF pixel display and the number of mismatches is therefore three, voltage V_Y2 is applied as the second pulse to column electrode Y₁. Similarly, V_Y1 is applied as the third pulse, -V_Y1 as the fourth pulse, and the following pulses are, in sequence, -V_Y2, V_Y1, - V_Y1, -V_Y1.
The next three row electrodes X₄ ∼ X₆ are then selected, and when the voltage shown in Fig. 47 (b)is applied to these row electrodes X₄ ∼ X₆, a column voltage of the voltage level corresponding to the number of mismatches between the on/off states of the pixels at the intersections of row electrodes X₄ ∼ X₆ and the column electrode and the on/off states of the voltage row select patterns applied to the row electrodes X₄ ∼ X₆ as shown in Fig. 47 (c) is applied.
Note that while the values 1 and -1 are used for the positive and negative selection pulses of the row voltage waveform, and -1 and 1 are used for the ON and OFF display data states of pixel, respectively, and the column voltage waveform is set according to the difference between the number of matches and the number of mismatches, values of 1 or -1 can be used for either, and the column voltage waveform can be set using only the number of matches or the number of mismatches without calculating the difference between the number of matches or the number of mismatches.
As described above, this method of simultaneously selecting and driving plural sequential row electrodes can suppress the drive voltage while achieving the same on/off ratio as the single line selection method shown in Fig. 45.
The general conditions, summary, and procedure of this method of simultaneously selecting and driving plural sequential row electrodes are described in order below.

A. Conditions

(a) N row electrodes are divided into N/h subgroups.
(b) Each subgroup comprises h address lines.
(c) The column electrode at any given time comprises h bit words.
d_k*h+1, d_k*h+2 ...d_k*h+h; d_k*h+j = 0 or 1 where 0 ≦ k ≦ (N/h)-1 and k is the subgroup.
In other words, the display data for one column can be defined as
d₁, d₂, ... d_h subgroup 0
d_h+1, d_h+2, ... d_h+h subgroup 1
d_N-h+1, d_N-h+2, ... d_N-h+h subgroup N/h-1.
(d) The selected pattern of the row electrode is the h bit word pattern of cycle 2^h where
a_k*h+1, a_k*h+2 ... a_k*h+h; a_k*h+j = 0 or 1.

B. Summary

(1) One subgroup is simultaneously selected at one time.
(2) One h-bit word is selected as the selected pattern of the row electrode.
(3) The row voltage is -Vr for logic 0, +Vr for logic 1, and 0 V when not selected.
(4) The row electrodes and column electrode of the selected subgroup are compared bit by bit.
(5) The number of mismatches i between the row electrode and column electrode patterns is determined.
(6) The voltage applied to the column electrode is V_(i) where i is the number of mismatches. (One predetermined voltage is selected according to the number of mismatches.)
(7) Based on this method, the column voltages are determined (simultaneously and in parallel).
(8) The row and column voltages thus determined are applied to the display for the time duration Δt_o only (where Δt_o is the minimum pulse width).
(9) A new row electrode selection pattern is selected, steps (4) ∼ (6) are recalculated, and the next column voltage is determined. This voltage is also applied for Δt_o only.
(10) For one cycle, all 2^h row electrode selection patterns appear in each subgroup, subgroup N/h is selected, and the process ends.
1 cycle = Δt * 2^h * (N/h).

C. Analysis

The row electrode selection pattern when there are i mismatches is considered below.
The number of mismatches that differ by only i-bit(s) between an h-bit word length row electrode selection pattern and a data pattern of the same h-bit word length is equal to
_hC_i = {h!}/{i!(h-i)!} = Ci.
For example, if h = 3 and the row electrode selection pattern is (0,0,0), the following data pattern variations are possible.

No. of mismatches Data pattern (column electrode) Ci

i = 0 (0,0,0) 1 pattern

i = 1 (0,0,1) (0,1,0) (1,0,0) 3 patterns

i = 2 (1,1,0) (1,0,1) (0,1,1) 3 patterns

i = 3 (1,1,1) 1 pattern
The number of Ci is determined by the number of bits in one word, and not by the row electrode selection pattern.
The amplitude V_pixel of the momentary voltage applied to the pixel is defined as
V_pixel = (V_column - V_row) or (V_row - V_column)
where V_row is the row voltage and V_column is the column voltage.
If V_row = ±Vr
Vcolumn = V(i)
then
V_pixel = +Vr - V_(i) or -Vr - V_(i).
If V_row = ±Vr
Vcolumn = ±V(i)
then
V_pixel = Vr - V_(i), Vr + V_(i),-Vr - V_(i), or -Vr + V_(i).
In other words,
V_pixel= ¦Vr - V_(i)¦ or ¦Vr + V_(i)¦.
Thus, the specific amplitude applied to the pixel is
-(Vr + V_(i)) or (Vr - V_(i)) for the selected line, and
V_(i) for unselected lines.
(The result will be as described in the paper if V_(i) is bipolar.)
In general, it is preferable in terms of achieving a high selection ratio for the voltage applied to a given pixel to be as high as possible with ON pixels and as low as possible with OFF pixels. Thus,
when ON, ¦Vr + V_(i)¦ works favorably for ON pixels,
¦Vr - V_(i)¦ works unfavorably for ON pixels;
when OFF, ¦Vr - V_(i)¦ works favorably for OFF pixels,
¦Vr + V_(i)¦ works unfavorably for OFF pixels,
where "favorable" for ON pixels means to raise the effective voltage, and "unfavorably" for ON pixels means to work in the direction lowering the effective voltage.
The number of combinations selecting i from among h bits is
Ci = _hC_i = {h!} / {i!(h-i)!}
where if i is the number of mismatches, this is the number of cases in which i bits will be mismatches in a selection of h bits. Because the number of mismatches is i in each level, the total number of mismatches is
i·Ci.
Because these mismatches are distributed through h bits, the average number of mismatches Bi per pixel (per one bit) is
Bi = i · Ci/h (number/pixel).
In addition, if the column voltage V_(i) level increases with the increase in the number of mismatches, then
V_pixel = V_row - V_column
will decrease with the increase in the number of mismatches.
If a mismatch is considered to work unfavorably for the target ON pixel, the number of mismatches will provide the number of unfavorable voltages (column voltages).
Therefore, the number of unfavorable voltages per pixel (on average) is
Bi = i · Ci/h.
However, because i/h of Ci is unfavorable, the remainder, i.e.,
Ai = {(h-i)/h} · Ci
works favorably. In addition,
{(h-i)/h} · Ci + (i/h) · Ci = (h/h)Ci = Ci,
and
Ai = Ci - Bi = {(h-1)!}/{i · (h-i-1)!)
where h ≧ i + 1.
Summarizing the above, we obtain
V_ON(r,m,s) = {(S₁ + S₂ + S₃)/S₄]^1/2
V_OFF(r,m,s) = {(S₅ + S₆ + S₃)/S₄}^1/2
Note also that:
When plural sequentially row electrodes are simultaneously selected and driven as in prior art example (2) described above, however, the pulse width applied to the row electrodes and column electrode also narrows as the number of simultaneously selected row electrodes increases, and picture quality deteriorates as crosstalk increases due to waveform rounding. This problem is particularly noticeable when this drive method is applied to gray scale displays using pulse width modulation.
The object of the present invention is to provide a drive method, drive circuit, and display apparatus for liquid crystal elements, etc., capable of achieving a good gray scale display even when simultaneously selecting and driving plural sequentially row electrodes.

[Disclosure of the Invention]

A drive method for liquid crystal elements, etc., according to the present invention multiplex drives liquid crystal elements comprising a liquid crystal layer provided between a substrate comprising row electrodes and a substrate comprising column electrodes, and is characterized by dividing the selection period into plural periods, and applying a voltage weighted according to the desired display data in the divided selection periods to achieve a gray scale display.
By using the above drive method, there is little crosstalk, etc., generated and a good gray scale display can be achieved even when simultaneously selecting plural sequential row electrodes for multiplex drive.
A drive circuit for liquid crystal elements, etc., according to the present invention simultaneously selects plural sequential row electrodes to multiplex drive liquid crystal elements formed from a liquid crystal layer provided between a substrate comprising row electrodes and a substrate comprising column electrodes, and is characterized by calculating the selected pulse data generated by the scan data generating circuit and the display data pattern for plural simultaneously selected scan lines by means of an operating circuit, transferring the data based on the calculation result to the column electrode driver and simultaneously transferring the scan data to the row electrode driver to achieve a desired gray scale display.
By using a drive circuit thus comprised, the above gray scale display can be achieved simply and reliably.
A display apparatus according to the present invention simultaneously selects plural sequential row electrodes to multiplex drive liquid crystal elements formed from a liquid crystal layer provided between a substrate comprising row electrodes and a substrate comprising column electrodes, and is characterized by a drive circuit for calculating the selected pulse data generated by the row-select pattern generating circuit and the display data for plural simultaneously selected scan lines by means of an operating circuit, transferring the data based on the calculation result to the column electrode driver and simultaneously transferring the scan data to the row electrode driver, dividing the selection period into plural parts, and applying a weighted column voltage according to the desired display data by the drive circuit to the column electrodes in each of the divided selection periods to achieve a gray scale display, to obtain a desired display.
By means of this configuration, a display apparatus providing a good gray scale display with little chance of crosstalk being generated can be provided.

Brief Description Of The Drawings

Fig. 1 is an applied voltage waveform showing the first embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 2 is a diagram showing the display data and basic configuration of the liquid crystal elements, etc.,
Fig. 3 is a diagram used to describe the row voltage waveforms applied to the row electrodes,
Fig. 4 is a block diagram of a first embodiment of a drive circuit,
Fig. 5 is a block diagram of the row electrode driver,
Fig. 6 is a block diagram of the column electrode driver,
Fig. 7 is an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 8 is used to describe the display data and operation when driving using a virtual electrode,
Fig. 9 is an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 10 is used to describe a gray scale display achieved by means of pulse width modulation,
Fig. 11 is an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 12 is an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 13 is used to describe the display data and location of the virtual electrodes,
Fig. 14 is an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 15 is an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 16 is used to describe the display data and location of the virtual electrodes,
Fig. 17 is an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 18 is used to describe the display data and location of the virtual electrodes,
Fig. 19 is an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 20 is used to describe the voltage waveforms applied to the column electrodes in an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 21 shows an applied voltage waveform of an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 22 is used to describe the display data and location of the electrodes,
Fig. 23 shows a waveform of the voltage applied to the column electrodes in the above embodiment,
Fig. 24 shows an applied voltage waveform of an embodiment dividing the selection period in the above embodiment into plural parts for driving in a single frame,
Fig. 25 shows a waveform of the voltage applied to the column electrodes in the above embodiment,
Fig. 26 shows an applied voltage waveform of an alternative embodiment dividing the selection period in the previous embodiment into plural parts for driving in a single frame,
Fig. 27 shows an applied voltage waveform of an alternative embodiment dividing the selection period in the previous embodiment into plural parts for driving in a single frame,
Fig. 28 shows an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 29 shows an applied voltage waveform of an embodiment dividing the selection period in the above embodiment into plural parts for driving in a single frame,
Fig. 30 shows an applied voltage waveform of an alternative embodiment dividing the selection period in the previous embodiment into plural parts for driving in a single frame,
Fig. 31 shows an applied voltage waveform of an alternative embodiment dividing the selection period in the previous embodiment into plural parts for driving in a single frame,
Fig. 32 shows an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 33 is used to describe the display data and location of the electrodes,
Fig. 34 shows an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 35 shows an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 36 shows an applied voltage waveform of an embodiment dividing the selection period in the above embodiment into plural parts for driving in a single frame,
Fig. 37 shows an applied voltage waveform of an alternative embodiment dividing the selection period in the previous embodiment into plural parts for driving in a single frame,
Fig. 38 shows an applied voltage waveform of an alternative embodiment dividing the selection period in the previous embodiment into plural parts for driving in a single frame,
Fig. 39 shows an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 40 shows an applied voltage waveform of an embodiment dividing the selection period in the above embodiment into plural parts for driving in a single frame,
Fig. 41 shows an applied voltage waveform of an alternative embodiment dividing the selection period in the previous embodiment into plural parts for driving in a single frame,
Fig. 42 shows an applied voltage waveform of an alternative embodiment dividing the selection period in the previous embodiment into plural parts for driving in a single frame,
Fig. 43 shows an applied voltage waveform showing an alternative embodiment of a drive method for liquid crystal elements, etc., according to the present invention,
Fig. 44 shows an applied voltage waveform of an embodiment dividing the selection period in the above embodiment into plural parts for driving in a single frame,
Fig. 45 shows an applied voltage waveform of one prior art drive method for liquid crystal elements, etc.,
Fig. 46 is used to describe the display pattern,
Fig. 47 shows an applied voltage waveform of another prior art drive method for liquid crystal elements, etc.,
Fig. 48 is used to describe the voltage waveform applied to the row electrodes.

Description Of Preferred Embodiments

The preferred embodiments of a drive method, drive circuit, and display apparatus for liquid crystal elements and other display elements according to the invention are described below based on the preferred embodiments shown in the figures.

(Embodiment 1)

Fig. 1 is an applied voltage waveform used to describe the first embodiment of a liquid crystal element drive method according to the present invention, Fig. 1(a) being the voltage waveform applied to the row electrodes X₁, X₂, and X₃, (b) being the voltage waveform applied to row electrodes row electrodes X₄, X₅, and X₆, (c) being the voltage waveform applied to column electrode Y₁, and (d) being the voltage waveform applied to the pixel at the intersection of row electrode X₁ and column electrode Y₁.
The present embodiment simultaneously selects three sequential row electrodes to achieve the display as shown in Fig. 2.
While the waveforms shown in Fig. 48 (a) or (b) can be used as the voltage waveforms applied to the simultaneously selected row electrodes, a waveform as shown in Fig. 1 (a) is used in this embodiment.
The problem when a voltage waveform corresponding to the bit word patterns as shown in Fig. 48 (a) or (b) is used is that each pulse width becomes narrower. Particularly when the number of simultaneously selected row electrodes increases, there is an exponential increase in the number of bit word patterns and each pulse width necessarily becomes narrower, leading to possible rounding when the waveform is actually applied to a pixel, and even possibly to crosstalk due to so-called rounding. In this embodiment and in the embodiments achieving a gray scale display by pulse width modulation as described below, the pulse width narrows further, resulting in crosstalk.
In the present embodiment, therefore, the voltage waveforms applied to the row electrodes are set as described below so that the pulse width is wider.
The voltage waveforms applied to the row electrodes are decided based on the conditions that:

(1) each row electrode must be identifiable,
(2) the frequency components applied to the row electrodes must not differ significantly, and
(3) the AC characteristic must be maintained for one or plural frames.

In other words, the pattern of the applied voltage is appropriately determined from a natural binary, Walsh, Hadamard, or other systems of orthogonal functions considering the above conditions.
Of these conditions, the first is absolute. To satisfy this condition the voltage waveforms applied to each row electrode are generated so that the voltage waveforms applied to each of the row electrodes are orthogonal to each other.
The applied voltage waveforms shown in Figs. 3 (a) and (b) were determined considering the above conditions. The applied voltage waveforms in Fig. 3 (a) contain different frequency components where

X₁:: 4 * Δt_o
X₂:: 4 * Δt_o, 2 * Δt_o
X₃:: 2 * Δt_o.

The applied voltage waveforms in Fig. 3 (b) contain different frequency components where

X₁:: 4 * Δt_o, 2 * Δt_o
X₂:: 4 * Δt_o, 2 * Δt_o
X₃:: 6 * Δt _o 2 * Δt_o.

While the shortest pulse width in the waveforms shown in Fig. 48(a) and (b) is Δt_o, the narrowest pulse width in the waveforms in Fig. 3 (a) and (b) is 2Δt_o, an increase of two times. It is thus possible to reduce the effects of waveform rounding, decrease crosstalk, and increase the number of simultaneously selected row electrodes by increasing the pulse width.
It is to be noted that the waveforms shown in Fig. 3 (a) and (b) are one example and can be changed as appropriate, and that the row electrode selection sequence and sequence of the row select patterns applied to the row electrodes can also be changed using the properties of the systems of orthogonal functions.
The row voltage waveform shown in Fig. 1 (a) and (b) forms the voltage waveform applied to the three simultaneously selected row electrodes based on the waveform in Fig. 3 (b). In addition, in this embodiment, the selection period is divided and driven in four parts t₁, t₂, t₃, t₄ in one frame.
Each of the selection periods t₁, t₂, t₃, t₄ divided as described above is further divided into plural parts as shown in Fig. 1 (c), and in each of these divided periods a weighted voltage data is applied to the column electrodes Y1 ∼ Y_m to obtain a desired display.
In other words, in this embodiment, period t₁ is divided into two equal parts to form the two periods a and b, a column voltage specifically weighted for each bit based on the display data shown in Fig. 2 and expressing a four gray scale display with two bits in a binary format is applied during period a for the high bit and to period b for the low bit as shown in Fig. 1.
Specifically, if voltage V_X1 is applied to the row electrode in each ON state, -V_X1 is applied in each OFF state, and the display data value is 0 when OFF and 1 when ON, and the ON/OFF states of the simultaneously selected row electrodes and the ON/OFF state of the display data are compared bit by bit to calculate the number of mismatches, the voltages applied for the high bit when the number of mismatches is 3, 2, 1, and 0, respectively, are V_Y4, V_Y2, -V_Y2, and -V_Y4, the voltages applied for the low bit when the number of mismatches is 3, 2, 1, and 0, respectively, are V_Y3, V_Y1, -V_Y1, and -V_Y3. Note that the relationship between each of the voltage levels is
2 * V_Y1 = V_Y2
2 * V_Y3 = V_Y4
2 * V_Y1 = V_Y3 - V_Y1
2 * V_Y2 = V_Y4 - V_Y2.
For example, during period t₁ in Fig. 1 (c), the selected pulses applied to row electrodes X₁, X₂, and X₃ are ON, ON, OFF, respectively, the display data for the pixels at the intersections of column electrode Y₁ and row electrodes X₁, X₂, and X₃ are (00), (01), (10), and the high bits are OFF, OFF, ON. Comparison shows the number of mismatches is three, and voltage V_Y4 is therefore applied to the column electrode Y₁ in period a. The low bits are OFF, ON, OFF, the number of mismatches compared with the row electrodes is one, and voltage -V_Y1 is therefore applied in period b.
Thus, the display data on the row electrodes X₁, X₂, and X₃ is compared with the selected pulses applied to the row electrodes for each of the column electrodes Y1 ∼ Y_m, and a column voltage corresponding to the number of mismatches is applied.
Next, row electrodes X₄, X₅, and X₆ are simultaneously selected and the corresponding column electrode waveform is applied to the column electrodes. When the sequence of simultaneously selecting the row electrodes three lines at a time and applying the corresponding column electrode waveform to the column electrodes until all row electrodes X₁ ∼ X_n have been scanned is completed, the operation returns to the first group of row electrodes X₁, X₂, and X₃ and the specified voltages are sequentially applied following the above sequence in periods t₂, t₃, and t₄. When all row electrodes X₁ ∼ X_n have been scanned in each of the four periods t₁ ∼ t₄, the next frame is repeated. Note that the polarity of the applied voltage is reversed in each frame in this embodiment for so-called alternating current drive scheme.
A good gray scale display with minimal crosstalk can thus be achieved by driving as described above.
It is to be noted that the sequence of the row voltage waveforms applied to the row electrodes in the above periods t₁ ∼ t₄ can be changed for all frames or in single frames, and the waveforms shown in Fig. 3 (a) or other waveforms satisfying the conditions described above can be used as the row voltage waveforms applied to the row electrodes. Moreover, two waveforms can alternately used for each group of simultaneously selected row electrodes, for example using the waveform shown in Fig. 3 (a) for row electrodes X₁ ∼ X₃ and the waveform shown in Fig. 3 (b) for row electrodes X₄ ∼ X₆, or a sequence of three or more waveforms can be used alternately. In addition, it is also possible to combine reordering the waveforms in periods t₁ ∼ t₄ with reordering the waveforms for the groups of simultaneously selected row electrodes.
While the periods t₁ ∼ t₄ can be driven separately in each period as in the above embodiment, or can be driven consecutively in one frame, if the selection period is driven in plural parts within one frame as in the present embodiment, the unselected selection period becomes shorter and contrast can be improved. In this case, while the selection period is divided into four parts t₁ ∼ t₄ in the above embodiment, any number of divisions can be used; for example, periods t₁ ∼ t₄ can be divided and driven in two parts, or can be divided and driven in more than two parts.
In addition, row electrodes are selected three at a time in sequence of position in the above embodiment, but the number of the selected row elements is an appropriate number and the row electrode do not necessarily need to be selected in sequence of position.
The above changes can also be applied to the alternative embodiments described below.
A drive circuit executing the drive method described above is described based on Figs. 4 ∼ Fig. 6.
Fig. 4 is a block diagram showing one example of a drive circuit. In this figure 1 is the row electrode driver, 2 is the column electrode driver, 3 is the frame memory, 4 is an arithmetic operation circuit, 5 is the row data generating circuit, and 6 is a latch.
Fig. 5 is a block diagram of the row electrode driver, Fig. 6 is a block diagram of the column electrode driver, and in Fig. 5 and Fig. 6, 11 and 21 are shift registers, 12 and 22 are latches, 13 and 33 are decoders, and 14 and 24 are level shifters.
In this configuration, each row electrode waveform causes data indicating a positive selection, negative selection, or no selection to be generated from the row data generating circuit 5 and sent to the row electrode driver 1.
In the row electrode driver 1, as shown in Fig. 5, the scan data signal S3 from the row data generating circuit 5 is sent to the level shifter 11 at the scan shift clock signal S5, the data is latched at latch signal S6 after transferring the data for each of the row electrodes in one scanning period, the data expressing the state of each row electrode is decoded, one of three analog switches 15 for each output is set ON, and voltage V_X1, -V_X1, or 0 is selected and output to the row electrode when the selection is positive, negative, or no selection, respectively.
For the column electrode waveforms, the display data signal S1 for the three simultaneously selected lines X₁, X₂, and X₃ is read from frame memory 3, the selection pulse data is latched from the display data signal S1 and the scanning data signal S3, and the display data signal S1 and scanning data signal S3 are converted by the arithmetic operation circuit 4. This data conversion is performed as described above, and transferred to the column electrode driver 2.
In the column electrode driver 2, as shown in Fig. 6, the data signal S2 from the arithmetic operation circuit 4 is sent to level shifter 21 at shift clock signal S7, the data is latched at the latch signal S8 after the data is sent to each column electrode in one scanning period, the data expressing the state of each column electrode is decoded, one of the eight analog switches 25 for each output is set ON, and one of the eight voltages V_Y4, V_Y3, V_Y2, V_Y1, -V_Y1, -V_Y2, - V_Y3, and -V_Y4 is output to each column electrode.
A drive method as described above can thus be simply and reliably achieved by using a drive circuit as described above.
If a display apparatus comprising display elements as described above comprises a drive circuit as described above to execute the drive method as described above, a display apparatus capable of achieving a good gray scale display with minimal crosstalk generated can be achieved.

(Embodiment 2)

In the first embodiment one of four voltages is selected according to the display data and applied to the column electrodes for each bit of the display data, but by providing a virtual electrode the number of voltage levels applied to the column electrodes can be reduced.
Fig. 7 is a voltage waveform for an embodiment that drives by reducing the number of voltage levels applied to the column electrodes by providing a virtual electrode, and Fig. 8 illustrates the basis for reducing the number of voltage levels applied to the column electrodes by providing a virtual electrode.
This embodiment provides, for example, virtual electrodes X_n+1, X_n+2, ... after the simultaneously selected row electrodes as shown in Fig. 8 such that X_n+1, is simultaneously selected when row electrodes X₁, X₂, and X₃, for example are selected, and the number of mismatches is calculated as in the first embodiment assuming voltage V_X1 is applied to the row electrode in each ON state, -V_X1 is applied in each OFF state, and the display data value is 0 when OFF and 1 when ON. In this case, the number of mismatches is always 1 or 3 by appropriately changing the display state of the virtual electrode.
When the number of mismatches between the display data and the high bit is 1, -V_Y2 selected, and when the number of mismatches is 3, V_Y2 is selected; when the number of mismatches between the display data and the low bit is 1, -V_Y1 selected, and when the number of mismatches is 3, V_Y1 is selected. Note that the relationship between each of the voltage levels is 2 * V_Y1 = V_Y2.
The display shown in Fig. 2 is achieved by the waveforms in Fig. 7 applying the above principle. During period t₁, the selected pulses applied to row electrodes X₁, X₂, X₃ and virtual electrode X_n+1 are ON, ON, OFF, ON, respectively, the display data for the pixels at the intersections of column electrode Y₁ and row electrodes X₁, X₂, X₃ and virtual electrode X_n+1 are (00), (01), (10), (11), and the high bits are OFF, OFF, ON, ON. Sequential comparison shows the number of mismatches is three; conversion data S2 is therefore generated according to this number of mismatches, and voltage V_Y2 is therefore applied to the column electrode Y₁ in period a.
The low bits are OFF, ON, OFF, ON, the number of mismatches compared with the row electrodes is one, conversion data S2 is therefore generated according to this number of mismatches, and voltage -V_Y1 is therefore applied in period b.
Thus, the display data on the row electrodes X₁, X₂, X₃ and virtual electrode X_n+1 is compared with the selected pulses applied to the row electrodes for each of the column electrodes Y1 ∼ Y_m, and a column voltage corresponding to the number of mismatches is applied.
Next, row electrodes X₄, X₅, X₆ and X_n+2 are simultaneously selected and the corresponding column electrode waveform is applied to the column electrodes. When the sequence of simultaneously selecting the row electrodes three lines at a time plus one virtual electrode line and applying the corresponding column electrode waveform to the column electrodes until all row electrodes to X_n have been scanned is completed, the operation returns to the first group of row electrodes X₁, X₂, and X₃ and sequential scanning using the row select pattern shown in t₂ continues. One frame period is completed by scanning four times with the row select patterns shown in t₁, t₂, t₃, and t₄, and the same operation is repeated in the next frame.
By thus providing a virtual electrode as above, the number of voltage levels applied to the column electrodes can be made less than that of the first embodiment.
That the number of voltage levels applied to the column electrodes can be reduced by providing a virtual electrode as described above can also be applied to each of the embodiments described below.
In addition, the same drive circuit used in the first embodiment can be used in the present embodiment and each of the embodiments described below. In this case, the arithmetic operation circuit 4 in Fig. 4 is comprised to execute data processing according to each of the embodiments, the voltage levels of the row electrode driver in Fig. 5 and the column electrode driver in Fig. 6 are provided according to each embodiment, and one of the voltage levels is selected by analog switches 15, 25.
In this embodiment, for example, the arithmetic operation circuit 4 in Fig. 4 and the row electrode driver in Fig. 5 are the same as those of the first embodiment, but while eight voltage levels V_Y4, V_Y3, V_Y2, V_Y1 , -V_Y1, -V_Y2, -V_Y3, and -V_Y4 are provided in the column electrode driver of the first embodiment in Fig. 6, it is sufficient to provide four voltage levels V_Y2, V_Y1, -V_Y1, and -V_Y2 in the present embodiment.

(Embodiment 3)

The above embodiment achieves a gray scale display by changing the voltage value according to the display data, but a gray scale display can also be achieved by changing the pulse width.
Fig. 9 is an applied voltage waveform of an embodiment achieving a gray scale display by changing the pulse width.
The general procedure for achieving a gray scale display by means of pulse width modulation is described first.
In general, the period Δt of each pulse is divided into f periods of unequal duration to achieve a gray scale display by means of pulse width modulation.

${Δt}_{g} {= 2}^{g-1} {/ (2}^{f} - 1)$

where f is the bit number of gradations.
For example, if f = 2, there are 2² = 4 gradations, and the period is divided:

${Δt₁ = (1/3)Δt}_{o}$

${Δt₂ = (2/3)Δt}_{o}$

as shown in Fig. 10.
The data is then divided into f bits (expressed as f bits).

${d₁ = (d}_{1,f} {,d}_{1,f-1} {...d}_{1,1})$

${d₂ = (d}_{2,f} {,d}_{2,f-1} {...d}_{2,1})$

$d_{h} {= (d}_{b,f} {, d}_{h,f-l} {... d}_{h,l})$

Each bit of the row electrode selection patterns and the data patterns are then compared at an interval of Δt_g.
For example, when f = 2,

${d₁ = (d}_{1,2} {,d}_{1,1})$

${d₂ = (d}_{2,2} {,d}_{2,1})$

The low bit (d_1,1) of d₁ and the row electrode selection pattern are first compared, and applied to the display for period Δt₁.
Bit d_1,2 and the row electrode selection pattern are then compared, and applied to the display for period Δt₂.
This is sequentially repeated as above for each bit d.
Fig. 9 based on the present embodiment achieves a four gray scale display as shown in Fig. 2 using pulse width modulation as described above.
In this example, the row voltage applied to the row electrodes X₁ ∼ X_n is the same as in the prior art example illustrated in Fig. 47, and the pulse widths of the corresponding column electrodes Y₁ ∼ Y_m are modulated according to the gray scale display as above.
In other words, each pulse width Δt is divided into three equal parts, a gray scale display with four gradations 0 ∼ 3 is expressed using the 2-bit binary display data expressions (00), (01), (10), (11). The signal voltage level of two of the three pulse width parts is determined based on the number of mismatches between the on/off state of the simultaneously selected row electrodes and the high bit state of the display data. The signal voltage level of the remaining one part is determined based on the number of mismatches between the ON/OFF state of the row electrodes and the low bit state. Variations in the brightness of the gray scale display can also be corrected by equally reducing the three parts.
Specifically, if in Fig. 9 an ON state is achieved by applying voltage V_X1 to the row electrode and an OFF state by applying voltage -V_X1, the first pulse applied to the row electrodes X₁, X₂, and X₃ generates an OFF state for all three row electrodes. Because a low bit value of 0 indicates an OFF state and a low bit value of 1 an ON state in the display data for the row electrodes X₁, X₂, and X₃ in Fig. 2, the corresponding states are OFF, ON, OFF. The number of mismatches is therefore one, and the voltage pulse during period Δt₁ is -V_Y1. Because the high bit states are OFF, OFF, ON, the number of mismatches is one, and the voltage pulse during period Δt₂ is -V_Y1. It is thus sufficient to obtain the voltage pulse applied to the column electrodes by a comparison executed each selection period Δt.
In this embodiment, the voltage for the high bit is applied during the latter two of the three period divisions, and the voltage for the low bit is applied during the first of the three period divisions.

(Embodiment 4)

The selection period can also be divided into plural units each frame as described in the first embodiment above to drive a gray scale display.
An example of such application is shown in Fig. 11. The voltage waveforms of eight row select patterns (blocks) applied to the row electrodes and column electrodes in the embodiment shown in Fig. 9 are divided into eight equal intervals each row select pattern.
When the liquid crystal elements are driven by dividing the selection period into plural parts in one frame as described above, the contrast can be improved as in the previous embodiment.

(Embodiment 5)

The four voltage levels V_Y2, V_Y1, -V_Y1, and -V_Y2 are used as the column electrode voltage levels in the third and fourth embodiments above, but this number of voltage levels can be further reduced by providing a virtual electrode as in the second embodiment.
Fig. 12 shows an example that provides a virtual electrode in the third embodiment to reduce the number of voltage levels applied to the column electrode, and is driven by dividing the selection period in to plural parts within one frame as in the fourth embodiment.
Reducing the number of voltage levels by providing a virtual electrode as described above has already been described in the second embodiment, but is described further below, including the general methodology.
First, of the h row electrodes in each subgroup, e column electrodes are operated as virtual row electrodes (virtual lines). By controlling the data matching/mismatching of these virtual row electrodes, the overall number of matches/mismatches can be controlled, and the number of drive voltage levels for the column electrodes can be reduced.
If the number of mismatches is Mi and Vc is an appropriate constant, the voltage V_column applied to the column electrode is defined as

or simply
V_column= V_(i)
where 0 ≦ i ≦ h.
In any event, V_column is h + 1 levels.
The case where the number of subgroups h = 4 and the number of virtual row electrodes - e = 1 is considered by way of example below.

As in the previous embodiment, the number of levels when h = 3 is four (-V_Y2, -V_Y1, V_Y1, V_Y2). If the number of mismatches is controlled using the virtual row electrodes to be an even number, the resulting voltage levels are shown in the following table.

Original voltage level	Original number of mismatches	Virtual row electrode	Number of mismatches after correction	Voltage level after correction
-V _Y2	0	Match	0	Va
-V _Y1	1	Mismatch	2	Vb
V
_Y1	2	Match	2	Vb
V
_Y2	3	Mismatch	4	Vd

As shown in the above table, the original four voltage levels can be reduced to three. If the number of mismatches is controlled to be odd, the number of mismatches after correction will change in the above table to 1, 1, 3, 3 (from the top), and there will be only two voltage levels (Va, Va, Vb, Vb from the top) after correction.

If the number of subgroups h = 4 and the number of unreduced voltage levels is therefore five (-V_Y2, -V_Y1, 0, V_Y1, V_Y2) , controlling the number of mismatches to be an even number using the virtual row electrodes results in the voltage levels shown in the following table.

Voltage levels before reduction	Number of mismatches before reduction	Virtual line	Number of mismatches after correction	Voltage level after correction
-V _Y2	0	Match	0	Va
-V _Y1	1	Mismatch	2	Vb
0	2	Match	2	Vb
V
_Y1	3	Mismatch	4	Vd
V
_Y2	4	Match	4	Vd

The original number of voltage levels can thus be reduced from five to three. Note that the voltage levels can also be set by controlling the number of mismatches to be odd.
It is not always necessary to provide these virtual row electrodes because they are not normally displayed. When they are provided, however, the virtual row electrodes can be provided in an area not affecting the display. When provided in a liquid crystal display, for example, the virtual row electrodes X_n+1 ... are provided outside the display area R as shown in Fig. 13. Alternatively, any extra row electrodes outside the normal display area R can also be used as virtual row electrodes.
The number of voltage levels can be further reduced by increasing the number e of virtual row electrodes. In the above example the number of mismatches is controlled to be divisible by two when e = 1, but if e = 2, the same result can be obtained by controlling the number of mismatches to be divisible by three. It is also possible to divide by three to leave a remainder of one or two.
The maximum reduction possible with the above method is 1/(e + 1), or 1/2 when e = 1 (except for 0 V).
The present embodiment as shown in Fig. 12 simultaneously selects three row electrodes and one virtual electrode to reduce the number of voltage levels applied to the column electrodes, and drives by dividing the selection period into plural parts in one frame.
As shown in Fig. 12 and Fig. 14, the present embodiment divides the selection period into four parts in one frame, and the number of mismatches with the display data is counted bit by bit for four row electrodes, including the virtual row electrode, in each of the four partial periods to adjust the number of mismatches to an odd number. The number of mismatches is thus either 1 or 3, and the voltage level of the column voltage waveform is therefore one of two levels, V_Y1 or -V_Y1.
Considering the display shown in Fig. 13, the virtual row electrode X_n+1, follows after the first three selected row electrodes X₁, X₂, and X₃ as shown in Fig. 8. Note that it is not essential for the virtual row electrode to be previously provided, but that when it is the virtual row electrode is preferably provided outside the display area R.
If a positive voltage applied to the row electrode is ON and a negative voltage is OFF, each of the selection periods Δt is divided into three parts, and the display data on the simultaneously selected row electrodes X₁, X₂, and X₃ is (00), (01), (10) as shown in Fig. 13, the data for the virtual row electrode is (11) as shown in Fig. 8.
The number of mismatches is then counted bit by bit to determine either voltage level V_Y1 or -V_Y1, and the voltages for the high bits are applied for the latter two of the three period divisions and the voltage for the low bit is applied for the first one period division. Note that, as in the third embodiment, it is also possible to apply the voltage for the high bit in the first two period divisions and to apply the voltage for the low bit in the last one period division.
It is therefore sufficient to determine the pulse width of voltage V_Y1 or -V_Y1 by a per bit comparison with the display data, and the present embodiment can reduce the number of voltage levels applied to the column electrodes, specifically to two in the above embodiment, by always setting the number of mismatches between the display data and the row select pattern of the selected pulse applied to the virtual row electrode to 1, 3, or some other odd number. Note that an even number of mismatches can be alternatively used.
Note also that while the above embodiment has been described for a four gray scale display, a display with a larger number of gradations is also possible. For example, an eight gray scale display can be achieved by using 3-bit display data and dividing each selection period into three parts weighted to the pulse width of each display data bit. A display with 16 gradations can be achieved by using 4-bit display data and dividing each selection period into four parts weighted to the pulse width of each display data bit. Thus, a gray scale display is possible by changing the number of divisions each selection period is divided into.

(Embodiment 6)

Providing a virtual electrode as in the fifth embodiment above to reduce the number of voltage levels applied to the column electrodes while also using pulse width modulation to achieve a gray scale display can also be applied to the case wherein a row voltage as in the first embodiment is applied to the simultaneously selected row electrodes, and an example of this is shown in Fig. 14.
The voltage waveform applied to the simultaneously selected row electrodes is the same as that of the first embodiment shown in Fig. 1 as above, each of the selection periods t₁ ∼ t₄, t₅ ∼ t₈ is divided into three parts, and when the display data of the simultaneously selected row electrodes X₁, X₂, and X₃ is (00), (01), (10) as shown in Fig. 13, it is sufficient for the data of the virtual electrode to be (11) as shown in Fig. 8.
The number of mismatches is then counted bit by bit to determine the voltage level, and either V_Y1 or -V_Y1 is applied as the voltage for the high bit in two of the three period divisions and the voltage for the low bit in one period division.
It is thus possible to obtain the same effects as with the fifth embodiment.
It is to be noted that the selection periods t₁ ∼ t₄ may be provided consecutively in one frame F, or separately in one frame F. The same is true of selection periods t₅ ∼ t₈.

(Embodiment 7)

Driving a gray scale display by means of frame rate control is also possible after dividing the selection period and reducing the number of applied voltage levels as described above, and Fig. 15 shows an embodiment whereby the number of voltage levels applied to the column electrodes is reduced using three sequential row electrodes and one virtual row electrode similarly to the sixth embodiment, and drives the display by dividing the selection period into plural parts within one frame, achieving a gray scale display by means of frame rate control modulation.
Note that while the waveform shown in Fig. 3 (b) is used as the voltage waveform applied to the simultaneously selected row electrodes in this embodiment, the waveform shown in Fig. 3 (a) or Fig. 48 (a) or (b) can also be used.
A gray scale display based on frame rate control modulation turns some frames on and some frames off during any given frame period, and in the example shown in Fig. 16, a gradation between on and off is displayed by applying an ON voltage during F1 and an OFF voltage during F2.
In this embodiment, the brightness difference between F1 and F2 is also reduced and flicker becomes less noticeable because the fields are selected four times during one frame.
For example, in a gray scale display using plural frame periods as one block, the position of the selection pulse can be changed within the plural frames, and the difference between frames can be reduced by interchanging periods t₃ and t₇, for example, in Fig. 15.
While a gray scale display was achieved by turning one of two frames ON and one frame OFF in the above embodiment, more frames, for example 7 frames, can be grouped in one block to achieve an 8 gray scale display by changing the number of ON and OFF frames within the block, or 15 frames can be grouped in one block to achieve a 16. Thus, a display with the desired number of gradations is possible depending on the number of frames of one block.

(Embodiment 8)

Driving a gray scale display by means of frame rate control modulation is also possible after dividing the selection period and reducing the number of applied voltage levels as in the fifth embodiment above, and Fig. 13 shows an embodiment whereby the number of voltage levels applied to the column electrodes is reduced using three sequential row electrodes and one virtual row electrode similarly to the fifth embodiment, and drives the display by dividing the selection period into plural parts within one frame, achieving a gray scale display by means of frame rate control modulation.
By displaying plural gradations during plural frame periods, gradations between the gradations of the plural frames can be displayed.
For example, by displaying (00) during the first frame F1 period and (01) during the next frame F2 period as shown in Fig. 18, a gradation actually between (00) and (01) can be displayed.
Display flicker can be reduced and a multiple gray scale display can be achieved by thus dividing the selection period and reducing the number of applied voltage levels, and combining pulse width modulation with frame rate control modulation for the gray scale display. Note also that the order of the selection pulses can be changed as in the sixth embodiment above.
While the fifth to eighth embodiments above have been described assuming the use of a virtual row electrode, it should be noted that a gray scale display can still be achieved by means of frame rate control modulation or by a combination of frame rate control modulation and pulse width modulation even when a virtual row electrode is not provided.

(Embodiment 9)

Each of the above embodiments have been described as achieving a four gray scale display by applying a column voltage weighted according to each bit of 2-bit display data, but it is possible to drive other numbers of gradations. For example, an eight gray scale display can be obtained using a column electrode waveform as shown in Fig. 19.
In other words, Fig. 19 is the column electrode waveform when the display data for the pixels at the intersection of the row electrodes X₁, X₂, and X₃ and column electrode Y₁ are (001), (010), (100) and the row electrode waveform applied to each of the row electrodes in Fig. 2 is the same as that of the first embodiment.
In this embodiment, the four selection periods t₁ ∼ t₄ in the first embodiment are each divided into three equal periods a, b, c, and the voltage waveform corresponding to the highest of the three display data bits is applied in the first period division a, the voltage waveform corresponding to the middle bit is applied in the next period division b, and the voltage waveform corresponding to the lowest bit is applied in the last period division c; each of these voltage waveforms is weighted according to each of the display data bits as in the first embodiment.
Specifically, one of the voltages -V_Y6, -V_Y4, V_Y4, or V_Y6 is selected for period a according to the highest display data bit, one of the voltages -V_Y5, -V_Y2, V_Y2, or V_Y5 is selected for period b according to the middle display data bit, and one of the voltages -V_Y3, -V_Y1, V_Y3, or V_Y1 is selected for period c according to the lowest display data bit. The relationship between each of the voltage levels is defined as
4 * V_Y1 = 2 * V_Y2 = V_Y4
4 * V_Y3 = 2 * V_Y5 = V_Y6
2 * V_Y1 = V_Y3 - V_Y1
2 * V_Y2 = V_Y5 - V_Y2
2 * V_Y4 = V_Y6 - V_Y4.
Under these conditions, an eight gray scale display can be achieved as in the first embodiment by generating the column electrode waveform based on the number of mismatches in each bit of the display data.
As described above, a four gray scale display is obtained in the first embodiment by selecting a voltage for each of the two equal periods into which the selection period is divided, and applying this voltage to the column electrode, but in the present embodiment an eight gray scale display is obtained by dividing the selection period into three equal parts. In addition, a sixteen gray scale display can be obtained by dividing the selection period into four equal parts, and as this indicates, the number of gradations can be increased by appropriately dividing the selection period into plural parts and applying a voltage selected for each of these parts to the column electrode. The brightness level of each gradation can also be adjusted by changing the voltage ratio applied to each column electrode, or by slightly changing the duration of each part into which the selection period is divided instead of using equal parts.

(Embodiment 10)

In a gray scale display obtained by changing the voltages applied to the column electrodes as shown in Fig. 19 of the ninth embodiment above, a voltage is applied according to each bit in sequence from the high bit in the periods a, b, c, divided according to the number of display data bits, but this sequence can be appropriately changed for each column electrode.
If, for example, in the ninth embodiment above the display of the pixels at the intersections of row electrodes X₁, X₂, and X₃ and column electrodes Y₂ ∼ Y_m are the same as the display of the pixels at the intersections of row electrodes X₁, X₂, and X₃ and column electrode Y₁, the column voltage waveforms applied to the column electrodes Y1 ∼ Y_m will all be identical to the waveforms shown in Fig. 19. However, rounding of the waveform applied to each pixel becomes great in this case, and display quality deteriorates.
The order of the column electrode waveforms applied to each of the column electrodes Y₁ ∼ Y_m is thus changed in this embodiment as shown in Fig. 20.
In other words, in the ninth embodiment the voltage corresponding to the highest of the three display data bits is applied in sequence to column electrode Y₁ during period a in Fig. 20, the voltage corresponding to the middle bit during period b, and the voltage corresponding to the lowest bit during period c. The same is true of the other column electrodes Y₁ ∼ Y_m.
In the present invention as shown in Fig. 20, however, if the period in which the voltage corresponding to the highest bit is applied is a, the period in which the voltage corresponding to the middle bit is applied is b, and the period in which the voltage corresponding to the lowest bit is applied is c, and the voltages are applied to column electrode Y₁ in the order (a, b, c) in sequence from the highest bit as in the second embodiment, the order is changed for the next column electrode, for example to (a, c, b) for column electrode Y₂, (b, a, c) for column electrode Y₃, (b, c, a) for column electrode Y₄, (c, a, b) for column electrode Y₅, and (c, b, a) for column electrode Y₆, and similar combinations are repeated for Y₇ ∼ Y_m.
If this method is applied, the effects of rounding rises and falls of column electrode waveform cancel each other out, and rounding of the waveforms applied to each pixel can be reduced because waveforms in six different order combinations are applied in essentially the same number to the column electrodes,
It is to be noted that any combination of waveforms applied to the column electrodes can used such that, for example, if there are six column electrode drivers, each combination of waveforms is applied to each column electrode driver. Thus, display quality can be improved if the number of rounding rises and falls cancel each other in the combination of waveforms applied to the respective column electrodeds.
Furthermore, changing the order of the voltages corresponding to each bit of display data for each of the column electrodes Y₁ ∼ Y_m as described above can also be applied to the various embodiments described hereinbefore and below.

(Embodiment 11)

In the ninth embodiment an eight gray scale display is obtained using a waveform as shown in Fig. 1(a), i.e., as shown in Fig. 3 (b), as the row voltage waveform applied to the row electrodes, but the waveform shown in Fig. 3 (a) or in the Fig. 48 (a) or (b) for the prior art method can also be used. The case wherein the waveform shown in Fig. 3 (a) is used for an eight gray scale display is described in further detail below.
Fig. 21 is an applied voltage waveform of the embodiment achieving an eight gray scale display based on the display data shown in Fig. 22 and using the waveform shown in Fig. 3 (a) as the row voltage waveform applied to the row electrodes. Fig. 21 (a) shows the row voltage waveform applied to row electrodes X₁, X₂, and X₃, Fig. 21 (c) is the column voltage waveform applied to column electrode Y₁, and Fig.21 (d) is the voltage waveform applied to the pixels at the intersection of row electrode X₁ and column electrode Y₁.
This embodiment also simultaneously selects three sequential row electrodes, and while only the three row electrodes X₁, X₂, and X₃ are shown in Fig. 21, the next three row electrodes X₄, X₅, and X₆ are selected after row electrodes X₁, X₂, and X₃ are selected as shown in Fig. 23, and a voltage is applied to these electrodes similarly to row electrodes X₁, X₂, and X₃. Thereafter, the row electrodes are selected in order three at a time, and one frame ends when all row electrodes have been selected.
By thus applying a row voltage waveform as shown in Fig. 3 (a) to the three simultaneously selected row electrodes, the minimum pulse width Δt is twice the minimum pulse width Δt_o of the prior art method shown in Fig. 48 as described above, and all selection periods t for each of the row electrodes in one frame comprise four periods t₁ ∼ t₄ of the size of pulse width Δt.
The above four periods t₁ ∼ t₄ are each divided into three periods a, b, c according to the number of bits of display data, and a column voltage specifically weighted according to the bits of the display data is applied to the column electrode in each of these period divisions.
Specifically, the high bit of the display data, which is expressed as a three digit binary number as shown in Fig. 22, corresponds to the first period division a of each period t₁ ∼ t₄, the middle bit corresponds to the next period division b, and the low bit corresponds to the last period division c, and the specifically weighted voltage ±V_Y4 or ±V_Y6 is applied according to the conditions described below for the high bit ±V_Y2 or ±V_Y5 is applied for the middle bit, and ±V_Y1 or ±V_Y3 is applied for the low bit.
It is to be noted that the ratio of the above voltage values is defined as:
V_Y1 : V_Y2 : V_Y4 = 1: 2 : 4
V_Y3 : V_Y5 : V_Y6 = 1 : 2 : 4
V_Y1 : V_Y3 = 1 : 3.
As the conditions for the above, ON is when the voltage waveform of the row electrode is positive and OFF is when negative, and a display data value of 1 is ON and 0 is OFF; the on/of state of the simultaneously selected row electrodes and the on/off state of the corresponding display data bit at the intersection of the selected row electrode and the column electrode to which the voltage is to be applied are compared for each bit position, and a voltage specified according to the number of mismatches is applied to the column electrode.
Specifically, when the number of mismatches between the row electrode and the high bit is 0, 1, 2, or 3, voltage value -V_Y6, -V_Y4, V_Y4, or V_Y6, respectively, is applied in this embodiment; when the number of mismatches between the row electrode and the middle bit is 0, 1, 2, or 3, voltage value -V_Y5, -V_Y2, V_Y2, or V_Y5, respectively, is applied; and when the number of mismatches between the row electrode and the low bit is 0, 1, 2, or 3, voltage value -V_Y3, -V_Y1, V_Y1, or V_Y3, respectively, is applied.
Therefore, in the embodiment in Fig. 21, the three row electrodes X₁, X₂, and X₃ are first selected, the selected row electrodes X₁, X₂, and X₃ are OFF, OFF, ON, respectively, and the high bits of the display data at the intersection of the column electrode Y₁ and these row electrodes X₁, X₂, and X₃ are OFF, ON, ON. Comparing both, the number of mismatches is 1, and the voltage -V_Y4 is applied to column electrode Y₁ in the first period division a of the first period t₁. A weighted voltage is simultaneously applied to the other column electrodes Y₂ ∼ Y_m in the same manner.
Next, during the next period division b of the first period t₁, the on/off state of row electrodes X₁, X₂, and X₃ is the same OFF, OFF, ON, and the middle bits corresponding to this period division b are, in order, ON, OFF, OFF; the number of mismatches is therefore 2, and voltage V_Y2 is applied. The low bits corresponding to the last period division c are OFF, ON, OFF; the number of mismatches is therefore 2, and voltage V_Y1 is applied.
During the next period t₂, the voltages -V_Y4, V_Y2, and -V_Y3, respectively, are applied to the column electrode Y₁ during period divisions a, b, c because the on/off states of row electrodes X₁, X₂, and X₃ are OFF, ON, OFF, the high bits of the display data at the intersection of the column electrode Y₁ and these row electrodes X₁, X₂, and X₃ are OFF, ON, ON, respectively, and the number of mismatches is 1 as described above, the middle bits are ON, OFF, OFF and the number of mismatches is 2, and the low bits are OFF, ON, OFF and the number of mismatches is 0.
The above sequence is also followed in the next periods t₃ and t₄ so that a column voltage corresponding to the number of mismatches is simultaneously applied to all column electrodes Y₁ ∼ Y_m and selection of row electrodes X₁, X₂, and X₃ ends, the next row electrodes X₄, X₅, and X₆ are selected and a specified column voltage is applied in the same manner to column electrodes Y₁ ∼ X_m, and one frame F ends when all row electrodes have been selected. Thereafter, the first row electrodes X₁, X₂, and X₃ are again selected in sequence and the next frame is started. The sign of the voltage applied to the row electrodes at this time is reversed, and the sign of the voltage applied to the column electrodes is accordingly reversed, to execute so-called alternating current drive scheme.
It is to be noted that it is not essential for the above voltage ratio to conform strictly to the above conditions, and it is not necessary for the periods t₁ ∼ t₄ and the divided periods a, b, c to be strictly divided into equal parts, and can, for example, be adjusted according to the characteristics of the liquid crystals. In addition, the sequence of the divided periods a, b, c can be changed. Furthermore, display of a various number of gradations is possible by means of the same principle described above; for example, to achieve a 16 gray scale display, it is sufficient to apply voltages weighted according to each bit of display data expressed using four bits. This is also true of the other embodiments described below.

(Embodiment 12)

The above embodiment 11 provides a single selection period t for the row electrodes in one frame F, but can also divide the selection period into plural parts in one frame F.
For example, one field can be the period required for all row electrodes to be selected in each of the periods t₁ ∼ t₄, and these four fields can be repeated in one frame F, or these periods can be further divided and the sequence repeated for all of the row electrodes for each display data bit. Fig. 24, Fig. 26, and Fig. 27 show an example of this case.
Fig. 24 is an applied voltage waveform showing an embodiment whereby the four periods t₁ ∼ t₄ in the eleventh embodiment are divided into plural parts for display drive, and Fig. 25 is a waveform of the row voltage applied to row electrodes X₁ ∼ X₆.
First, row electrodes X₁, X₂, and X₃ are selected and a column voltage corresponding to the number of mismatches with three bits is sequentially applied to column electrodes Y₁ ∼ Y_m in the same way as in the eleventh embodiment above, row electrodes X₄, X₅, and X₆ are next selected and a column voltage is again applied as above, and field f₁ for period t₁ ends when all row electrodes have been selected. Next, the row electrodes are again selected in sequence from row electrodes X₁, X₂, and X₃, field f₂ corresponding to the next period t₂ is executed, and when all four fields f₁ ∼ f₄ corresponding to the four period t₁ ∼ t₄ are completed, one frame F is completed.
Fig. 26 shows the case in which execution is grouped for each display data bit, i.e., for each of the subdivided periods of the four periods t₁ ∼ t₄ in the above embodiment.
First, the first period division a in the four periods t₁ ∼ t₄ in Fig. 1 is treated as one field f₁ until all row electrodes have been selected, and one frame is completed when field f₂ corresponding to period division b and field f₃ corresponding to period division c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly.
Fig. 27 shows the case in which execution is further divided and applied to all row electrodes in each of the period divisions a, b, c in Fig. 26. In this example, the effect is the same as frame rate control modulation applied for each display data bit in the embodiment in Fig. 21 above.
When the row electrode selection period is executed plural times within one frame F as described above, the period in which the selected voltage is not applied to each row electrode, i.e., to each pixel, can be shortened, the variation in display brightness can be reduced, and a loss of contrast can be prevented.

(Embodiment 13)

In the eleventh embodiment above, one selection period is divided into the same number of parts as there are gradation bits n, i.e., three, and a column voltage of one of six levels V_Y1 ∼ V_Y6 is selectively applied to the column electrodes, but the number of column voltage levels can be reduced by increasing the above number of divisions.
For example, the effective voltage when driving the liquid crystal elements of a liquid crystal display panel, etc., is generally determined by the voltage value and the voltage applied time (pulse width), and the panel can be equally driven whether a high voltage is applied for a short time or a low voltage is applied for a long time.
It is therefore possible to drive the liquid crystal elements with equivalent effect by selecting from the plural voltage levels a low level voltage and applying this voltage for an extended period rather than using a high level voltage. For example, by using voltage levels V_Y5 and V_Y2 in place of voltage levels V_Y6 and V_Y4 in the first embodiment and increasing the apply time, the elements can be driven in the same way as the first embodiment. It is thereby possible to reduce the number of column voltage levels.
Fig. 28 is an applied voltage waveform showing an embodiment whereby the number of column voltage levels is decreased.
Whereas the selection periods t₁, t₂, t₃, t₄ are divided into n parts, i.e., a, b, and c, in Fig. 21, each selection period is divided into (n+1) parts, i.e.,. a, a, b, c, in the present embodiment, and the first two period divisions a, a are assigned to the voltage apply time of the high display data bit.
Specifically, voltage levels V_Y5 and V_Y2 corresponding to the middle bit, which are half the level of V_Y6 and V_Y4, are respectively substituted for the V_Y6 and V_Y4 voltage levels corresponding to the high bit in the eleventh embodiment, and the apply time is twice that of the middle bit. As a result, the voltage applied to the liquid crystal elements and the time are twice the middle bit and four times the low bit values, and the weighting ratio for each bit is 1:2:4, the same as the case shown in Fig. 1.
Thus, drive equivalent to the case of the eleventh embodiment can be achieved while using one less voltage levels applied to the column electrode.
It is to be noted that the two highest voltage levels V_Y6 and V_Y4 in the eleventh embodiment are eliminated by this embodiment, but the voltage levels V_Y3 and V_Y1 for the low bit can be used, respectively, in place of the middle bit voltage levels V_Y5 and V_Y2 in the eleventh embodiment, using an apply time twice that of the low bits in the same way as above. Furthermore, it is also possible to eliminate four or more voltage levels, and reducing the number of voltage levels as described above is a particularly effective means of simplifying the drive circuit configuration when there are many gradation levels.

(Embodiment 14)

In the thirteenth embodiment above it is also possible to divide the selection periods t₁ ∼ t₄ into plural parts within one frame F as in the twelfth embodiment, and Fig. 29, Fig. 30, and Fig. 31 show examples of this case.
Fig. 29 is a waveform diagram for the case in which one selection period is divided into (n + 1) parts, i.e., 4 parts, and these selection periods are divided into plural parts in one frame, specifically into four fields f, in the third embodiment as in the second embodiment. Note, however, that the selection periods can also be divided into two or three parts.
Fig. 30 shows a case in which driving is executed in each of the period divisions of the four periods t₁ ∼ t₄ in the above embodiment. The first period division a of the period divisions a, a of the four periods t₁ ∼ t₄ in Fig. 21 is treated in sequence as one grouping, and the period until all row electrodes have been selected is one field f₁, and one frame is completed when field f₂ for the next period division a, field f₃ for period division b, and field f₄ for period division c are completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly.
Fig. 31 shows the case in which execution is further divided and applied to all row electrodes in each of the period divisions a, a, b, c in Fig. 10.
The embodiment shown in Fig. 30 and Fig. 31 above achieves the same effect as a gray scale display achieved by weighting the voltage applied to the column electrodes for each field.

(Embodiment 15)

The effective voltage when driving the liquid crystal elements as described above is generally determined by the voltage value applied and the apply time (pulse width), and the desired gray scale display can be achieved by appropriately combining the apply time and the value of the voltage applied to the column electrodes.
Fig. 32 is an applied voltage waveform for an embodiment achieving a 16 gray scale display based on the display data shown in Fig. 33 by appropriately combining the apply time and the value of the voltage applied to the column electrode.
This embodiment also sequentially selects three row electrodes, and applies the row voltage to each of the row electrodes during the four selection periods t₁ ∼ t₄ as in the first embodiment above.
Each of these four periods t₁ ∼ t₄ is divided into six periods a ∼ f, and the first two period divisions a, b correspond to the highest bit in the four digit binary display data shown in Fig. 33, the next period division corresponds to the second bit, the next two period divisions d, e to the third bit, and the last period division f corresponds to the lowest bit.
Column voltage ±V_Y4 or ±V_Y6 is selectively applied to the column electrodes according to the following conditions for the highest two bits, and ±V_Y1 or ±V_Y3 is selectively applied for the lowest two bits.
Note that the voltage value ratio is defined as:
V_Y1 : V_Y3 = 1 : 3
V_Y4 : V_Y6 = 1 : 3
V_Y1 : V_Y4 = 1 : 4.
As above, the highest two bits and the lowest two bits use the same two voltage combinations, the highest bit and the second from the lowest bit are weighted relative to the second from highest bit and the lowest bit, respectively, by doubling the respective pulse widths; the two highest bits can thus express four gradations, the two lowest bits express four gradations, and combined these express 4 × 4 = 16 gradations.
As conditions for the above, ON is when the voltage waveform of the row electrode is positive and OFF is when negative, and a display data value of 1 is ON and 0 is OFF; the on/of state of the simultaneously selected row electrodes and the on/off state of the corresponding display data bits at the intersections of the selected row electrode and the column electrode to which the voltage is to be applied are compared for each bit position, and a voltage specified according to the number of mismatches is applied to the column electrode.
Specifically, when the number of mismatches between the row electrode and the highest bit is 0, 1, 2, or 3, voltage value -V_Y6, -V_Y4, V_Y4, or V_Y6, respectively, is applied to the column electrode in period divisions a, b in this embodiment; for the number of mismatches between the row electrode and the second bit, the same voltages are applied to the column electrode during period division c under the same conditions as above. When the number of mismatches between the row electrode and the third bit is 0, 1, 2, or 3, voltage value -V_Y3, -V_Y1, V_Y1, or V_Y3, respectively, is applied to the column electrode in period divisions d, e; and for the number of mismatches between the row electrode and the lowest bit, the same voltages are applied to the column electrode during period division f under the same conditions as above.
Therefore, in Fig. 32, the three row electrodes X₁, X₂, and X₃ are first simultaneously selected, and the selected row electrodes X₁, X₂, and X₃ are OFF, OFF, ON, respectively, and the highest bits of the display data at the intersection of the column electrode Y₁ and these row electrodes X₁, X₂, and X₃ are OFF, OFF, ON. Comparing both, the number of mismatches is 0, and the voltage -V_Y6 is applied to column electrode Y₁ in the first period divisions a, b of the first period t₁.
Next, the second from highest bits are OFF, ON, OFF and the number of mismatches is 2 when compared with the OFF, OFF, ON states of the row electrodes X₁, X₂, and X₃; voltage V_Y4 is therefore applied in period division c. The second bits are ON, OFF, OFF, the number of mismatches is 2, and voltage V_Y1 is applied in period divisions d, e. The lowest bits are OFF, ON, OFF, the number of mismatches is 2, and voltage V_Y1 is therefore applied. A weighted voltage is applied to the other column electrodes Y₁ ∼ Y_m in the same way.
A column voltage corresponding to the number of mismatches is simultaneously applied to all column electrodes Y₁ ∼ Y_m in the following periods t₂ ∼ t₄ in the same way, selection of row electrodes X₁, X₂, and X₃ ends, the next row electrodes X₄, X₅, and X₆ are selected, the specified column voltages are applied to the column electrodes Y₁ ∼ Y_m in the same way as described above, and when all row electrodes have been selected, one frame F ends. The sign of the voltage applied to the row electrodes is then reversed because the first row electrodes X₁, X₂, and X₃ are again selected in sequence and the next frame begins, and the sign of the voltage applied to the column electrodes is also reversed for so-called alternating current drive scheme.
By thus achieving the desired gray scale display by appropriately combining the time and value of the voltage applied to the column electrodes as described above, a gray scale display can be achieved with fewer voltage levels, even when there are many gradations.
It is to be noted that it is not essential to set the voltage rate as described above in the eleventh embodiment strictly according to the above conditions, and the periods t₁ ∼ t₄ and period divisions a ∼ f do not need to be strictly equal. In addition, the order of the period divisions a ∼ f can be changed as appropriate.

(Embodiment 16)

In the fifteenth embodiment above, the selection period can be divided into plural parts within a single frame F as in the twelfth embodiment.
Fig. 34 shows this case. The periods t₁ ∼ t₄ in Fig. 32 are separately divided into four parts in a single frame F as in the second embodiment, one field f lasts until all row electrodes have been selected in each period, and the operation is repeated four times in one frame F.
Though not shown in the figures, the fifteenth embodiment can also be driven for each display data bit or can be further divided as shown in Fig. 30 and Fig. 31 in the fourteenth embodiment.

(Embodiment 17)

Embodiments 11 ∼ 16 above change the weighting of the display data bit for each column electrode, i.e., change the voltage level applied to the column electrodes, to achieve a gray scale display, but it is also possible to weight the row electrode, i.e., to change the voltage level applied to the row electrode, for a gray scale display.
Fig. 35 is an applied voltage waveform for the embodiment changing the voltage level applied to the row electrodes according to the display data bit to display eight gradations based on the display data shown in Fig. 22 similarly to the eleventh embodiment.
As in the eleventh embodiment, the row electrodes are selected sequentially three lines at a time, and voltage V_X4 or -V_X4 is applied to each row electrode for the high display data bit, V_X2 or -V_X2 is applied for the middle bit, and V_X1 or -V_X1 is applied for the low bit where the ratio V_X1:V_X2:V_X4 is 1:2:4.
The ON/OFF states of the row electrodes X₁, X₂, and X₃ and the display data ON/OFF states are compared bit by bit, and when the number of mismatches is 0, 1, 2, and 3, respectively, voltages -V_Y3, -V_Y1, V_Y1, and V_Y3 are applied to the column electrodes Y₁...; the V_Y1:V_Y3 ratio is 1:3.
If the number of voltage levels on the row electrode side is increased rather than increasing the voltage levels on the column electrode side as in the eleventh embodiment, the number of voltage levels applied to the column electrode can be significantly reduced, and the structure of the column electrode-side drive circuit can be simplified.

(Embodiment 18)

In the seventeenth embodiment above, the selection period can be divided into plural parts within a single frame F as in the twelfth embodiment. Fig. 36, Fig. 37, and Fig. 38 show this case.
Fig. 36 shows the case in which the periods t₁ ∼ t₄ in Fig. 35 are separately divided into four parts in a single frame F as in the twelfth embodiment, one field f lasts until all row electrodes have been selected in each period, and the operation is repeated four times in one frame F.
Fig. 37 shows the case wherein the display is driven for each display data bit, i.e., in each of the period divisions of the four periods t₁ ∼ t₄ in the previous embodiment.
Specifically, the first period division a in the four periods t₁ ∼ t₄ in Fig. 35 is treated as one field f₁ until all row electrodes have been selected, and one frame is completed when field f₂ corresponding to the other period division b and field f₃ corresponding to period division c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly.
As shown in Fig. 38, it is also possible to further divide the periods so that all row electrodes are sequentially selected in each period division.
The same effects obtained with the twelfth embodiment can thus be obtained by driving the display in plural parts within one frame as described above.

(Embodiment 19)

In the seventeenth embodiment above, it is also possible to increase the number of selection period divisions to reduce the number of applied voltage levels as in the thirteenth embodiment.
This case is illustrated in Fig. 39. Each of the periods t₁ ∼ t₄ in Fig. 35 is further divided into four parts in one frame F as in Fig. 28 with the first two period divisions being the apply time for the high bit, and the other period divisions being the apply times for the middle and low bits, respectively. Note that the relationship of the applied voltages in this embodiment is V_X1 : V_X2 = 1:2, and V_Y1:V_Y3 = 1:3.

(Embodiment 20)

In the nineteenth embodiment above, the selection period can also be divided into plural parts within a single frame F. Fig. 40, Fig. 41, and Fig. 42 show this case.
Fig. 40 shows the case where the periods t₁ ∼ t₄ in Fig. 39 are separately divided into four parts in a single frame F as in Fig. 25, one field f lasts until all row electrodes have been selected in each period, and the operation is repeated four times in one frame F.
Fig. 41 shows the case in which execution is grouped for each period division of the four periods t₁ ∼ t₄ in the previous embodiment; the First period division a of period divisions a, a in the four periods t₁ ∼ t₄ in Fig. 39 is treated as one field f₁ until all row electrodes have been selected, and one frame is completed when field f₂ corresponding to the other period division a, field f₃ corresponding to period division b, and field f₃ corresponding to period division c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly.
As shown in Fig. 22, it is also possible to further divide the periods so that all row electrodes are selected in each period division.
The same effects obtained with the twelfth embodiment can thus be obtained by driving the display in plural parts within one frame as described above.

(Embodiment 21)

Even in the case whereby a desired gray scale display is achieved by appropriately combining the apply time and the value of the voltage applied to the column electrodes as in the fifteenth embodiment above, drive identical to that of the fifteenth embodiment is possible by increasing the number of voltage levels on the row electrode side instead of increasing the number of voltage levels on the column electrode side as in the sixteenth embodiment.
Fig. 43 shows an example of this. In this example, voltage V_X4 or -V_X4 is used as the applied voltage level to each row electrode for the two highest display data bits, V_X1 or -V_X1 is applied for the two lowest bits, and the ratio V_X1:V_X4 is 1:4.
The ON/OFF states of the row electrodes X₁, X₂, and X₃ and the display data ON/OFF states are compared bit by bit, and when the number of mismatches is 0, 1, 2, and 3, respectively, voltages -V_Y3, -V_Y1, V_Y1, and V_Y3 are applied to the column electrodes Y₁...; the V_Y1:V_Y3 ratio is 1:3.

(Embodiment 22)

In embodiment 21 above, the selection period can also be divided into plural parts within a single frame F.
Fig. 44 shows this case. The periods t₁ ∼ t₄ in Fig. 41 are separately divided into four parts in a single frame F as in Fig. 24, one field f lasts until all row electrodes have been selected in each period, and the operation is repeated four times in one frame F. In this embodiment it is also possible to further divide and drive as in the previous embodiment.
Though not shown in the figures, embodiment 21 can also be driven for each display data bit or can be further divided as in embodiment 20 shown in Fig. 41 and Fig. 42.

It is to be noted that while each of the above embodiments has been described as simultaneously selecting three row electrodes, a gray scale display with the desired number of gradations is possible by simultaneously selecting two, four, or more row electrodes and applying the same concepts described above. For example, in an embodiment simultaneously selecting six row electrodes, selection periods divided into eight parts t₁ ∼ t₈ are provided in one frame period, and voltages as shown in the table below are applied in each of the selection periods t₁ ∼ t₈ of the six simultaneously selected row electrodes X₁ ∼ X₆.

	t₁	t₂	t₃	t₄	t₅	t₆	t₇	t₈
X₁	V_X1	V_X1	V_X1	V_X1	-V_X1	-V_X1	-V_X1	-V_X1
X₂	V_X1	V_X1	-V_X1	-V_X1	-V_X1	-V_X1	V_X1	V_X1
X₃	V_X1	V_X1	-V_X1	-V_X1	V_X1	V_X1	-V_X1	-V_X1
X₄	V_X1	-V_X1	-V_X1	V_X1	V_X1	-V_X1	-V_X1	V_X1
X₅	V_X1	-V_X1	-V_X1	V_X1	-V_X1	V_X1	V_X1	-V_X1
X₆	V_X1	-V_X1	V_X1	-V_X1	-V_X1	V_X1	-V_X1	V_X1

Note that 0 V is applied during the unselected period. The specified row voltage is applied to each of the row electrodes X₁ ∼ X₆ as described above, and the specified column voltage is simultaneously applied as described in the various embodiments to each of the column electrodes.
In addition, the waveform of the voltages applied to the row electrodes shall not be limited to the embodiments, and the waveforms can be changed to the waveforms as shown in Fig. 48 (a) and (b) or Fig. 3 (a) and (b), or the pulse widths thereof can be appropriately selected or the order changed insofar as the waveforms applied to the simultaneously selected row electrodes do not become intermixed and the row electrodes can be separately driven.
The concept of simultaneously selecting plural sequential row electrodes and dividing the selection period into plural parts in one frame for liquid crystal element drive as described above can also be applied to drive liquid crystal elements using non-linear (including MIM) elements.

Applications in Industry

A drive method and display apparatus for liquid crystal elements according to the present invention as described above simultaneously selects plural sequential row electrodes, divides one selection period into plural periods, and in each of these divided selection periods applies a voltage weighted according to the desired display data to achieve a gray scale display. As a result, lengthening of the time in which the selected voltage is not applied to the pixels and a drop in contrast, flickering due to lengthening of the repeat cycle, or crosstalk due to rounding of the applied voltage waveform are prevented, and a good gray scale display can be achieved. It is also possible to reduce the number of applied voltage levels relative to the number of gradations, the drive means of the drive can be structurally simplified, and a liquid crystal element drive method and display apparatus featuring outstanding reliability and display performance can be provided by means of the invention.

Claims

A liquid crystal element drive method for simultaneously selecting and multiplex driving liquid crystal elements formed with a liquid crystal layer provided between a substrate comprising row electrodes and a substrate comprising column electrodes, and characterized by
dividing the selection period into plural periods,
and applying a voltage weighted according to the desired display data to the electrodes in each of the divided selection periods.
A liquid crystal element drive method according to Claim 1 wherein a column voltage weighted according to the desired display data is applied to the column electrodes to achieve a gray scale display.
A liquid crystal element drive method according to Claim 2 wherein the display data is expressed by plural bits,
and a column voltage of which the pulse width is modulated according to each bit is applied to the column electrodes to achieve a gray scale display.
A liquid crystal element drive method according to Claim 2 wherein the display data is expressed by plural bits,
each of the divided selection periods is divided further according to that number of bits,
and a column voltage corresponding to the display data of each bit is applied to the column electrodes in each of the further divided selection periods to achieve a gray scale display.
A liquid crystal element drive method according to Claim 2 wherein the display data is expressed by plural bits,
each of the divided selection periods is divided further into more parts than the number of bits of display data,
and plural of the further divided selection periods are allocated to the display data corresponding to one of the bits to reduce the number of applied voltage levels.
A liquid crystal element drive method according to Claim 2 wherein the divided selection periods are divided further,
and the voltage value of the voltages applied to the column electrodes in those further divided selection periods and the apply time are appropriately combined to obtain a plural gray scale display.
A liquid crystal element drive method according to any of Claims 1 ∼ 6 wherein the voltages applied to the column electrodes are modulated during a period of plural frames to obtain a gray scale display.
A liquid crystal element drive method according to Claim 1 wherein a row voltage weighted according to the desired display data is applied to the row electrodes to obtain a gray scale display.
A liquid crystal element drive method according to Claim 8 wherein the display data is expressed by plural bits,
each of the divided selection periods is divided further according to that number of bits,
and a column voltage corresponding to the display data of each bit is applied to the column electrodes in each of the further divided selection periods to achieve a gray scale display.
A liquid crystal element drive method according to Claim 8 wherein the display data is expressed by plural bits,
each of the divided selection periods is divided further into more parts than the number of bits of display data,
and plural of the further divided selection periods are allocated to the display data corresponding to one of the bits to reduce the number of applied voltage levels.
A liquid crystal element drive method according to Claim 8 wherein the divided selection periods are divided further,
and the voltage value of the voltages applied to the column electrodes in those further divided selection periods and the apply time are appropriately combined to obtain a plural gray scale display.
A liquid crystal element drive method according to any of Claims 8 ∼ 11 wherein the voltages applied to the column electrodes are modulated during a period of plural frames to obtain a gray scale display.
A liquid crystal element drive method according to any of Claims 1 ∼ 12 wherein the number of voltage levels of the column voltages applied to the column electrodes is reduced by providing virtual electrodes.
A liquid crystal element drive method according to any of Claims 1 ∼ 13 wherein the order of the voltage waveforms applied to each of the row electrodes and column electrodes is changed within each frame.
A liquid crystal element drive method according to any of Claims 1 ∼ 13 wherein the order of the voltage waveforms applied to each of the row electrodes and column electrodes is changed each frame.
A liquid crystal element drive method according to any of Claims 1 ∼ 15 wherein the order of the column voltage waveforms applied to each of the column electrodes is changed each frame.
A liquid crystal element drive method according to any of Claims 1 ∼ 16 wherein the selection periods are provided and driven consecutively in one frame.
A liquid crystal element drive method according to any of Claims 1 ∼ 16 wherein the selection periods are divided into plural periods,
one field is until all row electrodes have been selected in each of the divided selection periods,
and this is executed until all of the above divided selection periods are completed in one frame.
A liquid crystal element drive method according to any of Claims 1 ∼ 16 wherein the divided selection periods are further divided for each bit of display data expressed by plural bits,
one field is until all row electrodes have been selected in each of the further divided selection periods,
and this is executed until all of the above divided and then further divided selection periods are completed in one frame.
A liquid crystal element drive method according to any of Claims 1 ∼ 16 wherein the divided selection periods are further divided into more than the number of bits of display data expressed by plural bits,
one field is until all row electrodes have been selected in each of the further divided selection periods,
and this is executed until all of the above divided and then further divided selection periods are completed in one frame.
A liquid crystal element drive method according to any of Claims 1 ∼ 20 wherein the polarity of the voltages applied to the row electrodes is reversed each frame.
A liquid crystal element drive method according to any of Claims 1 ∼ 20 wherein the polarity of the voltages applied to the row electrodes is reversed in each frame.
A liquid crystal element drive circuit for simultaneously selecting plural sequential row electrodes to multiplex drive liquid crystal elements formed with a liquid crystal layer provided between a substrate comprising row electrodes and a substrate comprising column electrodes, and characterized by
calculating by means of an operating circuit the selection pulse data generated by the scan data generating circuit and the display data for plural simultaneously selected row electrodes,
transferring the data based on that calculation result to the column electrode driver,
and simultaneously transferring the scan data to the row electrode driver to achieve a gray scale display.
A liquid crystal element display apparatus for simultaneously selecting plural sequential row electrodes to multiplex drive liquid crystal elements formed with a liquid crystal layer provided between a substrate comprising row electrodes and a substrate comprising column electrodes,
said display apparatus comprising a drive circuit for calculating by means of an operating circuit the selection pulse data generated by the scan data generating circuit and the display data for plural simultaneously selected row electrodes,
transferring the data based on that calculation result to the column electrode driver,
and simultaneously transferring the scan data to the row electrodes,
and characterized by dividing the selection period into plural periods,
and applying a voltage weighted according to the desired display data by said drive circuit to the electrodes in each of the divided selection periods.