JP3508115B2 - Liquid crystal device, driving method thereof, and driving circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a liquid crystal device such as a liquid crystal display panel (hereinafter,
A liquid crystal device, a liquid crystal element, a liquid crystal element, or the like), a driving method thereof, and a driving circuit.

2. Description of the Related Art Conventionally, multiplex driving by a voltage averaging method has been known as one of the driving methods of the above liquid crystal element.

[Prior Art Example 1] FIG. 45 is an applied voltage waveform diagram showing an example of a conventional driving method in the case where a simple matrix type liquid crystal element or the like as shown in FIG. 46 is multiplexed driven by a voltage averaging method.
45A and 45B are voltage waveforms applied to the scan electrodes X ₁ and X ₂ , respectively, FIG. 45C is a voltage waveform applied to the signal electrode Y _1, and FIG. 45D is a scan electrode X. ₃ shows a voltage waveform applied to a pixel where ₁ and the signal electrode Y ₁ intersect.

In this example, the scan electrodes X ₁ , X _2, ..., X _n are sequentially selected line by line to apply a scan voltage, and a signal corresponding to each pixel on the selected scan electrode is turned on or off. It is driven by applying a voltage to each of the signal electrodes Y ₁ , Y _2, ..., Y _m .

However, the one in which the scanning electrodes are selected and driven one line at a time as described above has a problem that good display cannot be obtained unless the driving voltage is relatively high.

[Conventional Example 2] Therefore, in order to reduce the drive voltage, a method of sequentially selecting and driving a plurality of scan electrodes at the same time has been proposed (for example, A GENERALIZD ADDRESSING TECHNIQUE FO).
R RMS RESPONDING MATRIX LCDS, 1988 INTERNATIONAL DI
See SPLAY RESEARCH CONFERENCE P80-85).

FIG. 47 is an applied voltage waveform diagram showing an example of a conventional driving method for sequentially selecting and driving a plurality of scan electrodes at the same time as described above, and FIG. 47A shows the scan electrodes X ₁ , X ₂ , X. ₃ , a scanning voltage waveform applied to the scanning electrode X ₄ , X ₅ and X ₆ , a scanning voltage waveform applied to the scanning electrode X ₁ , X ₅ and X ₆ , a scanning voltage waveform applied to the signal electrode Y ₁ . (D) shows scan electrode X ₁ and signal electrode Y ₁
7 shows a voltage waveform applied to a pixel where and intersect.

In this example, the scanning electrodes are sequentially selected by three lines at a time and the display as shown in FIG. 46 is performed.
That is, first, the three scan electrodes X ₁ , X _2, and X ₃ are selected, and a scan voltage as shown in FIG. 47A is applied to these scan electrodes X ₁ , X _2, and X ₃ . At the same time, a predetermined signal voltage described later is applied to each of the signal electrodes Y _{1 to} Y _m . Then selects the scanning electrodes X ₄ · X ₅ · X ₆ in FIG. 46, the signal electrodes Y ₁ simultaneously applying a scan voltage, such as electrodes in the same manner as described above in Figure 47 it (b) to Y _Apply signal voltage to _m . Then, one frame is set until all the scan electrodes X _{1 to} X _n in FIG. 46 are selected, and this is sequentially repeated.

Each of the above scanning voltage waveforms has a pulse pattern number of 2 ^h , where h is the number of simultaneously selected scanning electrodes. In this example, h = 3 and 2 ^h = 2 ³ A waveform having a pulse pattern number of = 8 is used.

For example, the ON / OFF pattern of the voltage applied to the _three scan electrodes X ₁ , X _2, and X ₃ that are simultaneously selected can be expressed as shown in the following table, with ON being 1 and OFF being 0.

When a voltage waveform applied to each scan electrode is formed based on this, it becomes as shown in FIG. However, the figure (a)
The waveform has a variation in frequency, and display unevenness may occur when it is actually used.

Therefore, the arrangement is appropriately changed to eliminate the deviation of the frequency components, and the waveform shown in FIG. 47B is obtained. In the conventional example shown in FIG. 47, this waveform is used.

On the other hand, the signal voltage applied to each of the signal electrodes Y _{1 to} Y _m has the same number of pulse patterns as the scanning voltage, and the voltage level of each pulse has a magnitude corresponding to ON / OFF on the selected scanning electrode. A voltage is applied, for example, in this example, when the scanning voltage waveform applied to the simultaneously selected scanning electrodes X ₁ , X _2, and X ₃ is a positive pulse, it is turned on, and when it is a negative pulse. Is turned off, display data is turned on and off for each pulse, and the signal voltage waveform is set according to the number of mismatches.

That is, in FIG. 47, when the number of mismatches is 0, −
V _Y2, 1 of when -V _Y1, is 2 when when V _Y1, 3 V _Y2
The pulse voltage is applied. The above voltage ratio of V _Y1 and V _Y2 is set so that V _Y1 : V _Y2 = 1: 3.

More specifically, at an applied voltage waveforms to the scan electrodes X ₁ · X ₂ · X ₃ in FIG. 47, on the case of applying a voltage of V _X1, and off when applying a voltage of -V _X1, FIG. When the black circle is turned on and the white circle is turned off, the pixel display of 46 is shown in FIG.
The display of the pixel at which the signal electrode Y ₁ and the scan electrode X ₁ , X ₂ , X ₃ intersect in is turned on and off in order, and in contrast to this, applied to each scan electrode X ₁ , X ₂ , X ₃ . The first pulse pattern of the applied voltage is OFF, OFF, OFF respectively. Since the two are sequentially compared and the number of mismatches is 2, the voltage V _Y1 is applied to the first pulse pattern of the signal electrode Y ₁ as shown in FIG. 47 (c).

The second pulse pattern of the voltage applied to each scan electrode X ₁ , X _2, and X ₃ is OFF, OFF, and ON, respectively. Since they do not match and the number of mismatches is 3, the voltage V _Y2 is applied to the second pulse of the signal electrode Y ₁ . In a similar manner, -V _Y1 is applied to the V _Y1, 4 th pulse to the third pulse, or less, -V _Y2, V _Y1, -
It is applied in the order of V _Y1 and −V _Y1 .

The selected three scan electrodes X ₄ to X ₆ of the following, when the voltage shown in (b) of FIG. 47 is applied to the scanning electrodes X ₄ to X _6, the respective scanning electrodes X ₄ and on-off display of the pixels at the intersection of the to X ₆ and the signal electrodes, the voltage level of the signal voltage corresponding to the mismatch between the on-off of each pulse pattern of the voltage applied to the scanning electrodes X ₄ to X ₆ Is applied as shown in FIG. 47 (c).

In the above example, the positive selection pulse of the scan voltage waveform is 1, the negative selection pulse is -1, the display of each pixel is -1 and the display of each pixel is off is 1. I set the signal voltage waveform by the difference, but which is 1 or -1
Alternatively, the signal voltage waveform can be set only by the number of matches or the number of mismatches without calculating the difference between the number of matches and the number of mismatches.

As described above, the method of sequentially selecting and driving a plurality of scanning electrodes simultaneously realizes the same on / off ratio as the method of selecting and driving one line at a time as shown in FIG. There is an advantage that the voltage can be kept low.

Next, general requirements, procedures, procedures, and the like of the method of sequentially selecting and driving a plurality of scanning electrodes simultaneously as described above will be described step by step.

A requirements a) Divide N scan electrodes into N / h subgroups.

b) Each subgroup has h address lines.

c) At a certain time, the signal electrode has an h-bit word (h
-Bit word).

d _{k * h + 1} , d _{k * h + 2} ... d _{k * h + h} ; d
_{k * h +} j = 0 or 1, where, 0 ≦ k ≦ (N / h) -1: display data (k subgroup) i.e. one _{column, d 1, d 2, ‥‥} d h ····· 0th subgroup d _{h + 1} , d _{h + 2}・ ・ ・ d _{h + h}・ ・ ・ ・ ・ 1st subgroup d _{N-h + 1} , d _{N-h + 2}・ ・ ・ d _{N-h + h}・・ ・ ・ It becomes the N / h-1 subgroup.

d) The scanning electrode selection pattern is ^h with a period of 2 ^h shown in the following equation.
It is a bit word pattern.

a _{k * h + 1} , a _{k * h + 2} ... a _{k * h + h} ; a
_{k * h + j} = 0 or 1 B. Procedure (1) One subgroup is selected at the same time.

(2) One h-bit word is selected as the scan electrode selection pattern.

(3) Scan voltage is -Vr for logic 0,                   + Vr for Logic 1,                   When not selected, it is 0 volt.

(4) The scan electrodes and signal electrodes of the selected subgroup are compared bit by bit.

(5) Determine the number i of pattern mismatches between the scan electrodes and the signal electrodes.

(6) The voltage applied to the signal electrode is V _(i) . i is the number of disagreements.

(Depending on the number of discrepancies, 1 of the predetermined voltage
(7) Determine the signal voltage based on the above method (simultaneously and in parallel).

(8) The scanning voltage and the signal voltage obtained as described above are applied to the display only during the time interval Δt ₀ . However, Δt ₀ is the minimum pulse width.

(9) A new scan electrode selection pattern is selected, the above (4) to (6) are calculated again, and the next signal voltage is determined.
This is also applied for the time interval Δt ₀ .

(10) One cycle (cycle) ends when all 2 ^h scan electrode selection patterns appear in each subgroup and N / h subgroups are selected.

1 cycle = Δt · 2 ^h · (N / h) C. Analysis Consider the scan electrode selection pattern when there are i mismatches (mismatches).

When the scan electrode selection pattern of h-bit word length does not match the data pattern of the same h-bit word length by i bits, the number is _h C _i = {h!} / {i! (hi)! } = Ci exist.

For example, considering the case where h = 3 and the scanning electrode selection pattern = (0,0,0), the following table is obtained.

These are determined by the number of bits of the word, not the scan electrode selection pattern.

Amplitude V _pixel of the instantaneous voltage applied to the pixel, a scan voltage V _row, when the signal voltage is _{V column, V pixel = (V} column -V row) or (V _row -V _column) where, V _row = ± Vr V _column = V _(i) , then V _pixel = + Vr-V _(i) or -Vr-V _(i) .

If V _row = ± Vr V _column = ± V _(i) , then V _pixel = Vr−V _(i) , Vr + V _(i) , −Vr−V _(i) or −Vr + V _(i), that is, V _pixel = | Vr−V _(i) | or | Vr ＋ V _(i) |.

Therefore, specific amplitudes applied to pixels in the selected row - a _(Vr + V _(i)) or _{(Vr-V (i))} V (i) in the non-selected rows. (If V _(i) is considered to be ambipolar, the above description can be made.) Generally, the voltage applied to a pixel should be as large as possible for on-pixels and as small as possible for off-pixels. It is desirable to realize a high selection ratio.

Therefore, when on, | Vr + V _(i) | favors on-pixels and | Vr−V _(i) | favors on-pixels.

When off, | Vr−V _(i) | favors off pixels and | Vr + V _(i) | favors off pixels.

Here, the advantage for ON is to increase the effective voltage, and the disadvantage for ON is to decrease the effective voltage.

The number of combinations that i pieces selected from among the h _{bits, Ci = h C i = {} h!} / {i! (h-i)! }, And if there is a mismatch with i, this is i out of h bits.
This is the number of cases where the bits do not match. Since the number of mismatches is i at each level, the total number of mismatches (total mismatch) is i · Ci.

These are distributed over h bits, so
The average number of mismatches Bi per pixel (per bit) is Bi = i · Ci / h (pieces / pixel).

Further, if the level of the signal voltage V _(i) is increased as the number of mismatches increases, V _pixel = V _row −V _column decreases as the number of mismatches increases.

Considering the mismatch as a disadvantage for the on-pixel of interest, the number of mismatches gives the number of adverse voltages (signal voltages).

Therefore, the number of (on average) disadvantageous voltages per pixel is Bi = i · Ci / h.

By the way, since i / h of Ci is disadvantageous, the rest, that is, Ai = {(h−i) / h} · Ci works favorably. Also, {(h−i) / h} · Ci + (i / h) · Ci = (h / h) Ci = Ci, and Ai = Ci−Bi = {(h−1)! } / {I · (h−i−1)! } However, it is h> = i + 1.

To summarize the above, V _ON (r, m, s) = {(S ₁ + S ₂ + S ₃ ) / S ₄ } ^1/2 V _OFF (r, m, s) = {(S ₅ + S ₆ + S ₃ ). / S ₄ } ^1/2 . In addition, Is.

Also, Vr / V ₀ = N ^1/2 / h ··· Row selection voltage V _(i) / V ₀ = (h−2i) / h = {1- (2i / h)} It is a column voltage, and R = (V _ON / V _OFF ) _max = {(N ^1/2 +1) / (N ^1/2 −1)} ^1/2 .

However, in the case of sequentially selecting and driving a plurality of scan electrodes simultaneously as in the second conventional example, the pulse width applied to the scan electrodes and the signal electrodes becomes narrower as the number of scan electrodes selected simultaneously increases. However, there is a problem that the crosstalk due to the summary of the waveform is increased and the image quality is deteriorated. In particular, when the gradation display is performed by the modulation of the pulse width, the problem becomes serious.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal device, a driving method thereof, and a driving circuit capable of excellent gray scale display even when a plurality of scanning electrodes are sequentially selected and driven as described above. .

DISCLOSURE OF THE INVENTION A liquid crystal device, a driving method thereof, and a driving circuit according to the present invention have the following configurations. That is, a liquid crystal device including a plurality of scan electrodes and a plurality of signal electrodes intersecting the plurality of scan electrodes, and a liquid crystal sandwiched between the scan electrodes and the signal electrodes, or a driving method or a driving circuit thereof. In, the plurality of scan electrodes are divided into sub-groups, the scan electrodes in the sub-group are simultaneously selected, the selection period is divided into a plurality of periods, the waveform of the scanning voltage in each divided period, Grayscale display is performed by applying a voltage applied to the simultaneously selected scan electrodes and weighted based on the waveform of the scan voltage and the data to be displayed during the selection period. Characterize.

With the above-described configuration, even when a plurality of scanning electrodes are sequentially selected at the same time to perform multi-blex drive, crosstalk or the like is less likely to occur and good gradation display can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an applied voltage waveform diagram showing an embodiment of a driving method of a liquid crystal element or the like according to the present invention.

FIG. 2 is an explanatory diagram showing a schematic configuration of a liquid crystal element and the like and display data.

  FIG. 3 is an explanatory diagram of a scan voltage waveform applied to the scan electrodes.

  FIG. 4 is a block diagram showing an embodiment of the drive circuit.

  FIG. 5 is a block diagram of the scan electrode driver.

  FIG. 6 is a block diagram of the signal electrode driver.

FIG. 7 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 8 is an explanatory diagram of the procedure and display data when driving using virtual electrodes.

FIG. 9 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

  FIG. 10 is an explanatory diagram of gradation display by pulse width modulation.

FIG. 11 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 12 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 13 is an explanatory view of the arrangement configuration of virtual electrodes and display data.

FIG. 14 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 15 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 16 is an explanatory diagram of the arrangement configuration of virtual electrodes and display data.

FIG. 17 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 18 is an explanatory view of the arrangement configuration of virtual electrodes and display data.

FIG. 19 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 20 is an explanatory diagram of a waveform of a voltage applied to a signal electrode showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 21 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

  FIG. 22 is an explanatory diagram of the arrangement configuration of electrodes and display data.

FIG. 23 is a waveform diagram of a voltage applied to the signal electrode in the above embodiment.

FIG. 24 is an applied voltage waveform diagram of an embodiment in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 25 is a waveform diagram of a voltage applied to the signal electrode in the above embodiment.

FIG. 26 is an applied voltage waveform diagram of another example in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 27 is an applied voltage waveform diagram of another example in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 28 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 29 is an applied voltage waveform diagram of an embodiment in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 30 is an applied voltage waveform diagram of another example in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 31 is an applied voltage waveform diagram of another example in which the selection period in the above-described embodiment is divided into a plurality of times for driving.

FIG. 32 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

  FIG. 33 is an explanatory diagram of the arrangement configuration of electrodes and display data.

FIG. 34 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 35 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 36 is an applied voltage waveform diagram of an embodiment in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 37 is an applied voltage waveform chart of another example in which the selection period in the above-described embodiment is driven a plurality of times within one frame.

FIG. 38 is an applied voltage waveform diagram of another example in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 39 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 40 is an applied voltage waveform diagram of an embodiment in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 41 is an applied voltage waveform diagram of another example in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 42 is an applied voltage waveform diagram of another example in which the selection period in the above-described embodiment is divided into a plurality of times for driving.

FIG. 43 is an applied voltage waveform diagram showing another embodiment of the method for driving a liquid crystal element or the like according to the present invention.

FIG. 44 is an applied voltage waveform diagram of an embodiment in which the selection period in the above embodiment is driven a plurality of times within one frame.

FIG. 45 is an applied voltage waveform diagram showing an example of a conventional method for driving a liquid crystal element or the like.

  FIG. 46 is an explanatory diagram of display patterns.

FIG. 47 is an applied voltage waveform diagram showing another example of a conventional method of driving a liquid crystal element or the like.

  FIG. 48 is an explanatory diagram of a voltage waveform applied to the scan electrodes.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a driving method of a liquid crystal element and the like, a driving circuit and a display device according to the present invention will be specifically described based on the embodiments shown in the drawings.

[Embodiment 1] FIG. 1 is an applied voltage waveform diagram showing an embodiment of a method for driving a liquid crystal display device or the like according to the present invention. FIG. 1 (a) shows the applied voltage to scan electrodes X ₁ , X ₂ , X _3. Voltage waveform, (b) is the scan electrode
Voltage waveform applied to X ₄ , X ₅ and X ₆ , (c) is signal electrode Y ₁
Waveform applied to the scan electrode, (d) is the scan electrode X ₁ and the signal electrode
Y ₁ and indicates the voltage waveform applied to the pixel crossing.

In this embodiment, the three scan electrodes are sequentially selected at the same time, as shown in FIG.
The display is as shown in.

As the voltage waveform applied to the scanning electrodes simultaneously selected, the waveform shown in FIG. 48 (a) or (b) can be used, but in the present embodiment, the waveform shown in FIG. 1 (a) is used. Is used.

When the voltage waveform corresponding to the bit word pattern as shown in (a) or (b) of FIG. 48 is used,
There is a problem that each pulse width becomes narrow, and especially when the number of scan electrodes selected at the same time increases, the number of the bit word patterns described above exponentially increases, and accordingly, each pulse width becomes inevitably narrower. When applied to a pixel, crosstalk due to so-called summary may occur. Moreover, when gradation display is performed by modulating the pulse width as in the present embodiment and the later-described embodiments, the pulse width is further narrowed and causes crosstalk.

Therefore, in the present embodiment, the waveform of the voltage applied to the scanning electrodes is set in the following manner so that the pulse width becomes wider.

The voltage waveform applied to the scan electrodes is as follows. Each scanning electrode can be distinguished. The frequency components applied to each scan electrode do not differ greatly. It is determined in consideration of the fact that the AC property is guaranteed within one frame or several frames.

That is, the pattern of the applied voltage is appropriately selected from the orthogonal function system such as natural binary, Walsh, Hadamard, etc. in consideration of the above conditions.

Of these, the above items are absolute conditions. In order to particularly satisfy the items, the voltage waveforms applied to the scan electrodes are determined so as to be orthogonal to each other.

The applied voltage waveforms shown in (a) and (b) of FIG. 3 are determined in consideration of the above requirements, and the applied voltage waveform of (a) of FIG. 3 is X ₁ : 4 * Δt ₀ X _It contains different frequency components of ₂ : 4 * Δt ₀ , 2 * Δt ₀ X ₃ : 2 * Δt ₀ .

The applied voltage waveform shown in FIG. 3B is X ₁ : 4 * Δt ₀ , 2 * Δt ₀ X ₂ : 4 * Δt ₀ , 2 * Δt ₀ X ₃ : 6 * Δt ₀ , 2 * Δt ₀ It contains different frequency components.

The shortest pulse width of the waveforms shown in (a) and (b) of FIG. 48 was Δt ₀ , while (a) and (b) of FIG.
The narrowest pulse width Δt of the waveform in (b) is 2Δt ₀ ,
Can be doubled. By increasing the pulse width in this way, it is possible to reduce the effect of the waveform summary.
Crosstalk can be reduced and the number of scan electrodes selected at the same time can be increased.
The waveforms shown in (a) and (b) of FIG. 3 are examples and can be changed as appropriate. The selection order of scan electrodes, the arrangement order of pulse patterns applied to each scan electrode, and the like use the property of an orthogonal function. Can be changed accordingly.

The scanning voltage waveforms of the present embodiment shown in FIGS. 1A and 1B constitute voltage waveforms applied to three scanning electrodes that are simultaneously selected based on the waveform of FIG. 3B. It is a thing. Further, in the present embodiment, an example is shown in which the selection period is divided into four times t1, t2, t3, and t4 within one frame for driving. (Here, each of the four selected periods is
This is called a small selection period. On the other hand, for the signal electrodes Y _{1 to} Y _m , as shown in (c) of FIG. 1, each of the divided selection periods t ₁ , t ₂ , t ₃ and t ₄ is further divided into a plurality of periods, In each of the divided periods, a voltage weighted according to desired display data is applied.

That is, in the present embodiment, the period of t ₁ is equally divided into two periods of a and b, and 4 gradation display is represented by 2 bits by the binary system based on the display data shown in FIG. The signal voltage with a predetermined weighting for each bit is applied during the period a for the upper bits and during the period b for the lower bits.

Specifically, when the voltage V _X1 is applied to the scan electrodes, it is turned on, when the voltage −V _X1 is applied, it is turned off, and the display data is turned off by turning on 1 and turning on simultaneously selected scan electrodes.・ The number of mismatches is calculated by comparing OFF and display data ON / OFF in order for each bit. For the upper bits, V _Y4 when the number of mismatches is 3, V _Y2 when 2, and when the number of mismatches is 1. When -V _Y2 and 0, -V _Y4 is applied respectively. For the lower bits, V _Y3 when the number of mismatches is 3, V _Y1 when 2, and -V _Y1 when ₁ and 0 when 0. Apply −V _Y3 respectively. The relationship between each voltage level is
2 * V _Y1 = V _Y2 , 2 * V _Y3 = V _Y4 , 2 * V _Y1 = V _Y3 −V _Y1 , 2
* V _Y2 = V _Y4 −V _Y2 .

For example, in the period of t ₁ in FIG. 1C, the selection pulse applied to the scan electrodes X ₁ , X ₂ and X ₃ is ON,
The order is off, off, signal electrode Y ₁ and scan electrode X ₁ ,
The display data of the pixel at each intersection with X ₂ and X ₃ is (00) (01)
In (10), the high-order bits are off, off, and on, and the number of mismatches is 3 when compared, and the signal electrode Y ₁
Is applied with voltage V _Y4 during period a. The lower bits are off, on, and off, and the number of mismatches is 1 as compared with the scan electrodes, and the voltage -V _Y1 is applied during the period b.

In this way, the display data on the scan electrodes X ₁ , X ₂ , and X ₃ is compared with the selection pulse applied to the scan electrodes for each of the signal electrodes Y _{1 to} Y _m , and the signal voltage corresponding to the number of mismatches is obtained. Is applied.

Next, the scanning electrodes X ₄ , X ₅ , and X ₆ are selected at the same time, and a signal electrode waveform corresponding to them is applied to the signal electrodes. In this way, while the scanning electrodes are simultaneously selected every three lines, the signal voltage waveform corresponding to the display data is applied to the signal electrodes, and when all the scanning electrodes X _{1 to} X _n have finished scanning, the first scanning electrodes are again scanned. Returning to X ₁ , X ₂ , and X ₃ , a predetermined voltage is sequentially applied in the same manner as above during the period of t ₂ , t ₃ , and t ₄ . And t ₁ ~
When four periods of t ₄ has finished scanning all the scanning electrodes X ₁ to X _n 1 frame is completed, the next frame will be repeated. In this embodiment, so-called AC driving is performed by alternately changing the polarities of the applied voltage for each frame.

By driving as described above, good gradation display with less crosstalk can be performed.

Note that the order of the scanning voltage waveforms applied to the scanning electrodes during the above-mentioned periods t _{1 to} t ₄ may be changed appropriately for all frames or for each frame, and the scanning voltage waveforms applied to the scanning electrodes are shown in FIG. It is also possible to use the waveform shown in a) or other waveforms that satisfy the above requirements.
Further, for example, the scanning electrodes X _{1 to} X ₃ are simultaneously selected such that the waveform shown in FIG. 3A is used and the next scanning electrodes X _{4 to} X ₆ are used the waveform shown in FIG. 3B. It is also possible to alternately switch two types of waveforms for each scan electrode, or to sequentially switch three or more types of waveforms. Further, it is also possible to combine the above-mentioned waveform replacement for each scanning electrode simultaneously with the waveform replacement for the periods t _{1 to} t ₄ .

Further, the above periods t _{1 to} t ₄ may be driven separately for each period as in this embodiment, or may be continuously provided and driven in one frame, but as in this embodiment, When the selection period is driven in a plurality of times in one frame F, the non-selection period is shortened and the contrast can be enhanced. In this case, in the above-described embodiment, the selection period is divided into four times t ₁ to t ₄ for driving, but the number of divisions is arbitrary, and for example, the period t _{1 to} t ₄ is 2 times.
It is also possible to drive in divided times, or to drive in more times.

Furthermore, in the above-mentioned embodiment, the scanning electrodes are selected at the same time by three in accordance with the arrangement order, but the number of selections is arbitrary, and the scanning electrodes can be selected without necessarily following the arrangement order.

The changes described above can be similarly applied to the embodiments described later.

Next, a configuration example of a drive circuit that executes the above-described drive method will be described with reference to FIGS.

FIG. 4 is a block diagram showing an example of a drive circuit, in which 1 is a scan electrode driver, 2 is a signal electrode driver,
Reference numeral 3 is a frame memory, 4 is an arithmetic circuit, 5 is a scan data generating circuit, and 6 is a latch.

FIG. 5 is a block diagram of the scan electrode driver, and FIG. 6 is a block diagram of the signal electrode drive. In FIGS. 5 and 6, 11 and 21 are shift registers, 12 and 22 are latches, 13 and 23 are decoders, and 14 and 24. Is a level shifter.

In the above configuration, each scan voltage waveform causes the scan data generation circuit 5 of FIG. 4 to generate data indicating positive selection, negative selection, or non-selection. Forward.

In the scan electrode driver 1, as shown in FIG. 5, the scan data signal S3 from the scan data generating circuit 5 is transferred to the shift register 11 by the scan shift clock signal S5, and after the data of each scan electrode in one scan period is transferred. Latch signal S6
Each data is latched by, the data showing the state of each scan electrode is decoded, and the analog switch for each output
Turn on one of the three switches at 15 to output V _X1 for positive selection, -V _{X1 for} negative selection, and 0 for non-selection to the selected scan electrode. To do.

On the other hand, for each signal voltage waveform, the display data signal S1 for each of the three scanning electrodes simultaneously selected from the frame memory 3 is read, and the selection pulse data is latched from the display data signal S1 and the scanning data signal S3. The scanning data signal S1 and the selection pulse data signal S4 are converted by the arithmetic circuit 4.
The data conversion is performed as described above and transferred to the signal electrode driver 2.

In the signal electrode driver 2, as shown in FIG. 6, the data signal S2 from the arithmetic circuit 4 is transferred to the shift register 21 by the shift clock signal S7, the data of each signal electrode in one scanning period is transferred, and then by the latch signal S8. Each data is latched, the data representing the state of each signal electrode is decoded, and one of the eight switches is turned on by the analog switch 25 for each output, and V _Y4 , V _Y3 , V _Y2 , V _Y1 , -V
Any one of eight voltages of _Y1 , -V _Y2 , -V _Y3 , -V _Y4 is output to each signal electrode.

By using the driving circuit as described above, the driving method as described above can be executed easily and reliably.

Further, by providing the display device having the above-mentioned display element or the like with the drive circuit as described above and executing the drive method as described above, good gradation display is performed with less occurrence of crosstalk and the like. Thus, a display device capable of being obtained is obtained.

[Embodiment 2] In the above Embodiment 1, one of four types of voltages for each bit of the display data is applied to the signal electrode in accordance with the display data.
However, the number of voltage levels applied to the signal electrodes can be reduced by providing virtual electrodes.

FIG. 7 is a voltage waveform diagram according to the present embodiment in which the number of voltage levels applied to the signal electrode is reduced by providing the virtual electrode in the first embodiment, and FIG. 8 is applied to the signal electrode by providing the virtual electrode. It is explanatory drawing which shows the point which reduces the number of the voltage levels to operate.

In this embodiment, for example, as shown in FIG. 8, virtual electrodes such as X _{n + 1} X _{n + 2} ... Are provided next to the scan electrodes that are simultaneously selected, and for example, scan electrodes X ₁ , X ₂ , X ₃ are provided. It is assumed that X _{n + 1} is also selected at the same time when is selected, and when the voltage V _X1 is applied to the scan electrode as in the first embodiment, the voltage is turned on and the voltage −V _X1 is applied.
Is turned off, display data is turned off 0, 1
Turn on to calculate the number of disagreements. In this case, the number of mismatches is always 1 or 3 by appropriately changing the state of the virtual electrode.
Try to be.

The -V _Y2 when the number of mismatches in the upper bits of the display data 1, select V _Y2 when the number of mismatches is 3, the number of mismatches in the low-order bits of the display data -V _Y1 when 1, the number of mismatches is 3 When to choose V _Y1 . The relationship between the voltage levels is 2 * V _Y1 = V _Y2 .

FIG. 7 shows the display shown in FIG. 2 according to the above procedure. Looking at the period of t ₁ , the scan electrodes X ₁ , X ₂ , X ₃
And the selection pulses applied to the virtual electrode X _{n + 1} are sequentially turned on,
ON, OFF, ON, signal electrode Y ₁ and scan electrode X ₁ ,
The display data of the pixel at each intersection with X ₂ , X ₃ and X _{n + 1} is (0
In 0) (01) (10) (11), the upper bits are off, off, on, and on. When compared in order, the number of mismatches is 3, and the conversion data S2 is created according to the number of mismatches. The voltage V _Y2 is applied to the signal electrode Y ₁ in the period a.

Looking at the lower bit, it turns off, on, off, and on, and the number of mismatches is 1 compared to the scan electrodes, and the conversion data S2 is created according to the number of mismatches, and the voltage is applied to the signal electrode Y ₁ in the period b. −V _Y1 is applied.

In this way, the display data on the scan electrodes X ₁ , X ₂ , X ₃ and X _{n + 1} is compared with the selection pulse applied to the scan electrodes for each of the signal electrodes Y _{1 to} Y _m , and the number of mismatches is determined. A corresponding voltage is applied.

Next, the scan electrodes X ₄ , X ₅ , X ₆ and X _{n + 2} are simultaneously selected and the signal electrode waveform corresponding to them is applied to the signal electrodes.
In this way, while 3 scanning lines and 1 virtual electrode line are simultaneously selected, the corresponding signal electrode waveform is applied to the signal electrode, and when scanning up to the scanning electrode X _{n is} completed, the first scanning electrode X _{1 is} again scanned. , X ₂ , X ₃ , and scan in sequence with the pulse pattern indicated by t ₂ . In this way
One frame period is completed by scanning four times with each pulse pattern shown in t ₁ , t ₂ , t ₃ , and t _4, and the same operation is repeated in the next frame.

By providing the virtual electrodes as described above, the number of voltage levels applied to the signal electrodes can be reduced as compared with the case of the first embodiment.

It should be noted that reducing the number of voltage levels applied to the signal electrodes by providing the virtual electrodes as described above can also be applied to each embodiment described later.

Also, in the present embodiment and each of the embodiments described later, the same drive circuit as that of the first embodiment can be used. In that case, the arithmetic circuit 4 in FIG. 4 is configured to perform data processing according to each embodiment, and the voltage levels of the scan electrode driver of FIG. 5 and the signal electrode driver of FIG. 6 are provided according to each embodiment. The analog switches 15 and 25 may be configured to select either voltage level.

For example, in this embodiment, the arithmetic circuit 4 in FIG. 4 and the scan electrode driver in FIG. 5 are the same as those in the first embodiment, and the signal electrode driver in FIG.
8 of V _Y4 , V _Y3 , V _Y2 , V _Y1 , -V _Y1 , -V _Y2 , -V _Y3 , -V _Y4
Although two voltage levels are provided, V _Y2 , V
_It is only necessary to provide four voltage levels _Y1 , -V _Y1 , -V _Y2 .

[Third Embodiment] In each of the above-described embodiments, gradation display is performed by changing the voltage value according to the display data, but gradation display can also be performed by changing the pulse width.

FIG. 9 is an applied voltage waveform diagram of an embodiment in which gradation display is performed by pulse width modulation.

First, a general procedure for performing gradation display by pulse width modulation will be described.

Generally, when performing gradation display by pulse width modulation, the time width Δt of the pulse is divided into f time widths of unequal intervals.

Δt _g = 2 ^g -1 / (2 ^f -1) (f is the number of gradation bits) For example, when f = 2, 2 ² = 4 gradations, and the time width is as shown in FIG. It is divided into Δt ₁ = (1/3) Δt ₀ and Δt ₂ = (2/3) Δt ₀ .

Next, divide each data into f bits (represented by f bits)
To do.

Then, each bit of the scan electrode selection pattern and the data pattern is compared at an interval of Δtg.

For example, when f = 2 Next, first, of d _1, d _{1, 1} compares the (lower bits) and the scan electrode selection pattern is applied between Delta] t ₁ display.

Next, d _1,2 is compared with the scanning electrode selection pattern, and Δt ₂
Apply to the display during.

This may be sequentially performed for each d in the same manner as described above.

In FIG. 9 according to the present embodiment, the display of four gradations as shown in FIG. 2 is performed by pulse width modulation in the above manner.

In this example, the same scanning voltage as in the conventional example of FIG. 47 is applied to each scanning electrode X _{1 to} X _n , and the signal electrode Y _{1 corresponding} thereto is applied.
The pulse width of Y _m is modulated according to the gradation display.

That is, each pulse width Δt is equally divided into three, and the gradation display of four steps from 0 to 3 is represented by 2-bit display data (00), (01), (10), (11). The voltage level of two divisions among the three divisions is determined by the ON / OFF of the scan electrodes selected at the same time and the number of disagreements with the upper bits of the above display data. The voltage level is determined for the divided portion. Further, by making the three divisions non-uniform, it is possible to correct the luminance change of the gradation display.

Specifically, when the voltage V _X1 is applied to the scan electrodes in FIG. 9 and the voltage −V _X1 is applied to the scan electrodes in FIG. 9, the first pulse applied to the scan electrodes X ₁ , X _2, and X ₃ is the first pulse. Are all off, while the scan electrodes of FIG.
X _1, X _2, X ₃ display data of the lower bits off the 0, turns on the 1, because it is off-on-off, the number of mismatches becomes 1, the voltage pulses between Delta] t ₁ is -V _Y1 Since the upper bits are off, off, and on, the number of mismatches is 1 and the voltage pulse during Δt ₂ is −V _Y1 . In this way, the voltage pulse to be applied to the signal electrode may be obtained by comparing each selection period Δt.

In this embodiment, the voltage for the upper bit is applied in the latter two periods of the three divisions, and the voltage for the lower bit is applied in the one previous period of the three divisions. The voltage for the upper bit may be applied in the two previous periods of the three divisions, and the voltage for the lower bit may be applied in the one subsequent period of the three divisions.

[Embodiment 4] Even in the case of performing the gradation display as described above, it is possible to drive the selection period divided into a plurality of times within one frame as in the case of the above-described Embodiment 1.

FIG. 11 shows an example thereof. In the embodiment of FIG. 9, the voltage waveform composed of eight pulse patterns (blocks) applied to the scanning electrodes and the signal electrodes is divided into eight at regular intervals for each pulse pattern. The following shows an example in which it is output.

When the selection period is driven a plurality of times within one frame as described above, the contrast can be enhanced as in the above-described embodiment.

[Fifth Embodiment] In the above-described third and fourth embodiments, four levels of V _Y2 · V _Y1 · -V _Y1 · -V _Y2 are used as the voltage levels of the signal electrodes. Similarly, the number of voltage levels can be reduced by providing virtual electrodes.

FIG. 12 shows an example in which virtual electrodes are provided in the third embodiment to reduce the voltage level applied to the signal electrodes, and the selection period is divided into a plurality of times within one frame, as in the fourth embodiment.

The procedure for reducing the number of voltage levels by providing the virtual electrodes as described above has already been described in the second embodiment, but the general method and the like will be described here.

First, among the h subgroups described above, e lines are set as virtual scan electrodes (virtual lines), and the coincidence / disagreement of data of the virtual scan electrodes is controlled to limit the total number of coincidences / disagreements, and The number of drive voltage levels of the electrodes is reduced.

If the number of mismatches is Mi and Vc is an appropriate constant, the applied voltage V _column to the signal electrode is Alternatively, simply V _column = V _(i) 0 ≤ i ≤ h In any case, V _column is at level h + 1.

For example, consider the case where the subgroup h = 4 and the virtual scan electrode e = 1.

As in the above embodiment, the number of levels when h = 3 is −
There are four levels of V _Y2 , −V _Y1 , V _Y1 , and V _Y2 . At this time, if the virtual scan electrodes are controlled so as to cause an even number of mismatches, the results are as shown in the table below.

As described above, the original voltage level can be changed from four levels to three levels. If the number of mismatches is an odd number, the corrected number of mismatches in the above table will be
The numbers become 1, 1, 3, and 3 from the top, and the corrected voltage level can be set to two levels of Va, Va, Vb, and Vb, for example.

Further, when the subgroup is h = 4 and the voltage level is not reduced, the voltage levels are, for example, -V _Y2 , -V _Y1 , 0,
Although 5 levels of V _Y1 and V _Y2 are required, the following table is obtained when the virtual scan electrodes are controlled so as to have an even number of mismatches.

As described above, the original voltage level of 5 steps can be changed to 3 steps. Also in the above case, the voltage level can be set so that the number of mismatches becomes an odd number.

Note that the above virtual scan electrode does not necessarily have to be actually provided because it does not normally need to be displayed, but when provided, it may be provided in a portion that does not affect the display. For example, in a liquid crystal display device, Display area R as shown in 13
Outside the above area, virtual scan electrodes X _{n + 1} ... Can be provided, or if there is an extra scan electrode outside the display region R, it can be used as a virtual scan electrode.

Further, the number of levels can be further reduced by increasing the number e of virtual scan electrodes. In that case, as described above, when e = 1, the number of mismatches was controlled to be divided by 2, but
For example, when e = 2, control may be performed so that the number of mismatches is all three. However, everything is divided by 3 and 1 is left,
Alternatively, two may be left over.

Furthermore, the maximum number of reductions that can be reduced by the above method is 1 / (e
+1), and when e = 1, it is 1/2 except 0V.

According to this embodiment, FIG. 12 shows three scanning electrodes and one scanning electrode at the same time.
The virtual scanning electrode of the book is selected to reduce the voltage level applied to the signal electrode, and the selection period is divided into a plurality of times for driving within one frame.

The selection period is as shown in FIG. 12 and FIG. 14 in this embodiment.
As shown in, the number of disagreements is counted for each bit of the display data for four scan electrodes including the virtual scan electrode for each period divided into four times, and the number of disagreements is always an odd number. By setting, the number of mismatches becomes 1 or 3, and the voltage level of the signal voltage waveform is correspondingly V _Y1 and −V.
_{I have} two levels of _Y1 .

Specifically, for example, when the display as shown in FIG. 13 is performed, the virtual scan electrode X _{n +} is selected next to the scan electrode X ₁ , X ₂ , X ₃ which is first selected as shown in FIG. _Suppose there is one. However, in practice, it does not have to be provided as described above,
When provided, it is desirable to provide it outside the display area R as shown in FIG.

When the voltage applied to the scan electrodes is positive, the voltage is on, and when the voltage is negative, the voltage is off.
Scan electrodes X ₁ and X ₂ selected by dividing each into three
・ The display data of X ₃ is (00), (01), (1
If it is 0), the data of the virtual scanning electrodes may be (11) as shown in FIG.

Then, the number of mismatches is counted for each bit to determine the voltage level of either V _Y1 or −V _Y1 , and the voltage for the upper bit is divided into two periods after the three divisions, and the voltage for the lower bit is divided into three. It is sufficient to apply the voltage in one period before the above. As in the third embodiment, the voltage for the upper bit may be applied in the two previous periods of the three divisions and the voltage for the lower bit may be applied in the one subsequent period of the three divisions. .

As described above, the pulse width of the voltage V _Y1 or −V _Y1 may be determined by comparing each bit according to the display data, and the number of mismatches between the polarity of the selection pulse applied to the virtual scan electrode and the display data is always constant. The voltage level applied to the signal electrode is reduced by setting the number to be an odd number such as 1, 3 ..., and can be set to 2 levels in this embodiment. However, the number of mismatches may be an even number as described above.

Further, with the above configuration, the circuit configuration of the liquid crystal driver is simple, and the same driver as the conventional pulse width modulation driver can be used.

It should be noted that, in the above-mentioned embodiment, the description is given of the 4-gradation display, but more multi-gradation display is possible, and for example, the display data is 3 bits, and each selection period is weighted to the pulse width for each bit of the display data. 8 gradations can be displayed by dividing the display data into 4 bits, and the display data is set to 4 bits, and each selection period is divided into 4 parts by weighting the pulse width for each bit of the display data, thereby providing 16 gradations. Can be displayed. By changing the number of divisions in each selection period in this way, multi-gradation display can be performed.

[Sixth Embodiment] As in the fifth embodiment, the virtual electrodes are provided to reduce the voltage level applied to the signal electrodes and then the gradation display is performed by the pulse width modulation. The present invention can be applied to the case where the scanning voltage is applied as in Example 1, and FIG. 14 is an explanatory diagram showing an example thereof.

The waveform of the voltage applied to the scan electrodes simultaneously selected is the same as that of FIG. 1 in the first embodiment as described above, and each selection period t ₁
~ T ₄ and t ₅ ~ t ₈ are each divided into _three , and the display data of the scan electrodes X ₁ , X _2, and X ₃ selected at the same time are (00),
If (01) and (10), the data of the virtual scanning electrode may be set to (11) as shown in FIG.

Then, the number of mismatches is counted for each bit to determine the voltage level, and the voltage of V _Y1 or −V _Y1 is determined for two periods of the three divisions for the upper bit and one period of the three divisions for the lower bit. It may be applied.

By doing so, the same effect as that of the fifth embodiment can be obtained.

The selection periods t _{1 to} t ₄ described above may be continuously provided in one frame F, or may be separately provided in one frame F. The same applies to the selection periods t _{5 to} t ₈ .

[Seventh Embodiment] It is also possible to perform gradation display by frame modulation after dividing the selection period and reducing the applied voltage level as described above. The number of scanning electrodes and one virtual scanning electrode are used to reduce the voltage level applied to the signal electrodes, and the selection period is driven in a plurality of times within one frame, and gradation display is performed by frame modulation. The following is an example of the case.

As the voltage applied to the scan electrodes selected at the same time,
In this embodiment, the waveform shown in FIG. 3B is used, but the waveform shown in FIG. 3A or FIG. 48A or FIG. 48B may be used.

Gradation display by frame modulation is to display the gradation depending on how many frames are turned on and how many frames are turned off in a certain frame period.For example, as shown in FIG. 16, it is turned on between F1 and between F2. When an off voltage is applied, a halftone between on and off is displayed.

Further, in the present embodiment, since the selection is made four times in one frame, the difference in brightness between the F1 period and the F2 period becomes small, and the flicker becomes inconspicuous.

For example, when grayscale display is performed for a plurality of frame periods as one block, it is possible to switch the positions of the selection pulses in the plurality of frames. For example, in FIG. 15, t ₃ and t ₇ are switched. By doing so, the difference between frames can be made smaller.

In the above embodiment, an example in which gradation display is performed by turning on one frame of two frames and turning off one frame has been described, but more frames, for example, seven frames are set as one block. It is possible to display 8 gradations depending on the combination of the number of on-frames and off-frames, and it is also possible to display 16 gradations with 15 frames as one block. 1 like this
It is possible to display an arbitrary number of gradations depending on the number of frames in one block.

[Embodiment 8] Furthermore, it is possible to perform gradation display by combining pulse width modulation and frame modulation after dividing the selection period and reducing the applied voltage level as described above.
FIG. 6 is an explanatory diagram showing an example of a procedure for performing gradation display by a combination of pulse width modulation and frame modulation.

By displaying some halftones in a certain number of frame periods, it is possible to display each grayscale data and a grayscale intermediate between the grayscale data.

For example, as shown in FIG. 18, (00) is displayed during the period of the first frame F1 and (0
By displaying 1) you are actually (00) and (01)
The middle of can be displayed.

When the selection period is divided and the applied voltage level is reduced as described above, and gradation display is performed by the combination of pulse width modulation and frame modulation, display flicker can be reduced and multi-gradation display can be performed. Is possible. Also, the selection pulses can be exchanged as in the sixth embodiment.

Further, for example, in the case where the voltage is weighted by the display data as shown in the second embodiment, the gradation display by the combination with the frame modulation as in the present embodiment is also applied to the other other embodiments or the later-described embodiments. Can also be done.

Although the fifth to eighth embodiments have been described with respect to the case where the virtual scanning electrodes are provided, even if the virtual scanning electrodes are not provided, gradation display by frame modulation or a combination of frame modulation and pulse width modulation is performed. Gradation display can be performed.

[Embodiment 9] In each of the above embodiments, four gradation display is realized by applying display signals of 2 bits and weighted signal voltages corresponding to each bit, but the number of gradations is set to any number. It is also possible to display 8 gradations as a signal electrode waveform as shown in FIG. 19, for example.

That is, FIG. 19 shows that the scan electrode waveform applied to each scan electrode in FIG.
It is a signal electrode waveform when the display data of each pixel at the intersections of X ₁ , X ₂ , X ₃ and the signal electrode Y ₁ is (001) (010) (100) in order from the top.

In this embodiment, each of the four selection periods t ₁ , t ₂ , t ₃ , t ₄ in the first embodiment is divided into three equal parts a, b, c.
Of the 3-bit display data, the voltage waveform corresponding to the most significant bit is in period a, the voltage waveform corresponding to the middle bit is in period b, and the voltage waveform corresponding to the least significant bit is In the period c, weighting is applied according to the display data of each bit in the same manner as in the first embodiment, and applied.

That is, in the period a, one is selected from the voltage levels of −V _Y6 , −V _Y4 , V _Y4 , and V _Y6 according to the display data of the most significant bit, and in period b, according to the display data of the middle bit −
Select one from the voltage levels of V _Y5 , −V _Y2 , V _Y2 , and V _Y5 , and select −V _Y3 , −V according to the least significant bit display data in period c.
Select one from the voltage levels of _Y1 , V _Y1 , and V _Y3 . The relationship between each voltage level is 4 * V _Y1 = 2 * V _Y2 = V _Y4 , 4 * V _Y3 = 2
* V _Y5 = V _Y6 , 2 * V _Y1 = V _Y3 −V _Y1 , 2 * V _Y2 = V _Y5 −V _Y2 ,
2 * V _Y4 = V _Y6 −V _Y4 .

Under these conditions, in the same manner as in the first embodiment, 8-gradation display is performed by creating a signal electrode waveform by the number of mismatches for each bit of display data.

As described above, in the first embodiment, four gradation display is performed by selecting a voltage corresponding to each period obtained by dividing the selection period into two equal parts and applying the voltage to the signal electrode, and by dividing the selection period into three equal parts in the present embodiment. 8 gradations are displayed. It is possible to increase the number of gradations by dividing the selection period into several and applying a voltage corresponding to each period to the signal electrode, such as 16 gradations by further dividing this into four. It is also possible to adjust the luminance at each gradation by changing the voltage ratio of each signal electrode or slightly changing the selection period instead of dividing it equally.

[Embodiment 10] In FIG. 19 of Embodiment 9 described above, in gradation display by changing the voltage applied to the signal electrode, each bit is divided into periods a, b, and c divided according to the number of bits of display data. The corresponding voltage is applied in order from the upper bit, but the order can be changed appropriately for each signal electrode.

In the ninth embodiment, for example, the display of each pixel where the scan electrodes X ₁ , X ₂ , X ₃ and the signal electrodes Y _{2 to} Y _m intersect is
If it is the same as the display of the pixel where X ₁ , X ₂ , X ₃ and the signal electrode Y ₁ intersect, the signal voltage waveforms applied to the signal electrodes Y _{1 to} Y _m are all the same as the waveform shown in FIG. 19. Become. However, in such a case, the summary of the waveform applied to each pixel becomes large and the display quality deteriorates.

Therefore, in this embodiment, as shown in FIG. 20, the signal electrode waveforms applied to the respective signal electrodes Y _{1 to} Y _m are switched in order.

That is, in the ninth embodiment, the voltage corresponding to the most significant bit of the 3-bit display data is in the period a, the voltage corresponding to the middle bit is in the period b, and the voltage corresponding to the least significant bit is in the period c. , In that order, to the signal electrode Y ₁ . The same applies to the other signal electrodes Y _{1 to} Y _m .

On the other hand, in this embodiment, as shown in FIG.
Assuming that the period for applying the voltage to the most significant bit is a, the period for applying the voltage to the middle bit is b, and the period for applying the voltage to the least significant bit is c, for example, in the signal electrode Y ₁ as in the second embodiment. A / b /
If the voltage is applied in the order of c, the order is appropriately changed in the next signal electrode, and for example, in the signal electrode Y ₂ , a.c.b and the signal electrode Y _{3 are applied.}
B ・ a ・ c, signal electrode Y ₄ b ・ c ・ a, signal electrode
The above-mentioned combination is repeated for the other signal electrodes Y _{7 to} Y _m , which are applied in the order of c · a · b for Y _{5 and} c · b · a for the signal electrode Y ₆ .

With the above arrangement, in the above-described embodiment, the waveforms of six different combinations in different orders are applied to the signal electrodes in substantially the same number, so that the influences of the rising and falling edges of the waveforms of the signal electrodes cancel each other out. The summary of the applied waveform can be reduced.

Any combination of waveforms may be applied to each signal electrode. For example, if there are six signal electrode drivers, each combination of waveforms may be applied to each signal electrode driver. In this way, the display quality can be improved by making the combinations of the waveforms applied to the respective signal electrodes approximately the same.

Further, as described above, applying the voltage corresponding to each bit of the display data by appropriately exchanging it for each of the signal electrodes Y _{1 to} Y _m can be applied to each of the above-described embodiments and the embodiments described later.

[Embodiment 11] In the above-described Embodiment 9, eight gradations are displayed using the waveform as shown in FIG. 1A, that is, FIG. 3B, as the scanning voltage waveform applied to the scanning electrodes. It is also possible to use the waveform of FIG. 3 (a) or the conventional example of FIG. 48 (a) or (b). In the following, 8-level display is performed using the waveform shown in FIG. 3 (a). Will be described in more detail by taking as an example.

FIG. 21 shows the applied voltage of the embodiment in which eight gradations are displayed based on the display data shown in FIG. 22 using the waveform shown in FIG. 3A as the scanning voltage waveform applied to the simultaneously selected scan electrodes. It is a waveform diagram, the figure (a) is a scan electrode X ₁ X ₂ X ₃
, A scanning voltage waveform applied to the signal electrode, a signal voltage waveform applied to the signal electrode Y ₁ and a scanning voltage waveform applied to the pixel where the scanning electrode X ₁ and the signal electrode Y ₁ intersect. The voltage waveform is shown.

Also in this example, three scanning electrodes are sequentially selected and driven at the same time, and only three scanning electrodes X ₁ , X _2, and X ₃ are shown in FIG. 21, but as shown in FIG. After the scan electrodes X ₁ , X _2, and X ₃ are selected, the next three scan electrodes
When X ₄ , X _5, and X ₆ are selected and the same voltage as that of the scan electrodes X ₁ , X _2, and X ₃ is applied, and in the same manner, three scan electrodes are sequentially selected and all scan electrodes are selected. One frame ends.

Further, as described above, the scanning voltage waveform shown in FIG. 3A is applied to the three scanning electrodes selected at the same time, and the minimum pulse width Δt thereof is the same as in the conventional example of FIG. Twice the minimum pulse width Δt ₀ ,
All the selection periods t in one frame of each scan electrode are composed of _four periods t _{1 to} t 4 having the pulse width Δt.

The above four periods t _{1 to} t ₄ are divided into three periods a, b, and c according to the number of bits of display data, and a predetermined weight is assigned to each divided period corresponding to the bits of display data. The applied signal voltage is applied to the signal electrode.

That is, in FIG. 22, the upper bit of the display data represented by a three-digit number in the binary system in the _first divided period a of each period t _{1 to} t ₄ , the central bit in the next divided period b, the lower bit To the last divided period c, with ± V _Y4 or ± V _Y6 with predetermined weighting for the upper bits, ± V _Y2 or ± V _Y5 for the central bits, and for the lower bits. Then, ± V _Y1 or ± V _Y3 is applied according to the conditions described later.

The above voltage value ratio is set to V _Y1 : V _Y2 : V _Y4 = 1: 2: 4 V _Y3 : V _Y5 : V _Y6 = 1: 2: 4 V _Y1 : V _Y3 = 1: 3 There is.

As the above conditions, when the scanning voltage waveform applied to the scanning electrodes is on the positive side, it is turned on, when it is on the negative side, it is turned off, and 1 of the display data is turned on and 0 is turned off. The on / off and on / off of the same bit of the display data of the intersection with the signal electrode to be applied on the selected scan electrode are sequentially compared for each position, and a predetermined voltage is determined according to the number of mismatches. Is applied to the signal electrode.

Specifically, in this example, when the number of mismatches between the scan electrodes and the upper bits is 0, -V _Y6 , 1 is -V _Y4 , 2 is V _Y4 , and 3 is V _Y6 , respectively. When the number of disagreements between the scan electrode and the central bit is 0, -V _{Y5 is applied} , 1 is -V _Y2 , 2 is V _Y2 , and 3 is V _Y5. When the number of disagreement with the lower bit is 0, -V _{Y3 is applied} , 1 is applied-V _Y1 , 2 is applied V _Y1 , and 3 is applied V _Y3 .

Therefore, in the embodiment of FIG. 21, first, three scan electrodes X ₁ , X _2, and X ₃ are simultaneously selected, and the selected scan electrodes X ₁ , X _2, and X ₃ are turned off, off, and on in order. , Its scanning electrodes
The upper bits of the display data of the intersection with the signal electrode Y ₁ on X ₁ , X _2, and X ₃ are OFF, ON, and ON in order, and when the two are compared in order, the number of mismatches is 1, and the first period t ₁ In the first divided period a, the voltage of −V _Y4 is applied to the signal electrode Y ₁ . Voltages weighted in the same manner are simultaneously applied to the other signal electrodes Y _{2 to} Y _m .

Next, in the next divided period b of the first period t ₁ , the on / off of the scan electrodes X ₁ , X _2, and X ₃ is the same off / off / on as above, and in the divided period b. Since the corresponding central bits are on / off / off in sequence, the number of mismatches is 2 and the voltage of V _Y2 is applied, and the lower bits for the last divided period c are off / on / off. At 2 V _Y1 is applied.

With respect to the next period t _2, the on-off on the scanning electrodes X ₁ · X ₂ · X ₃ is sequentially off-on-off, on the scanning electrode X ₁ · X ₂ · X ₃ contrast The upper bit of the display data at the intersection with the signal electrode Y ₁ is OFF / ON / ON in the same manner as above, and the number of mismatches is 1, so −V _Y4 is the center bit is ON / OFF / OFF in order, and the number of mismatches is V _{Y2 because} it is ₂
Since the lower bit is off / on / off and the number of mismatches is 0, the voltage of -V _Y3 is divided into the divided periods a and b, respectively.
-In c, it is sequentially applied to the signal electrode Y ₁ .

Further, also in the next periods t ₃ and t ₄ , the signal voltage corresponding to the number of mismatches is applied to all the signal electrodes Y _{1 to} Y _{m in} the same manner as above.
Are simultaneously applied to complete the selection of the scan electrodes X ₁ , X _2, and X ₃ , and then the scan electrodes X ₄ , X _5, and X ₆ are selected, and the signal electrodes Y _{1 to} Y _m are selected in the same manner as above. A predetermined signal voltage is applied to
One frame F where all scan electrodes are selected
Ends. After that, the _first scan electrodes X ₁ , X ₂ , X ₃ are selected again in order and the next frame is started.At that time, the positive and negative of the voltage applied to the scan electrodes are inverted, and the signal electrodes are accordingly changed. The so-called AC drive is performed by inverting the positive / negative of the voltage applied to the.

Note that the above voltage ratio does not necessarily have to strictly meet the above conditions, and the period t _{1 to} t ₄
The divided periods a, b, and c do not necessarily have to be strictly divided into equal parts, and may be appropriately adjusted according to, for example, the characteristics of the liquid crystal. Furthermore, the divided period a
The order of b and c may be exchanged. It is also possible to perform display with various numbers of gradations in the same manner as described above. For example, with 16 gradations, a voltage weighted corresponding to each bit of display data represented by 4 bits may be used. The following points are the same for the examples described later.

Twelfth Embodiment In the eleventh embodiment, the selection period t of each scanning electrode is collectively provided once within one frame F, but it may be provided at a plurality of times within one frame F.

For example, the above-mentioned periods t _{1 to} t ₄ may be divided into one field until all scan electrodes are selected in each period, and this may be repeated four fields in one frame F, or It may be further divided and repeated for all the scan electrodes for each bit of the display data. 24, 26 and 27 show an example thereof.

FIG. 24 is a waveform diagram of applied voltage showing an embodiment of driving in a plurality of times for each of the _four periods t _{1 to} t 4 in the eleventh embodiment.
Reference numeral 25 is a scan voltage waveform diagram applied to the scan electrodes X _{1 to} X ₆ .

First, the scan electrodes X ₁ , X _2, and X ₃ are selected, and
A signal voltage corresponding to the number of mismatches with the three bits is sequentially applied to the signal electrodes Y _{1 to} Y _{m in the same} manner as in, and then the scanning electrodes
X ₄ , X _5, and X ₆ are selected, the signal voltage is applied in the same manner as above, and when all the scan electrodes are selected, the field f ₁ for the period t ₁ ends. Next, the scan electrodes X ₁ , X ₂ , X ₃ are selected again in order from the _first scan electrode, and the next period
Field f ₂ is performed with respect to t _2, 4 two periods t ₁ ~t ₄
Where the _four fields f _{1 to} f ₄ for
One frame F is completed.

In FIG. 26, the process is executed collectively for each bit of the display data, that is, for each divided period of the _four periods t _{1 to} t 4 in the above embodiment.

First, the first divided periods a in the _four periods t _{1 to} t 4 of FIG. 1 are collectively grouped in order to form one field f ₁ until all scan electrodes are selected, and other divided periods are similarly set. One frame is formed until the field f ₂ for b and the field f ₃ for divided period c are finished. The voltage applied to the scan electrodes is inverted for each field, and the voltage applied to the signal electrodes is also inverted accordingly.

FIG. 27 is further subdivided into divided periods a, b, and b in FIG.
This is performed for all scan electrodes for each c. In the present example, the embodiment of FIG. 21 can be regarded as equivalent to the frame gradation for each bit of the display data.

As described above, when the scanning electrode selection period is divided into a plurality of times within one frame F, the period during which the selection voltage is not applied to each scanning electrode, that is, each pixel can be shortened, so that increase or decrease in display brightness is reduced. As a result, it is possible to prevent the deterioration of the contrast.

[Embodiment 13] In Embodiment 11, one selection period is divided into the same number as the grayscale bit number n, that is, divided into three, and signal voltages of six levels V _{Y1 to} V _Y6 are selectively applied to the signal electrodes. However, the number of signal voltage levels can be reduced by increasing the number of divisions.

For example, the effective voltage when driving a liquid crystal element such as a liquid crystal display panel is generally determined by the voltage value and the application time (pulse width). Even if a high voltage is applied for a short time, a low voltage is applied for a long time. Can be driven equally.

Therefore, it is possible to use the lower level voltage of the plurality of voltage levels instead of the higher level voltage and to drive them equally even if the application time is extended. V _Y6 and V in Example 1
Instead of using the voltage level of _Y4 , respectively V _Y5 and V _Y2
Even if the voltage level is used and the application time is extended, the driving can be performed as in the case of the first embodiment. As a result, the number of signal voltage levels can be reduced.

FIG. 28 is an applied voltage waveform diagram showing an embodiment in which the number of signal voltage levels is reduced in the above manner.

In the case of FIG. 21, the four selection periods t ₁ , t ₂ , t ₃ , and t ₄ are divided into n, that is, a, b, and c, respectively, according to the number of bits of display data. In the present embodiment, each of the above selection periods is divided into n + 1, that is, four of a.a.b.c, and the first two divided periods a.a are applied to the voltage application time of the upper bit of the display data. Is.

That is, instead of the voltage levels V _Y6 and V _Y4 for the upper bits in the eleventh embodiment, the voltage levels V _Y5 and V _Y2 of the intermediate bit having a half size thereof are used,
The application time is set to be twice as long as the intermediate bit. As a result, the voltage value applied to the liquid crystal element and the time become twice the intermediate bit and four times the lower bit, and the weighting ratio for each bit is 1 as in the case of FIG. : 2: 4.

With the above arrangement, the voltage level applied to the signal electrode is reduced by one as compared with the case of the eleventh embodiment, and then the first embodiment.
It can be driven in the same manner as in the case of.

In this embodiment, the two highest voltage levels V _Y6 and V _Y4 in the eleventh embodiment are omitted.
The voltage level V for the intermediate bit in the eleventh embodiment
Lower bit voltage level V _Y3 · V instead of _{Y 5} and V _Y2
Each _Y1 may be used, and the application time thereof may be doubled as that of the lower bit in the same manner as described above. Furthermore, it is also possible to reduce the voltage level of 4 or more, and reducing the voltage level as described above is effective in simplifying the configuration of the drive circuit and the like especially when the number of gradations is large. .

[Embodiment 14] Also in Embodiment 13 described above, it is possible to execute the divided selection periods t _{1 to} t ₄ in a plurality of times within one frame F, as in Embodiment 12, as shown in FIG. 30 and 31 show an example thereof.

FIG. 29 shows that one selection period in the above-described thirteenth embodiment is n + 1, specifically, a selection period divided into four is divided into a plurality of fields within one frame as in the case of the twelfth embodiment, specifically four times of fields. It is divided into f and executed. However, it can be divided into two or three times.

Figure 20 is obtained by such run are summarized for each divided period of the four periods t ₁ ~t ₄ in the embodiment, divided period a four periods t ₁ ~t ₄ of FIG 21, The first divided period “a” of “a” is grouped in order, and one field f ₁ is set until all the scanning electrodes are selected. Similarly, the field f ₂ for the next divided period “a” and the divided period One frame F ₁ is formed until the end of the field f ₃ for b and the field f ₄ for the divided period c. The voltage applied to the scan electrodes is inverted for each field, and the voltage applied to the signal electrodes is also inverted accordingly.

FIG. 31 is further subdivided into divided periods a.a.
This is executed for all scan electrodes for each of b and c.

The embodiments of FIGS. 30 and 31 can be regarded as equivalent to the frame gradation in which the applied voltage to the signal electrode is weighted for each field.

Fifteenth Embodiment As described above, the effective voltage when driving a liquid crystal element or the like is generally determined by the voltage value applied and the application time (pulse width), and the voltage value of the applied voltage to the signal electrode and the applied voltage. A desired gradation display can be performed by appropriately combining with time.

FIG. 32 is an applied voltage waveform diagram of an example in which 16 gradations are displayed based on the display data shown in FIG. 33 by appropriately combining the voltage value of the applied voltage to the signal electrode and the application time.

Also in this embodiment, three scanning electrodes are sequentially selected, and a scanning voltage is applied to each scanning electrode within the selection period consisting of _four periods t _{1 to} t 4 as in the first embodiment.

The above four periods t _{1 to} t ₄ are replaced by six periods a to
f and divide the first two divided periods a and b into the most significant bit of the binary 4-digit display data shown in FIG. 33, the next divided period c into the second bit, and the next two divided periods. Divided period d ・ e
To the third bit and the last divided period f to the least significant bit.

Then, a signal voltage of ± V _Y4 or ± V _Y6 is applied to the upper two bits, and ± V _Y1 is applied to the lower two bits.
Alternatively, a signal voltage of ± V _Y3 is selectively applied to the signal electrodes according to the conditions described later.

The ratio of the above voltage values is set to V _Y1 : V _Y3 = 1: 3 V _Y4 : V _Y6 = 1: 3 V _Y1 : V _Y4 = 1: 4.

As described above, the same two sets of voltages are used for the upper two bits and the lower two bits, and the most significant bit for the second highest bit and the second least significant bit for the lowest bit are Each is weighted by doubling the pulse width, and 4 gradations are expressed by the upper 2 bits and 4 gradations are expressed by the lower 2 bits, and both can be multiplied to express 4 × 4 = 16 gradations. .

As the above conditions, when the voltage waveform of the scan electrode is on the positive side, it is turned on, when it is on the negative side, it is turned off, 1 of the display data is turned on, 0 is turned off, and the selected scan electrode is turned on and off at the same time. , Turning on the same bit of the display data of the intersection of the selected scan electrode and the signal electrode to be applied
OFF is sequentially compared for each position, and a predetermined voltage is applied to the signal electrode according to the number of mismatches.

Specifically, in this example, -V _Y6 when the number of mismatches between the scan electrode and the most significant bit is 0, -V _Y4 when 1 and -V _Y4 , 2
, V _Y4 for 3 and V _Y6 for 3, respectively divided periods a and b
Then, the same voltage is applied to the signal electrode in the divided period c under the same conditions as above with respect to the number of mismatches between the scanning electrode and the second bit. When the number of disagreement between the scan electrode and the third bit is 0, -V _Y3 , when it is ₁ , -V _Y1 ,
When it is 2, V _Y1 and when it is 3, V _Y3 is applied to the signal electrode in the divided period d · e, and the same voltage is applied in the divided period under the same conditions as above for the number of mismatch between the scan electrode and the least significant bit. It is applied to the signal electrode at f.

Therefore, in FIG. 32, first, three scan electrodes X ₁
X ₂ and X ₃ are simultaneously selected, and the selected scan electrode X ₁ and
The scan voltage waveforms of X ₂ and X ₃ are turned off, then turned on, and the most significant bit of the display data at the intersection with the signal electrode Y ₁ on that scan electrode X ₁ , X _2, and X ₃ is turned off and off in order. It is on, and when the two are compared in order, the number of mismatches is 0, and the voltage of −V _Y6 is applied to the signal electrode Y ₁ in the first divided periods a and b of the first period t ₁ .

Next, the second bit from the top is OFF / ON / OFF, and the number of mismatches is 2 in comparison with the OFF / OFF / ON of the scan electrodes X ₁ , X ₂ , X ₃ , and the voltage of V _Y4 is applied in the divided period c. The second bit is ON / OFF / OFF, the number of mismatches is 2 and V _Y1 is applied to the divided period d · e, and the least significant bit is OFF / ON / OFF and the number of mismatches is 2 and V _Y1 is applied. Has been done. Voltages weighted in the same manner are simultaneously applied to the other signal electrodes Y _{2 to} Y _m .

In this way, also in the next period t _{2 to} t ₄ , the signal voltage corresponding to the number of mismatches is applied to all the signal electrodes Y _{1 in} the same manner as above.
To Y _m at the same time, the selection of the scan electrodes X ₁ , X _2, and X ₃ is completed, and then the scan electrodes X ₄ , X _5, and X ₆ are selected, and the signal electrode Y ₁ is selected in the same manner as above. One frame F ends when a predetermined signal voltage is applied to Y _m and all the scan electrodes are selected. After that, the _first scan electrodes X ₁ , X ₂ ,
When the next frame is started by sequentially selecting from X _3, the positive and negative of the voltage applied to the scan electrode at that time is inverted, and the positive and negative of the voltage applied to the signal electrode is also inverted accordingly, so-called AC drive is performed.

As described above, a desired gradation display can be performed by appropriately combining the voltage value of the voltage applied to the signal electrode and the time. Even when the number of gradations is large, gradation display can be performed with a small voltage level. It becomes possible to do.

As described above in the eleventh embodiment, the voltage ratio does not necessarily have to be strictly set to the above condition, and the periods t _{1 to} t ₄ and the divided periods a to f are not always exactly equal. It does not have to be divided. The order of the divided periods a to f may be changed appropriately.

[Embodiment 16] In Embodiment 15 as well, similar to Embodiment 12, the selection period can be divided into a plurality of times within one frame F and executed.

Figure 34 shows an example of this, and the period in Figure 32 above.
As in the case of the second embodiment, t _{1 to} t ₄ are separately divided into 4 in one frame F, and 4 in one frame F until all scan electrodes are selected for each period.
It is designed to be repeated once.

Although not shown in the drawing, also in the fifteenth embodiment, as in the case of the fourteenth embodiment shown in FIGS. 30 and 31, the display data can be driven bit by bit or further subdivided.

Example 17 In Examples 11 to 16 described above, the signal electrodes are weighted with respect to the bits of the display data, that is, gradation display is performed by changing the voltage level applied to the signal electrodes, but the scanning electrodes are weighted. That is, gradation display can be performed by changing the voltage level applied to the scan electrodes.

FIG. 35 is a waveform diagram of an applied voltage of an embodiment in which the voltage level applied to the scan electrodes is changed according to the bit of the display data and eight gradations are displayed based on the display data of FIG. 22 as in the eleventh embodiment. Is.

As in the case of the eleventh embodiment, three scanning electrodes are sequentially selected, and each scanning electrode is selected for the upper bit of the display data.
V _X4 or --V _X4 and V _X2 or --V for center bit
_X2 is applied to V _X1 or −V _X1 for the lower bits, respectively, and V _X1 : V _X2 : V _X4 is set to have a relationship of 1: 2: 4.

On the other hand, for the signal electrodes Y _1, ..., On / off of the scan electrodes X ₁ , X ₂ , X ₃ and on / off of the display data are compared for each bit, and when the number of mismatches is 0, −V _{When Y3} is 1, -V _Y1
, V _Y1 is applied when 2, and V _Y3 is applied when 3, and V _Y1 : V _Y3 is set to have a relationship of 1: 3.

If the voltage level on the scan electrode side is increased as in the present embodiment instead of increasing the voltage level on the signal electrode side as in the eleventh embodiment, the number of voltage levels applied to the signal electrode is significantly reduced. Therefore, there is an advantage that the circuit configuration of the driver on the signal electrode side can be simplified.

[Embodiment 18] In Embodiment 17 as well, similar to Embodiment 12, the selection period can be divided into a plurality of times within one frame F and executed. 36, 37, and 38 show an example thereof.

36. In FIG. 36, the periods t _{1 to} t ₄ in FIG. 35 are divided into four in each one frame F as in the case of the twelfth embodiment, and one field f is set until all the scanning electrodes are selected in each period. Is repeated four times within one frame F.

In FIG. 37, the process is executed collectively for each bit of the display data, that is, for each divided period of the _four periods t _{1 to} t 4 in the above embodiment.

That is, the _first divided periods a in the _four periods t _{1 to} t 4 in FIG. 35 are collectively grouped in order to form one field f ₁ until all scan electrodes are selected, and the other divided periods b are similarly set. For one field until the end of the field f ₂ for the divided period and the field f ₃ for the divided period c. The voltage applied to the scan electrodes is inverted for each field, and the voltage applied to the signal electrodes is also inverted accordingly.

In FIG. 38, all the scanning electrodes are sequentially selected and driven for each divided period a, b, and c by further subdividing.

As described above, the same effect as that of the twelfth embodiment can be obtained by driving in a plurality of times within one frame.

[Embodiment 19] In Embodiment 17, as in Embodiment 13, the number of divisions of the selection period can be increased to reduce the number of applied voltage levels.

FIG. 39 shows an example thereof, in which each period t _{1 to} t ₄ in FIG. 35 is divided into four in one frame F as in the case of FIG. 28, and the first two divided periods are applied to the upper bit. In addition, the other divided periods are applied times for the intermediate bit and the lower bit, respectively. In this embodiment, the relationship between the applied voltages is V _X1 : V _X2 = 1: 2, V _Y1 : V _Y3 =
It is set to 1: 3.

[Embodiment 20] Also in Embodiment 19, the selection period can be divided into a plurality of times within one frame F and executed. Figure 40, Figure 41, Figure
42 shows an example thereof.

In FIG. 40, each period t _{1 to} t ₄ in FIG. 39 is divided into four times in one frame F as in the case of FIG. 25, and one field f is defined as one field f until all scan electrodes are selected. This is repeated four times in the frame F.

41. FIG. 41 shows a case in which the divided periods of the _four periods t _{1 to} t 4 in the above embodiment are collectively executed.
Sequentially and one field f ₁ up to all the scan electrodes are collectively is selected the start of a division period a of the divided period a · a four within the period t ₁ ~t ₄ in the following in the same way The field f ₂ for the divided period a, the field f ₃ for the divided period b, and the field f ₄ for the divided period c are completed as one frame. The voltage applied to the scan electrodes is inverted for each field, and the voltage applied to the signal electrodes is also inverted accordingly.

In FIG. 42, the selection period of FIG. 41 is further subdivided so that all the scanning electrodes are sequentially selected and driven for each divided period.

As described above, the same effect as that of the twelfth embodiment can be obtained by driving in a plurality of times within one frame.

Example 21 In the same way as in Example 16 in the case of performing a desired gradation display by appropriately combining the voltage value of the voltage applied to the electrodes and the application time as in Example 15, the signal electrode side By increasing the voltage level on the scan electrode side instead of increasing the voltage level, the same driving as in Example 15 can be performed.

FIG. 43 shows an example thereof. In this example, the applied voltage level to the scan electrode is V _X4 or −V _X4 for the upper two bits of the display data in FIG. 13 and V _X1 or −V _X1 for the lower two bits. , Respectively, and V _X1 : V _X4 are set to have a relationship of 1: 4.

On the other hand, for the signal electrodes Y _1, ..., On / off of the scan electrodes X ₁ , X ₂ , X ₃ and on / off of the display data are compared for each bit, and when the number of mismatches is 0, −V _{When Y3} is 1, -V _Y1
, V _Y1 is applied when 2, and V _Y3 is applied when 3, and V _Y1 : V _Y3 is set to have a relationship of 1: 3.

[Embodiment 22] Also in Embodiment 21, the selection period can be divided into a plurality of times within one frame F and executed.

FIG. 44 shows an example thereof, and each period t _{1 to} t ₄ in FIG. 41 is divided into four times in one frame F as in the case of FIG. 24, and all the scanning electrodes are selected in each period. Are defined as one field f and repeated four times in one frame F. Also in this example, as in the case of the above-described example, the drive can be further subdivided and driven.

Although not shown in the figure, also in the twenty-first embodiment, the display data can be driven bit by bit or further subdivided as in the case of FIGS. 41 and 42 in the twenty embodiment.

In the above embodiments, the case where three scan electrodes are selected at a time has been described as an example, but two or four or more scan electrodes can be selected at the same time in the same manner according to the above-mentioned concept. It is possible to perform gradation display of the number of gradations. For example, an example of simultaneously selecting six scan electrodes is shown. Six scan electrodes X ₁ selected at the same time are provided by providing eight selection periods t ₁ to t ₈ during one frame period.
The voltage as shown in the table below is applied during each selection period t _{1 to} t ₈ of X ₆ to X ₆ .

Note that 0 volt is applied during the non-selection period. A predetermined scan voltage is applied to each scan electrode X _{1 to} X ₆ as described above, and at the same time, a predetermined signal voltage may be applied to each signal electrode in the same manner as in each of the above embodiments. .

Further, the waveform of the voltage applied to the scanning electrodes is not limited to the above-mentioned respective embodiments, and may be changed to, for example, any of (a) and (b) in FIG. 48 or (a) and (b) in FIG. The pulse waveforms such as the above may be appropriately selected, or the arrangement order may be appropriately exchanged, and it is only necessary that the waveforms applied to the scan electrodes simultaneously selected can be driven separately without being confused with each other.

Further, as described above, it is possible to drive a liquid crystal element or the like using a non-linear element such as a MIM element by sequentially selecting a plurality of scanning electrodes at the same time and driving the selection period in a plurality of times in one frame. It is also applicable when doing.

INDUSTRIAL APPLICABILITY As described above, the liquid crystal device, the driving method, and the driving circuit according to the present invention sequentially select a plurality of scan electrodes at the same time, and divide one selection period into a plurality of periods. In each divided selection period, a voltage weighted according to desired display data is applied to perform gray scale display, so that the time during which the selection voltage is not applied to the pixels becomes long and the contrast decreases, It is possible to prevent flickering due to a long repetition period, or to prevent crosstalk due to rounding of the waveform of the applied voltage, and to perform good gradation display. In addition, it is possible to reduce the number of applied voltage levels instead of the number of gray scales, to easily configure a driving means such as a driver, and to provide a liquid crystal device excellent in reliability and display performance, a driving method thereof, and a driving circuit. There is an effect that it can be provided.

─────────────────────────────────────────────────── ─── Continuation of the front page Preliminary examination (56) References JP-A-5-100642 (JP, A) T.S. N. RUCKMONGATHA N, A GENERALIZED AD DRESSING TECHNIQUE FOR RMS RESPONDIN G MATRIX LCDS, CONF ERENCE RECORD OF T HE 1988 INTERNATIONA L DISPLAY RESEARCH CONFERENCE, the United States, 1988, 80-85 (58) investigated the field (Int.Cl. ^7, DB Name) G09G 3/36 G02F 1/133 505 G09G 3/20 622

Claims (18)

(57) [Claims] 1. A plurality of scan electrodes, a plurality of signal electrodes intersecting the plurality of scan electrodes, and a substrate on which the scan electrodes are formed and a substrate on which the signal electrodes are formed. In a liquid crystal device including a liquid crystal, the plurality of scan electrodes are divided into subgroups, the scan electrodes in the subgroups are simultaneously selected, a scan voltage is applied to the simultaneously selected scan electrodes, and the scan electrodes are The scanning voltage selected at the same time is applied in each of a plurality of small selection periods provided at intervals in one frame, the small selection period is divided into a plurality of periods, in each divided period, The scan voltage is applied to the scan electrodes selected at the same time, and a value according to the data to be displayed and a value according to the scan voltage applied in each of the divided periods. A signal voltage corresponding to the number of matches and the number of mismatches is applied to the signal electrode, the data to be displayed has a constant value in the one frame, and the scan voltage and the signal are included in the small selection period. A gray scale display is performed by applying a voltage based on the voltage between the electrodes. 2. The liquid crystal device according to claim 1, wherein the signal voltage weighted based on the data to be displayed is applied to the signal electrode. 3. The liquid crystal device according to claim 1, wherein the scanning voltage having a plurality of voltage values weighted based on the data to be displayed is applied to the scanning electrodes. 4. A plurality of scan electrodes, a plurality of signal electrodes intersecting the plurality of scan electrodes, and a substrate on which the scan electrodes are formed and a substrate on which the signal electrodes are formed. In a liquid crystal device including a liquid crystal, the plurality of scan electrodes are divided into subgroups, the scan electrodes in the subgroup are simultaneously selected, a selection period is divided into a plurality of periods, and in each divided period, A scan voltage is applied to the simultaneously selected scan electrodes, data to be displayed is represented by a plurality of bits, and each bit of the plurality of bits and a waveform of the scan voltage are represented in each of the divided periods. A liquid crystal device, wherein a signal voltage set based on the signal voltage is applied to the signal electrode. 5. The number of voltage levels of the signal voltage applied to the signal electrode is reduced as compared with the case where a virtual scanning electrode is included as the scanning electrode in the subgroup and the virtual scanning electrode is not included. The liquid crystal device according to claim 1, wherein the liquid crystal device is a liquid crystal device. 6. The scan electrode selected at the same time is three, and the number of voltage levels of the signal voltage applied to the signal electrode is two, according to any one of claims 1 to 5. Liquid crystal device. 7. A plurality of scan electrodes, a plurality of signal electrodes intersecting the plurality of scan electrodes, and a substrate on which the scan electrodes are formed and a substrate on which the signal electrodes are formed. In a method of driving a liquid crystal device including a liquid crystal, the plurality of scan electrodes are divided into subgroups, the scan electrodes in the subgroups are simultaneously selected, and a scan voltage is applied to the scan electrodes that are simultaneously selected, and the scan is performed. The scanning voltage for simultaneously selecting electrodes is applied in each of a plurality of small selection periods provided at intervals in one frame, the small selection period is divided into a plurality of periods, and each divided period is divided. And applying the scan voltage to the simultaneously selected scan electrodes, and a value according to the data to be displayed and a value according to the scan voltage applied in each of the divided periods. A signal voltage corresponding to the number of matches and the number of mismatches is applied to the signal electrode, the data to be displayed is a constant value in the one frame, and the scan voltage and the signal are included in the small selection period. A method for driving a liquid crystal device, wherein gradation display is performed by applying a voltage based on the voltage between the electrodes. 8. The method of driving a liquid crystal device according to claim 7, wherein the signal voltage weighted based on the data to be displayed is applied to the signal electrode. 9. The method of driving a liquid crystal device according to claim 7, wherein the scan voltage composed of a plurality of voltage values weighted based on the data to be displayed is applied to the scan electrodes. 10. A method of driving a liquid crystal device, comprising: a plurality of scan electrodes; a plurality of signal electrodes intersecting the plurality of scan electrodes; and a liquid crystal sandwiched between the respective scan electrodes and the respective signal electrodes. , Dividing the plurality of scan electrodes into subgroups, simultaneously selecting the scan electrodes in the subgroup, dividing the selection period into a plurality of periods, and simultaneously selecting the scan voltage in each of the divided periods. A signal voltage applied to the scan electrodes to represent the data to be displayed by a plurality of bits, and set in each of the divided periods based on each bit of the plurality of bits and the waveform of the scan voltage. Is applied to the signal electrode. A method of driving a liquid crystal device. 11. The number of voltage levels of the signal voltage applied to the signal electrode is reduced as compared with a case where a virtual scanning electrode is included as the scanning electrode in the subgroup and the virtual scanning electrode is not included. 11. The method for driving a liquid crystal device according to claim 7, which is characterized in that. 12. The scanning electrode selected at the same time is three in number, and the number of voltage levels of the signal voltage applied to the signal electrode is two, according to claim 7. Driving method of liquid crystal device. 13. A drive circuit for a liquid crystal device, comprising: a plurality of scan electrodes; a plurality of signal electrodes intersecting the plurality of scan electrodes; and a liquid crystal sandwiched between the respective scan electrodes and the respective signal electrodes. , Dividing the plurality of scan electrodes into subgroups, simultaneously selecting the scan electrodes in the subgroup, applying a scan voltage to the scan electrodes selected at the same time, and the scan voltage selecting the scan electrodes at the same time, It is applied in each of a plurality of small selection periods provided at intervals in one frame, the small selection period is divided into a plurality of periods, and the scanning voltage is simultaneously selected in each of the divided periods. Applied to the scan electrodes and corresponds to the number of coincidences and the number of disagreements between the value according to the data to be displayed and the value according to the scan voltage applied in each of the divided periods. A signal voltage is applied to the signal electrodes, the data to be displayed is a constant value in the one frame, and a voltage based on the scan voltage and the signal voltage is applied between the electrodes during the small selection period. A drive circuit of a liquid crystal device, which performs gradation display by applying a voltage. 14. The drive circuit for a liquid crystal device according to claim 13, wherein the signal voltage weighted based on the data to be displayed is applied to the signal electrode. 15. The drive circuit for a liquid crystal device according to claim 13, wherein the scan voltage composed of a plurality of voltage values weighted based on the data to be displayed is applied to the scan electrodes. 16. A drive circuit for a liquid crystal device, comprising: a plurality of scan electrodes, a plurality of signal electrodes intersecting the plurality of scan electrodes, and a liquid crystal sandwiched between the respective scan electrodes and the respective signal electrodes. , Dividing the plurality of scan electrodes into subgroups, simultaneously selecting the scan electrodes in the subgroup, dividing the selection period into a plurality of periods, and simultaneously selecting the scan voltage in each of the divided periods. A signal voltage applied to the scan electrodes to represent the data to be displayed by a plurality of bits, and set in each of the divided periods based on each bit of the plurality of bits and the waveform of the scan voltage. Is applied to the signal electrode, a drive circuit of a liquid crystal device. 17. The number of voltage levels of the signal voltage applied to the signal electrode is reduced as compared with the case where a virtual scanning electrode is included as the scanning electrode in the subgroup and the virtual scanning electrode is not included. 17. The drive circuit for a liquid crystal device according to claim 13, wherein the drive circuit is a liquid crystal device. 18. The scanning electrode selected at the same time is three, and the number of voltage levels of the signal voltage applied to the signal electrode is two, according to any one of claims 13 to 17. Liquid crystal device drive circuit.