EP0806780B1 - Zink-Phosphatbeschichtung für Varistor und Verfahren zur Herstellung - Google Patents

Zink-Phosphatbeschichtung für Varistor und Verfahren zur Herstellung Download PDF

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Publication number
EP0806780B1
EP0806780B1 EP96400993A EP96400993A EP0806780B1 EP 0806780 B1 EP0806780 B1 EP 0806780B1 EP 96400993 A EP96400993 A EP 96400993A EP 96400993 A EP96400993 A EP 96400993A EP 0806780 B1 EP0806780 B1 EP 0806780B1
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EP
European Patent Office
Prior art keywords
oxide
electrically conductive
phosphoric acid
zinc
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP96400993A
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English (en)
French (fr)
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EP0806780A1 (de
Inventor
Palaniappan Ravindranathan
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Littelfuse Inc
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Littelfuse Inc
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Priority to AT96400993T priority Critical patent/ATE195198T1/de
Priority to EP96400993A priority patent/EP0806780B1/de
Publication of EP0806780A1 publication Critical patent/EP0806780A1/de
Application granted granted Critical
Publication of EP0806780B1 publication Critical patent/EP0806780B1/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/102—Varistor boundary, e.g. surface layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/02—Housing; Enclosing; Embedding; Filling the housing or enclosure
    • H01C1/034—Housing; Enclosing; Embedding; Filling the housing or enclosure the housing or enclosure being formed as coating or mould without outer sheath

Definitions

  • the present invention relates to nonlinear resistive devices, such as varistors, and more particularly to methods of making such devices using barrel plating techniques in which only the electrically contactable end terminals of the device are plated.
  • Nonlinear resistive devices are disclosed in the specifications of U.S. Patent No. 5,115,221.
  • Figure 1 is a typical device 10 that includes plural layers 12 of semiconductor material with electrically conductive electrodes 14 between adjacent layers. A portion of each electrode 14 is exposed in a terminal region 16 so that electrical contact may be made therewith. The electrodes 14 may be exposed at one or both of opposing terminal regions, and typically the electrodes are exposed at alternating terminal regions 16 as illustrated. The exposed portions of the electrodes 14 are contacted by electrically conductive end terminals 18 that cover the terminal regions 16.
  • the apparently simple structure of such devices belies their manufacturing complexity.
  • the attachment of the end terminals 18 has proved to be a problem in search of a solution.
  • the terminal regions may be plated with nickel and tin-lead metals to increase solderability and decrease solder leaching.
  • One method of affixing the end terminals 18 is to use a conventional barrel plating method in which the entire device is immersed in a plating solution.
  • the stacked layers are semiconductor material, such as zinc oxide, that may be conductive during the plating process so that the plating adheres to the entire surface of the device.
  • a portion of the plating must be removed after immersion, or covered before immersion with a temporary plating resist comprised of an organic substance insoluble to the plating solution.
  • a temporary plating resist comprised of an organic substance insoluble to the plating solution.
  • the removal of the plating or organic plating resist is an extra step in the manufacturing process, and may involve the use of toxic materials that further complicate the manufacturing process.
  • the metal forming the end terminals 18 be flame sprayed onto the device, with the other portions of the surface of the device being masked. Flame spraying is not suitable for many manufacturing processes because it is slow and includes the creation of a special mask, with the additional steps attendant therewith, as disclosed in the specification of U.S. Patent No. 4,316,171.
  • An object of the present invention is to provide a method and device that obviates the problems of the prior art, and in which an electrically insulating, inorganic layer is formed on portions of the device before the device is barrel plated.
  • Another object is to provide a method and device in which a phosphoric acid is reacted with the exposed surface of stacked zinc oxide semiconductor layers to form a zinc phosphate coating, and in which a zinc phosphate coating protects portions of the device that are not to be plated when the end terminals are formed.
  • a further object is to provide a method and nonlinear resistive device having a body of layers of semiconductor material with an electrode between adjacent layers, in which the body of the nonlinear resistive device is coated with an inorganic layer that is electrically insulating, except at a terminal region of the body where an electrode is exposed for connection to an end terminal, and in which the coated body is plated with an electrically conductive metal to form the end terminal in a process in which the body becomes electrically conductive and in which the electrically conductive metal does not plate the coated portions of the body because the inorganic layer is not electrically conductive.
  • Figure 1 is a pictorial depiction of a varistor typical of the prior art.
  • Figure 2 is vertical cross section of an embodiment of the device of the present invention.
  • Figure 3 is a pictorial depiction of a high energy disc varistor with an insulating layer of the present invention thereon.
  • Figure 4 is a pictorial depiction of a surface mount device with an insulating layer of the present invention.
  • Figure 2 illustrates an embodiment of a nonlinear resistive element 20 that includes a body 22 having stacked zinc oxide semiconductor layers 24 with planar electrodes 26 between adjacent pairs of layers 24.
  • Each electrode 26 has a contactable portion 28 that is exposed for electrical connection to electrically conductive metal (preferably silver, silver-platinum, or silver-palladium) end terminations 30 that cover terminal regions 32 of the body 22 and contact the electrodes 26.
  • electrically conductive metal preferably silver, silver-platinum, or silver-palladium
  • the portions of body 22 not covered with the end terminations 30 are coated with an electrically insulative zinc phosphate layer 34.
  • the end terminations 30 may be plated with layers 36 of electrically conductive metal that form electrically contactable end portions for the resistive element 20.
  • the zinc oxide layers 24 may have the following composition in mole percent: 94-98% zinc oxide and 2-6% of one or more of the following additives; bismuth oxide, cobalt oxide, manganese oxide, nickel oxide, antimony oxide, boric oxide, chromium oxide, silicon oxide, aluminum nitrate, and other equivalents.
  • the body 22 and end terminations 30 are provided conventionally.
  • the zinc phosphate layer 34 may be formed by reacting phosphoric acid with the zinc oxide semiconductor layers exposed at the exterior of the body 22. The reaction may take place for 25-35 minutes at 70° to 80°C.
  • one part orthophosphoric acid 85 wt% may be added to fifty parts deionized water. The solution may be heated to 75°C and stirred.
  • the body 22 with end terminations 30 affixed may be washed with acetone and dried at 100°C for ten minutes. The washed device may be submerged in the phosphoric acid solution at 75°C for thirty minutes to provide the layer 34.
  • the body may be cleaned with hot, deionized water and dried at about 100°C for about fifteen minutes.
  • the layer 34 does not adhere to the end terminations 30 because the silver or silver-platinum in the end terminations 30 is not affected by the phosphoric acid.
  • the phosphoric acid solution may also be applied by spraying, instead of submerging, the washed device.
  • the device may be barrel plated with an electrically conductive metal, such as nickel and tin-lead, to provide the layers 36.
  • an electrically conductive metal such as nickel and tin-lead
  • a conventional barrel plating process may be used, although the pH of the plating solution is desirably kept between about 4.0 and 6.0.
  • the device is made electrically conductive and the plating material adheres to the electrically charged portions of the device.
  • the metal plating of layers 36 does not plate the zinc phosphate layer 34 during the barrel plating because the zinc phosphate is not electrically conductive.
  • the zinc phosphate layer 34 is electrically insulating and may be retained in the final product to provide additional protection.
  • the layer 34 does not effect the I-V characteristics of the device.
  • the semiconductor may be iron oxide, a ferrite.
  • a high energy disc varistor has a glass or polymer insulating layer on its sides.
  • the disc varistor 40 may have an insulating layer 42 of phosphate formed in the manner discussed above.
  • the present invention is applicable to other varistor products such as a surface mount device depicted in Figure 4, radial parts, arrays, connector pins, discoidal construction, etc.

Claims (9)

  1. Verfahren zum Herstellen eines nichtlinearen Widerstandsbauteils (20), das folgende Schritte aufweist:
    a) Vorsehen eines Körpers (22) für das nichtlineare Widerstandsbauteil (20), wobei das Äußere des Körpers ein Zinkoxid-Halbleiter (24) ausgenommen an einer Anschlußregion (32) ist, an der ein Kontaktanschluß (30) vorgesehen ist;
    b) Durchführen einer Reaktion von Phosphorsäure mit dem Körper (20), um einen elektrisch isolierenden Zinkphosphat-Überzug (34) auf dem freigelegten Zinkoxid-Halbleiter zu bilden, wobei der Kontaktanschluß (30) nicht mit dem Zinkphosphat beschichtet wird; und
    c) Durchführen eines Trommelplattierens des Körpers (22), um auf den Anschluß (30) ein elektrisch leitfähiges Metall (36) abzuscheiden, wobei das elektrisch leitfähige Metall (36) während des Trommelplattierens nicht die mit Zinkphosphat beschichteten Abschnitte des Körpers beschichtet, weil das Zinkphosphat nicht elektrisch leitfähig ist.
  2. Verfahren nach Anspruch 1, bei dem der Kontaktanschluß (30) eine Schicht eines Metalls aufweist, das aus der Gruppe Silber, Silber-Platin und Silber-Palladium ausgewählt ist.
  3. Verfahren nach Anspruch 1 oder 2, bei dem der Körper (22) 94 bis 98 Mol% Zinkoxid und 2 bis 6 Mol% von einem oder mehreren Zusätzen aufweist, die aus der Gruppe der Zusätze Wismutoxid, Kobaltoxid, Manganoxid, Nickeloxid, Antimonoxid, Boroxid, Chromoxid, Siliziumoxid und Aluminiumnitrat ausgewählt sind
  4. Verfahren nach einem der Ansprüche 1 bis 3, bei dem der Schritt des Durchführens einer Reaktion von Phosphorsäure den Schritt des Tauchens des Körpers (22) in die Phosphorsäure aufweist, wobei der Schritt des Tauchens des Körpers das Tauchen in eine Ortho-Phosphorsäurelösung für 25 bis 35 Minuten bei 70 bis 80° C umfaßt.
  5. Verfahren nach einem der Ansprüche 1 bis 4, bei dem das elektrisch leitfähige Metall (36) mindestens einen der Stoffe Nickel und Zinn-Blei umfaßt und der Körper (22) ein Varistor ist.
  6. Verfahren zum Vorsehen eines Halbleiterbauteils mit einer anorganischen elektrisch isolierenden Schicht, wobei das Halbleiterbauteil eine freigelegte Halbleiteroberfläche (24) und elektrisch leitfähige Metallkontaktanschlüsse (28) aufweist, wobei das Verfahren die Schritte umfaßt:
    a) Exponieren des Halbleiterbauteils einer Phosphorsäurelösung, um eine Phosphatbeschichtung auf den ausgesetzten Halbleiteroberflächen, aber nicht auf den Kontaktanschlüssen (30) zu bilden; und
    b) Trommelplattieren des Halbleiterbauteils mit einem elektrisch leitfähigen Metall, das'in einem Prozeß abgeschieden wird, mittels dem das Bauteil elektrisch geladen und in eine Galvanisierlösung getaucht ist, wobei die Plattierung auf den Kontaktanschlüssen (30) und nicht auf der Phosphatbeschichtung gebildet wird, weil die Phosphatbeschichtung nicht elektrisch leitfähig ist.
  7. Verfahren nach Anspruch 6, bei dem die exponierten Halbleiteroberflächen entweder Zinkoxid oder Eisenoxid aufweisen.
  8. Verfahren nach Anspruch 6 oder 7, bei dem die Phosphorsäurelösung Ortho-Phosphorsäure und deionisiertes Wasser umfaßt.
  9. Verfahren nach einem der Ansprüche 6 bis 8, bei dem das nicht beschichtete Halbleiterbauteil in eine Phosphorsäurelösung für 25 bis 35 Minuten bei 70 bis 80° C getaucht wird, um eine elektrisch isolierende Zinkphosphatschicht auf der exponierten Oberfläche der Zinkoxidschichten (24) zu bilden, wobei die Kontaktanschlüsse (30) nicht mit der Zinkphosphatschicht überzogen werden.
EP96400993A 1996-05-09 1996-05-09 Zink-Phosphatbeschichtung für Varistor und Verfahren zur Herstellung Expired - Lifetime EP0806780B1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AT96400993T ATE195198T1 (de) 1996-05-09 1996-05-09 Zink-phosphatbeschichtung für varistor und verfahren zur herstellung
EP96400993A EP0806780B1 (de) 1996-05-09 1996-05-09 Zink-Phosphatbeschichtung für Varistor und Verfahren zur Herstellung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96400993A EP0806780B1 (de) 1996-05-09 1996-05-09 Zink-Phosphatbeschichtung für Varistor und Verfahren zur Herstellung

Publications (2)

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EP0806780A1 EP0806780A1 (de) 1997-11-12
EP0806780B1 true EP0806780B1 (de) 2000-08-02

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614074A (en) * 1994-12-09 1997-03-25 Harris Corporation Zinc phosphate coating for varistor and method
GB2326976A (en) * 1997-06-30 1999-01-06 Harris Corp Varistor nickel barrier electrode
US6214685B1 (en) * 1998-07-02 2001-04-10 Littelfuse, Inc. Phosphate coating for varistor and method
US6841191B2 (en) * 2002-02-08 2005-01-11 Thinking Electronic Industrial Co., Ltd. Varistor and fabricating method of zinc phosphate insulation for the same
WO2020018651A1 (en) 2018-07-18 2020-01-23 Avx Corporation Varistor passivation layer and method of making the same
TWI760706B (zh) * 2020-03-06 2022-04-11 立昌先進科技股份有限公司 電子元件封裝結構及其製作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3004736C2 (de) * 1979-02-09 1986-08-21 TDK Corporation, Tokio/Tokyo Varistor und Verfahren zu seiner Herstellung
JPS5816602B2 (ja) * 1979-02-09 1983-04-01 ティーディーケイ株式会社 電圧非直線性抵抗素子
CA1186130A (en) * 1981-06-16 1985-04-30 Jeffery L. Barrall Rigid, water-resistant phosphate ceramic materials and processes for preparing them
JPH0770380B2 (ja) * 1988-04-11 1995-07-31 ローム株式会社 電子部品のニッケルメッキ方法
JPH03131004A (ja) * 1989-10-17 1991-06-04 Toshiba Corp 非直線抵抗体の製造方法
GB2242066B (en) * 1990-03-16 1994-04-27 Ecco Ltd Varistor structures
JP2815990B2 (ja) * 1990-07-26 1998-10-27 株式会社東芝 非直線抵抗体の製造方法
JPH05136012A (ja) * 1991-11-15 1993-06-01 Rohm Co Ltd チツプタイプ電子部品の製造方法
US5614074A (en) * 1994-12-09 1997-03-25 Harris Corporation Zinc phosphate coating for varistor and method

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ATE195198T1 (de) 2000-08-15
EP0806780A1 (de) 1997-11-12

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