EP0806711A1 - Taktselektionsschaltung - Google Patents

Taktselektionsschaltung Download PDF

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Publication number
EP0806711A1
EP0806711A1 EP96107337A EP96107337A EP0806711A1 EP 0806711 A1 EP0806711 A1 EP 0806711A1 EP 96107337 A EP96107337 A EP 96107337A EP 96107337 A EP96107337 A EP 96107337A EP 0806711 A1 EP0806711 A1 EP 0806711A1
Authority
EP
European Patent Office
Prior art keywords
input
latch
strobe signals
output
combining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96107337A
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English (en)
French (fr)
Other versions
EP0806711B1 (de
Inventor
Jason Julyan
Michael Stephen Hardwood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Priority to EP19960107337 priority Critical patent/EP0806711B1/de
Priority to DE1996622843 priority patent/DE69622843T2/de
Publication of EP0806711A1 publication Critical patent/EP0806711A1/de
Application granted granted Critical
Publication of EP0806711B1 publication Critical patent/EP0806711B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F1/00—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers
    • G04F1/005—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers using electronic timing, e.g. counting means

Definitions

  • the present invention relates generally to digital devices and more particularly to the implementation of timing circuitry using digital devices.
  • IC fabrication processes tend to be targeted at one of two applications. Some allow chips to be made with precision passive components (resistors, capacitors, etc.) while others allow very dense areas of transistors to be placed. The former are required for chips with a mostly analogue function and will use Bipolar (and maybe MOSFET) transistors. The latter are targeted at large digital chips and will use MOSFET transistors exclusively.
  • the present invention provides an implementation of timing circuits, which are specified by a minimum and maximum value and intended for analogue implementation, using a digital counter and a clock signal of varying phase thus eliminating the need for passive components.
  • One embodiment of the present invention as shown in Fig.1 includes a strobe select circuit 7 which uses several input clock signals 10, 12, 14 and 16 having the same frequency, but differing phases to implement a timing circuit.
  • These input clock signals 10, 12, 14 and 16 are produced by various techniques including a Delay Locked Loop with multiple variable-delay stages, or by creating increasing delay paths for a single input clock signal.
  • the former technique provides for evenly separated phases, while the latter, although much simpler to design, is subject to process, temperature, and voltage level variations.
  • Other methods for producing the input clock signals 10, 12, 14 and 16 will be readily apparent to those skilled in the art.
  • the number of input clock signals used is determined by the accuracy requirements of the application and by the frequency of a base clock, not shown, from which the input clock signals 10, 12, 14 and 16 are derived.
  • the frequency must be a multiple of the shortest timer needed, i.e., if a timer of 50ns (+/-5ns) is needed, then a 10ns or 25ns period is appropriate but a 33ns period is not.
  • the range of the exemplary timer is 45-55ns, i.e. 10ns.
  • 2 phases give a resolution of 12.5ns
  • 4 phases which give a resolution of 6.25ns, are chosen to allow for subsequent gate delays.
  • An asserted reset signal 18 holds the circuit 7 or 9 in a reset state, with the output signal at 62 in Fig. 1 and at 64 in Fig. 2 held low.
  • Four RS latches 90, 92, 94 and 96 are held reset (where their outputs are HIGH) using this reset signal 18.
  • the reset circuits 7 and 9 may be arranged for the signal 18 to be active HIGH or active LOW.
  • clock strobes (input signals 10, 12, 14 and 16) are used in the circuits 7 and 9 shown in Figures 1 and 2, respectively, and are called stb0, stb90, stb180 and stb270, respectively, (the numbers referring to their relative phase to the base clock, not shown, from which they are derived).
  • the waveforms associated with each of these strobes are shown in Figs. 3A-D, respectively.
  • Each pair of adjacent strobes i.e. a pair of strobes separated by 90 degrees
  • Each of these signals 66, 68, 70 and 72 are associated with one of the RS latches 90, 92, 94 and 96.
  • the number of adjacent strobes AND-ed together so that only one of the combinations is HIGH at any one time depends on the number of input clock strobes used. As an example, if eight clock strobes are used instead of four, four adjacent clock strobes are AND-ed together to give eight signals, only one of which is HIGH at any one time.
  • the set input 30 for the RS latch 90 is the NAND 28 of the signal 66 and the output signals 102, 104 and 106 of the other three RS latches 92, 94 and 96.
  • NAND gates 32, 36 and 40 are similarly used to generate the set inputs 34, 38 and 42 for the RS latches 92, 94 and 96, respectively.
  • the RS latches 90, 92, 94 and 96 are able to be set.
  • the NAND gates 28, 32, 36 and 40 on the set inputs 30, 34, 38 and 42 of the RS latches 90, 92, 94 and 96 only one gets set, as shown by the exemplary waveform in Fig.5C, namely the one associated with the two strobe inputs 10 and 12, 12 and 14, 14 and 16, or 16 and 10 which are both HIGH.
  • the strobe inputs which are 90 and 180 out of phase from the base clock are selected.
  • this RS latch 90, 92, 94 or 96 sets, its output signal 100, 102, 104 or 106 goes LOW which feeds into the NAND gates 28, 32, 36 and 40, respectively, on the other three RS latches and prevents them from being able to be set. So only one RS latch 90, 92, 94 or 96 will ever have its output signal 100, 102, 104 or 106 LOW.
  • the output signals 100, 102, 104 and 106 of the four RS latches 90, 92, 94 and 96, respectively, are inverted and fed into NAND gates 52, 54, 56 and 58 respectively, along with one of the input strobes 10, 12, 14 or 16.
  • the RS latch 90, 92, 94 or 96 which is set enables its associated strobe signal 10, 12, 14 or 16 to traverse the NAND gate 52, 54, 56 or 58.
  • NAND gate 62 (which, by DeMorgan's Theorem implements an OR function) to give the output clock signal 62 in the first embodiment shown in Fig.1 and to give the output clock signal 64 in the second embodiment shown in Fig. 2.
  • Figs. 1 and 2 Two embodiments of the strobe selection circuit 7 and 9 are shown in Figs. 1 and 2, respectively, the difference being in which strobe signal 10, 12, 14 or 16 gets selected by which RS latch 90, 92, 94 or 96.
  • the strobe signal 10, 12, 14 or 16 selected to the output 62 or 64 must either be (upto) halfway through its LOW period, as illustrated by the waveform in Fig.5D, or (upto) halfway HIGH as illustrated by the waveform shown in Fig.5E (the other two could be transitioning LOW to HIGH or HIGH to LOW at this time which gives a very short glitch on the output clock signal 62 or 64), the waveforms of which are shown in Figs.5F and 5G, respectively.
  • the final component of a timer in accordance with the present invention is a synchronous count-down counter 110.
  • the counter 110 is held reset by the same reset signal 18 as the strobe select circuits 7 and 9 shown in Figs.1 and 2, respectively.
  • the counter 110 counts down with each clock edge output 62 or 64 from the strobe select circuits 7 or 9 shown in Figs.1 and 2, respectively.
  • the delay to the first rising edge is either upto half a cycle minus delay through two NAND gates, and fanout into the counter in the circuit shown in Fig.1, or just these gate delays in the circuit shown in Fig.2.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
EP19960107337 1996-05-09 1996-05-09 Taktselektionsschaltung Expired - Lifetime EP0806711B1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19960107337 EP0806711B1 (de) 1996-05-09 1996-05-09 Taktselektionsschaltung
DE1996622843 DE69622843T2 (de) 1996-05-09 1996-05-09 Taktselektionsschaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19960107337 EP0806711B1 (de) 1996-05-09 1996-05-09 Taktselektionsschaltung

Publications (2)

Publication Number Publication Date
EP0806711A1 true EP0806711A1 (de) 1997-11-12
EP0806711B1 EP0806711B1 (de) 2002-08-07

Family

ID=8222766

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19960107337 Expired - Lifetime EP0806711B1 (de) 1996-05-09 1996-05-09 Taktselektionsschaltung

Country Status (2)

Country Link
EP (1) EP0806711B1 (de)
DE (1) DE69622843T2 (de)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2928045A (en) * 1957-09-20 1960-03-08 Itt Signal decoder
US3502991A (en) * 1967-06-19 1970-03-24 Bell Telephone Labor Inc Signal generator with asynchronous start
JPS58184886A (ja) * 1982-04-22 1983-10-28 Nippon Hoso Kyokai <Nhk> クロツク再生方式

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2928045A (en) * 1957-09-20 1960-03-08 Itt Signal decoder
US3502991A (en) * 1967-06-19 1970-03-24 Bell Telephone Labor Inc Signal generator with asynchronous start
JPS58184886A (ja) * 1982-04-22 1983-10-28 Nippon Hoso Kyokai <Nhk> クロツク再生方式

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 008, no. 021 (E - 224) 28 January 1984 (1984-01-28) *
S. BOÏNODIRIS: "Clock synchronisation for counting time intervals.", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 16, no. 7, December 1973 (1973-12-01), NEW YORK, pages 2087 - 2089, XP002016553 *
Z. TARZY-HORNOCH: "Some nanosecond and subnanosecond resoltution timing techniques.", WESCON TECHNICAL PAPERS, vol. 18, no. 27/4, 1974, NORTH HOLLYWOOD, pages 1 - 7, XP002016552 *

Also Published As

Publication number Publication date
EP0806711B1 (de) 2002-08-07
DE69622843D1 (de) 2002-09-12
DE69622843T2 (de) 2002-11-28

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