EP0798777A3 - Verfahren zur Metallisierung von Submikron-(bzw. um-) Kontaktlöchern in Halbleiterkörpern - Google Patents

Verfahren zur Metallisierung von Submikron-(bzw. um-) Kontaktlöchern in Halbleiterkörpern Download PDF

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Publication number
EP0798777A3
EP0798777A3 EP97104276A EP97104276A EP0798777A3 EP 0798777 A3 EP0798777 A3 EP 0798777A3 EP 97104276 A EP97104276 A EP 97104276A EP 97104276 A EP97104276 A EP 97104276A EP 0798777 A3 EP0798777 A3 EP 0798777A3
Authority
EP
European Patent Office
Prior art keywords
contact holes
submicronie
micronie
metallizing
semiconductor body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97104276A
Other languages
English (en)
French (fr)
Other versions
EP0798777A2 (de
EP0798777B1 (de
Inventor
Konrad Dr. Dipl.-Phys. Hieber
Helmuth Dipl.-Ing. Ireichel (Fh)
Heinrich Dr. Dipl.-Chem. Körner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0798777A2 publication Critical patent/EP0798777A2/de
Publication of EP0798777A3 publication Critical patent/EP0798777A3/de
Application granted granted Critical
Publication of EP0798777B1 publication Critical patent/EP0798777B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/907—Continuous processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/907—Continuous processing
    • Y10S438/908—Utilizing cluster apparatus

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Zur Metallisierung von Submikron-Kontaktlöchern in Halbleiterkörpern wird durch einen einzigen CVD-Prozeß innerhalb einer einzigen CVD-Kammer zunächst eine titanreiche Schicht und anschließend eine niederohmige TiSi2-Schicht abgeschieden.
EP97104276A 1996-03-29 1997-03-13 Verfahren zur Metallisierung von Submikron Kontaktlöchern in Halbleiterkörpern Expired - Lifetime EP0798777B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19612725A DE19612725A1 (de) 1996-03-29 1996-03-29 Verfahren zur Metallisierung von Submikron-Kontaktlöchern in Halbleiterkörpern
DE19612725 1996-03-29

Publications (3)

Publication Number Publication Date
EP0798777A2 EP0798777A2 (de) 1997-10-01
EP0798777A3 true EP0798777A3 (de) 1998-07-01
EP0798777B1 EP0798777B1 (de) 2004-05-26

Family

ID=7789977

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97104276A Expired - Lifetime EP0798777B1 (de) 1996-03-29 1997-03-13 Verfahren zur Metallisierung von Submikron Kontaktlöchern in Halbleiterkörpern

Country Status (6)

Country Link
US (1) US6057229A (de)
EP (1) EP0798777B1 (de)
JP (1) JP2996931B2 (de)
KR (1) KR970067651A (de)
DE (2) DE19612725A1 (de)
TW (1) TW386294B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976976A (en) 1997-08-21 1999-11-02 Micron Technology, Inc. Method of forming titanium silicide and titanium by chemical vapor deposition
US5930671A (en) * 1997-10-20 1999-07-27 Industrial Technology Research Institute CVD titanium silicide for contract hole plugs
US6136693A (en) * 1997-10-27 2000-10-24 Chartered Semiconductor Manufacturing Ltd. Method for planarized interconnect vias using electroless plating and CMP
TW507015B (en) * 1997-12-02 2002-10-21 Applied Materials Inc In-situ, preclean of wafers prior to a chemical vapor deposition titanium deposition step
US6284316B1 (en) 1998-02-25 2001-09-04 Micron Technology, Inc. Chemical vapor deposition of titanium
US6573181B1 (en) 2000-10-26 2003-06-03 Applied Materials, Inc. Method of forming contact structures using nitrogen trifluoride preclean etch process and a titanium chemical vapor deposition step
US6911391B2 (en) 2002-01-26 2005-06-28 Applied Materials, Inc. Integration of titanium and titanium nitride layers
US6998014B2 (en) * 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
JP2012193445A (ja) * 2011-02-28 2012-10-11 Tokyo Electron Ltd 窒化チタン膜の形成方法、窒化チタン膜の形成装置及びプログラム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04137621A (ja) * 1990-09-28 1992-05-12 Toshiba Corp 半導体装置の製造方法
US5397742A (en) * 1993-04-16 1995-03-14 Hyundai Electronics Industries Co., Ltd. Method for forming tungsten plug for metal wiring
US5462895A (en) * 1991-09-04 1995-10-31 Oki Electric Industry Co., Ltd. Method of making semiconductor device comprising a titanium nitride film

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4737474A (en) * 1986-11-17 1988-04-12 Spectrum Cvd, Inc. Silicide to silicon bonding process
DE4132560C1 (en) * 1991-09-30 1993-04-22 Siemens Ag, 8000 Muenchen, De Plasma-aided deposition of film for integrated semiconductor circuit - using neutral particles, activated by microwave in separate chamber, and non-excited reaction gas, etc.
JP3120517B2 (ja) * 1991-12-03 2000-12-25 ソニー株式会社 シリサイドプラグの形成方法
US5240739A (en) * 1992-08-07 1993-08-31 Micron Technology Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers
US5846881A (en) * 1995-12-28 1998-12-08 Micron Technology, Inc. Low cost DRAM metallization

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04137621A (ja) * 1990-09-28 1992-05-12 Toshiba Corp 半導体装置の製造方法
US5462895A (en) * 1991-09-04 1995-10-31 Oki Electric Industry Co., Ltd. Method of making semiconductor device comprising a titanium nitride film
US5397742A (en) * 1993-04-16 1995-03-14 Hyundai Electronics Industries Co., Ltd. Method for forming tungsten plug for metal wiring

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 016, no. 408 (E - 1255) 28 August 1992 (1992-08-28) *

Also Published As

Publication number Publication date
TW386294B (en) 2000-04-01
KR970067651A (ko) 1997-10-13
US6057229A (en) 2000-05-02
EP0798777A2 (de) 1997-10-01
DE59711655D1 (de) 2004-07-01
JP2996931B2 (ja) 2000-01-11
DE19612725A1 (de) 1997-10-02
JPH1050637A (ja) 1998-02-20
EP0798777B1 (de) 2004-05-26

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