EP0731403A2 - Konstantstromquelle - Google Patents

Konstantstromquelle Download PDF

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Publication number
EP0731403A2
EP0731403A2 EP96301270A EP96301270A EP0731403A2 EP 0731403 A2 EP0731403 A2 EP 0731403A2 EP 96301270 A EP96301270 A EP 96301270A EP 96301270 A EP96301270 A EP 96301270A EP 0731403 A2 EP0731403 A2 EP 0731403A2
Authority
EP
European Patent Office
Prior art keywords
transistor
current
voltage
source
mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP96301270A
Other languages
English (en)
French (fr)
Other versions
EP0731403A3 (de
Inventor
David Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA, SGS Thomson Microelectronics Inc filed Critical STMicroelectronics lnc USA
Publication of EP0731403A2 publication Critical patent/EP0731403A2/de
Publication of EP0731403A3 publication Critical patent/EP0731403A3/de
Pending legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • This invention is in the field of integrated circuits, and is more particularly directed to current source circuits useful therein.
  • CMOS complementary metal-oxide-semiconductor
  • functional circuits internal to an integrated circuit rely upon current sources that conduct a stable current.
  • Examples of such functional circuits include voltage regulators, differential amplifiers, sense amplifiers, current mirrors, operational amplifiers, level shift circuits, and reference voltage circuits.
  • Such current sources are generally implemented by way of field effect transistors, with a reference voltage applied to the gate of the field effect transistor.
  • the integrated circuits utilizing such current sources would operate optimally if the current provided by the current source were to be stable over variations in operating and process conditions.
  • the drive characteristics of MOS transistors can vary quite widely with these operating and process variations.
  • MOS transistor current sources will generally source more current at low operating temperature (e.g., 0°C), high V cc power supply voltage (e.g., 5.3 volts for a nominal 5 volt power supply), and process conditions that maximize drive (e.g., shorter than nominal channel length); conversely, these current sources will source less current at high operating temperature (e.g., 100°C), low V cc power supply voltage (e.g., 4.7 volts for a nominal 5 volt power supply), and process conditions that minimize drive current (e.g., longer than nominal channel length).
  • the ratio between the maximum current drive and minimum current drive for such conventional current sources has been observed to be on the order of 2.5 to 6.0. The behavior of circuits that rely on these current sources will therefore tend to vary greatly over these operating and process conditions, requiring the circuit designer to design for a greater operating margin, thus reducing the maximum performance of the integrated circuit.
  • Variations in the current provided by a current source are especially troublesome where the current to be sourced is relatively large.
  • output driver circuitry for conventional integrated circuits may require currents of up to as much as 20 ma to be sourced by a current source. In such an application, variations of this current of greater than a factor of two cannot be tolerated.
  • the invention may be implemented into an integrated circuit as a current source, having a current mirror output stage, controlled by a bias voltage from a bias circuit that tracks variations in process parameters and power supply voltage.
  • the bias circuit is based on a resistor voltage divider that sets the current in the input leg of a current mirror in the bias circuit; in this input leg, a modulating transistor that is maintained in saturation, which in turn dictates the current through a linear load device in the output leg of the bias circuit current mirror, generating the bias voltage applied to the current mirror output stage.
  • the current mirror output stage has a reference leg that includes a p-channel transistor having its gate receiving the bias voltage from the bias circuit, in series with an n-channel transistor having its gate tied to its drain.
  • the relative sizes of the p-channel and n-channel transistors in this reference leg are selected to maintain the p-channel transistor in saturation.
  • the output leg of the current mirror output stage is an n-channel transistor having its gate connected to the gate and drain of the n-channel transistor in the reference leg. The current sourced in the output leg of the current mirror is thus quite stable over variations in the power supply voltage, temperature, and manufacturing process conditions.
  • Figure 1 is an electrical diagram, in block form, of a current source according to the preferred embodiment of the invention.
  • Figure 2 is an electrical diagram, in schematic form, of the current source according to the preferred embodiment of the invention.
  • Figure 3 is a plot of bias voltage BIAS versus V cc power supply voltage for various process conditions and temperatures, as generated by the bias circuit shown in Figure 2.
  • Figure 4 is an electrical diagram, in schematic form, of the current source according to an alternative embodiment of the invention.
  • Current source 2 includes bias circuit 20 for generating a bias voltage on line BIAS.
  • bias circuit 20 includes resistor divider 10 which produces a voltage that is a desired fraction of the voltage of the V cc power supply. This divided voltage is applied to a current mirror 15.
  • current mirror 15 generates a current that is applied to a load, so that the output of current mirror 15 is a bias voltage on line BIAS.
  • the voltage on line BIAS is applied to a current mirror 40, which sinks a fixed output current i OUT at terminal OUT, operating as a current source.
  • bias circuit 20 is a current mirror bias circuit, in which the reference leg of a current mirror 15 is controlled by a voltage divider 10.
  • bias circuit 20 provides a bias voltage on line BIAS that varies in a consistent manner with variations in the value of power supply voltage V cc , and with variations in certain manufacturing process parameters.
  • bias circuit 20 provides a voltage on line BIAS to the gate of p-channel transistor 52 in current mirror 40. It is desired in this example that the gate-to-source voltage of p-channel transistor 52 remain substantially constant over variations in the voltage of the V cc power supply, so that the current therethrough remains constant; in other words, it is desired that the voltage on line BIAS follow variations in V cc . In this way, current i OUT produced at terminal OUT by current mirror 40 will remain substantially constant over such variations.
  • bias circuit 20 includes resistor divider 10 having resistors 21, 23 connected in series between the V cc power supply and ground.
  • the output of resistor divider 10, at the node between resistors 21, 23, is presented to the gate of an n-channel transistor 28 in current mirror 15.
  • Resistors 21, 23 are preferably implemented as polysilicon resistors, in the usual manner.
  • additional resistors 25, 27 may also be present in each leg of the voltage divider, with fuses 24, 26 connected in parallel therewith.
  • the integrated circuit into which bias circuit 20 is implemented is fuse-programmable to allow adjustment of the voltage applied to the gate of transistor 28, if desired. Indeed, it is contemplated that multiple ones of additional resistors 25, 27 and accompanying fuses may be implemented in the voltage divider, to allow a wide range of adjustment of the voltage output of the voltage divider.
  • the gate of transistor 28 receives the output of the voltage divider of resistors 21, 23.
  • the source of transistor 28 is biased to ground, and the drain of transistor 28 is connected to the drain and gate of p-channel transistor 30, which in turn has its source tied to V cc .
  • the combination of transistors 28, 30 is a reference leg of a current mirror, with the current conducted therethrough substantially controlled by the voltage output of resistor divider 10 of resistors 21, 23. Accordingly, the voltage applied to the gate of transistor 28, and thus the current conducted by transistors 28, 30 in the reference leg of the current mirror, will vary with variations in the voltage of the V cc power supply so as to remain at approximately the same fraction of the voltage of the V cc power supply.
  • the output leg of current mirror 15 in bias circuit 20 includes p-channel mirror transistor 32 and linear load device 34.
  • P-channel transistor 32 has its source connected to V cc and its gate connected to the gate and drain of transistor 30, in current mirror fashion.
  • the drain of transistor 32 is connected to the linear load device 34, at line BIAS.
  • Load device 34 may be implemented as an n-channel transistor 34, having its source at ground and its gate at V cc , in which case the common drain node of transistors 32, 34 drives the bias voltage output on line BIAS.
  • linear load device 34 may be implemented as a precision resistor, or as a two-terminal diode.
  • linear load device 34 is important in providing compensation for variations in process parameters, such as channel length. Variations in the channel length of transistors 30, 32 will cause variations in the current conducted by transistor 32 and thus, due to the linear nature of load device 34, will cause a corresponding variation in the voltage on line BIAS. Accordingly, bias circuit 20 provides an output voltage on line BIAS that tracks variations in process parameters affecting current conduction by transistors in the integrated circuit.
  • the current conducted by transistor 32 is controlled to match, or to be a specified multiple of, the current conducted through transistor 30. Since the current conducted through transistors 28, 30 is controlled according to the divided-down voltage of the V cc power supply, the current conducted by transistor 32 (and thus the voltage on line BIAS) is therefore controlled by the V cc power supply. The voltage on line BIAS will thus also track modulation in the V cc power supply voltage, as will be described in further detail hereinbelow, by way of modulation in the voltage drop across linear load 34.
  • transistor 28 is preferably near, but not at, the minimum channel length and channel width for the manufacturing process used.
  • transistor 28 having a channel length near the process minimum the current conducted by transistor 28 will vary with variations in the channel length for the highest performance transistors in the integrated circuit; use of a longer channel length would reduce the sensitivity of transistor 28 to such variations.
  • the channel length of transistor 28 should be slightly larger than minimum, to avoid hot electron effects and short channel effects.
  • Transistor 28 also preferably has a relatively small, but not minimum, channel width, to minimize the current conducted therethrough, especially considering that bias circuit 20 will conduct DC current at all times through transistors 28, 30 (and mirror leg transistor 32 and linear load 34).
  • An example of the size of transistor 28 according to a modern manufacturing process would be a channel length of 0.8 ⁇ m and a channel width of 4.0 ⁇ m, where the process minimums would be 0.6 ⁇ m and 1.0 ⁇ m, respectively.
  • P-channel transistors 30, 32 must also be properly sized in order to properly bias transistor 28 and linear load device 34 (when implemented as a transistor), respectively.
  • transistor 28 is preferably biased in the saturation (square law) region, while transistor 34 is biased in the linear (or triode) region. This allows transistor 34 to act effectively as a linear resistive load device, while transistor 28 remains saturated. As is evident from the construction of bias circuit 20 in Figure 2, such biasing depends upon the relative sizes of transistor 28 and 30, and the relative sizes of transistors 32 and 34.
  • transistor 30 it is preferable for transistor 30 to be as large as practicable so that the voltage at the gate of transistor 28 may be as near to V cc as possible while maintaining transistor 28 in saturation. This is because variations in V cc will be applied to the gate of transistor 28 in the ratio defined by the voltage divider of resistors 21, 23; accordingly, it is preferable that this ratio be as close to unity as possible, while still maintaining transistor 28 in saturation.
  • a large W/L ratio for transistor 30 allows its drain-to-source voltage to be relatively small, thus pulling the drain voltage of transistor 28 higher, which allows the voltage at the gate of transistor 28 to be higher while still maintaining transistor 28 in saturation. The tracking ability of bias circuit 20 is thus improved by transistor 30 being quite large.
  • the following table indicates the preferred channel widths (in microns) of transistors 28, 30, 32 and 34 in the arrangement of Figure 2, for the case where the channel length of each is 0.8 ⁇ m: Table Transistor Channel Width ( ⁇ m) 28 4.0 30 32.0 32 76.0 34 4.0
  • FIG. 3 is a plot of the voltage on line BIAS as a function of V cc , simulated for maximum and minimum transistor channel lengths in a 0.8 micron manufacturing process, illustrating the operation of bias circuit 20 according to the present invention.
  • Curves 44, 46 in Figure 3 correspond to the low-current process corner (i.e., maximum channel length) at 0° and 100° C junction temperatures, respectively;
  • curves 47, 49 in Figure 3 correspond to the high-current process corner (i.e., minimum channel length) at 0° and 100° C junction temperatures, respectively.
  • Current mirror 40 in this example is implemented by way of p-channel transistor 52 having its source biased to V cc and its gate biased by bias voltage BIAS from the output of bias circuit 20 described hereinabove.
  • N-channel transistor 54 is connected in diode fashion, with its gate and drain connected to the drain of transistor 64.
  • the sizes of transistors 52 and 54 are selected to ensure that p-channel transistor 52 remains in saturation for the desired level of bias voltage BIAS. For example, for a bias voltage BIAS of approximately 2 volts, transistors 52 and 54 with W/L ratios of approximately 15 will maintain transistor 52 in saturation where V cc is nominally 5 volts.
  • the common node at the drains of transistors 52, 54 presents a reference voltage ISVR that is applied to the gate of n-channel transistor 56, which constitutes the output leg of current mirror 40.
  • N-channel transistor 56 has its source biased to ground, and its drain connected to terminal OUT. Accordingly, the current conducted by transistor 56, namely output current i OUT , is a mirrored current relative to the current conducted by transistor 54 in the reference leg of current mirror 40.
  • the relative sizes of transistors 54, 56 are selected so that the current sourced by transistor 56 is the desired multiple of that conducted by transistors 52, 54. For example, if the ratio is to be 1:1, the width/length ratios of transistors 54, 56 will be equal to one another; alternatively, if the current to be sourced by transistor 56 is to be a multiple of that conducted by transistors 52, 54, the W/L ratio of transistor 56 will be the desired multiple of that of transistor 54.
  • current source 2 provides a relatively constant output current i OUT as a result of the tracking of variations in power supply voltage and process parameters by bias circuit 20 in its generation of the bias voltage on line BIAS, because the conditions causing shifts in the voltage on line BIAS similarly affect the drive characteristics of the transistors in current mirror 40.
  • both variations in the process conditions that shift the voltage on line BIAS e.g., the shift between curves 46 and 49 in Figure 3
  • variations in the power supply voltage V cc affect the drive characteristics of transistor 52 in current mirror 40, with the net effect being that the current conducted by transistor 52 is substantially constant over these variations.
  • simulation results indicate that the ratio of maximum to minimum current conducted by transistor 56 in current mirror 40, where bias circuit 20 set the voltage on line BIAS applied thereto, is approximately 1.17, taken over variations in temperature from 0°C to 100°C, over variations in process parameters (i.e., transistor channel length, gate oxide thickness, and other known drive-varying parameters) resulting in drive current variations of about 50%, and over variations in the V cc power supply voltage from 4.7 volts to 5.3 volts.
  • process parameters i.e., transistor channel length, gate oxide thickness, and other known drive-varying parameters
  • the current source of this embodiment of the invention may be useful in other circuit designs, as well.
  • circuits such as voltage regulators, differential amplifiers, sense amplifiers, current mirrors, operational amplifiers, level shift circuits, and reference voltage circuits all may be implemented to utilize a current source transistor (i.e., transistor 56).
  • a current source transistor i.e., transistor 56. Control of the current source transistor in the manner described hereinabove, to ensure a relatively stable current to be sourced by transistor 56, is contemplated to be beneficial in these applications, as well.
  • bias circuit 20 may be made while still benefiting from the present invention.
  • One such variation is illustrated in Figure 4, by way of bias circuit 20'. Similar elements in circuit 20' as those in circuit 20 described hereinabove will be referred to with the same reference numerals.
  • Bias circuit 20' is constructed similarly as bias circuit 20 described hereinabove.
  • the gate of linear load transistor 34 is set by voltage divider 38, such that the gate voltage is a specified fraction of the V cc power supply voltage.
  • Transistor 34 while operating substantially as a linear load, is in fact a voltage-controlled resistor, such that its on resistance is a function of the gate-to-source voltage.
  • circuitry may be provided to selectively enable and disable the generation of the bias voltage BIAS, if such selectivity is useful in a particular application.
  • the present invention thus provides the important advantage of a current source that provides a stable output current over a wide range of temperature, power supply voltage, and manufacturing process parameters.
  • this stable output current is obtained from the generation of a bias voltage that tracks variations in process conditions and power supply voltages in a manner which compensates for the effects of these variations in the transistors of an output current mirror.
  • the current source of the present is especially beneficial in applications where relatively large currents are required, such as in output driver circuitry, without risk that the maximum current of the current source is excessive.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
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EP96301270A 1995-03-08 1996-02-26 Konstantstromquelle Pending EP0731403A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39907995A 1995-03-08 1995-03-08
US399079 1999-09-17

Publications (2)

Publication Number Publication Date
EP0731403A2 true EP0731403A2 (de) 1996-09-11
EP0731403A3 EP0731403A3 (de) 1997-07-23

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EP (1) EP0731403A3 (de)
JP (1) JPH08263158A (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8054111B2 (en) 2004-12-13 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance using the same
US8872572B2 (en) 2009-09-16 2014-10-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5630863B2 (ja) 2010-11-26 2014-11-26 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 構造化文書に含まれるノードの全順序関係を、ログ情報に基づいて決定して可視化する方法、装置及びコンピュータプログラム

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3714543A (en) * 1970-11-21 1973-01-30 Minolta Camera Kk Constant current circuit constituted on a monolithic ic
US4251743A (en) * 1977-10-28 1981-02-17 Nippon Electric Co., Ltd. Current source circuit
EP0282725A1 (de) * 1987-03-06 1988-09-21 International Business Machines Corporation CMOS-Referenzspannungsgeneratoreinrichtung
US5047707A (en) * 1990-11-19 1991-09-10 Motorola, Inc. Voltage regulator and method for submicron CMOS circuits
EP0472202A2 (de) * 1990-08-22 1992-02-26 Nec Corporation Konstantstromquellenschaltung vom Stromspiegeltyp mit geringer Abhängigkeit von der Versorgungsspannung
EP0536063B1 (de) * 1991-09-30 1995-07-19 STMicroelectronics S.A. Präzisionsstromgenerator

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3714543A (en) * 1970-11-21 1973-01-30 Minolta Camera Kk Constant current circuit constituted on a monolithic ic
US4251743A (en) * 1977-10-28 1981-02-17 Nippon Electric Co., Ltd. Current source circuit
EP0282725A1 (de) * 1987-03-06 1988-09-21 International Business Machines Corporation CMOS-Referenzspannungsgeneratoreinrichtung
EP0472202A2 (de) * 1990-08-22 1992-02-26 Nec Corporation Konstantstromquellenschaltung vom Stromspiegeltyp mit geringer Abhängigkeit von der Versorgungsspannung
US5047707A (en) * 1990-11-19 1991-09-10 Motorola, Inc. Voltage regulator and method for submicron CMOS circuits
EP0536063B1 (de) * 1991-09-30 1995-07-19 STMicroelectronics S.A. Präzisionsstromgenerator

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8054111B2 (en) 2004-12-13 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance using the same
US8179170B2 (en) 2004-12-13 2012-05-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance using the same
US8872572B2 (en) 2009-09-16 2014-10-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US9368519B2 (en) 2009-09-16 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US9830878B2 (en) 2009-09-16 2017-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US9934747B2 (en) 2009-09-16 2018-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US10181304B2 (en) 2009-09-16 2019-01-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US10446103B2 (en) 2009-09-16 2019-10-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US10902814B2 (en) 2009-09-16 2021-01-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US11545105B2 (en) 2009-09-16 2023-01-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US11984093B2 (en) 2009-09-16 2024-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance

Also Published As

Publication number Publication date
EP0731403A3 (de) 1997-07-23
JPH08263158A (ja) 1996-10-11

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