EP0724932A1 - Halbleiterwafer, Halbleiteranordnung enthaltende denselben und Verfahren zur dessen Herstellung - Google Patents

Halbleiterwafer, Halbleiteranordnung enthaltende denselben und Verfahren zur dessen Herstellung Download PDF

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Publication number
EP0724932A1
EP0724932A1 EP96300388A EP96300388A EP0724932A1 EP 0724932 A1 EP0724932 A1 EP 0724932A1 EP 96300388 A EP96300388 A EP 96300388A EP 96300388 A EP96300388 A EP 96300388A EP 0724932 A1 EP0724932 A1 EP 0724932A1
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European Patent Office
Prior art keywords
substrate
semiconductor substrate
axis
semiconductor
semiconductor device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP96300388A
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English (en)
French (fr)
Inventor
Keiji C/O Seiko Instruments Inc. Sato
Yutaka C/O Seiko Instruments Inc. Saito
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Seiko Instruments Inc
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Seiko Instruments Inc
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Publication of EP0724932A1 publication Critical patent/EP0724932A1/de
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/10—Single-purpose machines or devices
    • B24B7/16—Single-purpose machines or devices for grinding end-faces, e.g. of gauges, rollers, nuts, piston rings
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/04—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor involving a rotary work-table
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain

Definitions

  • the present invention relates to semiconductor substrates and semiconductor devices utilizing the same, especially, semiconductor devices having a photoelectric conversion device, an MIS structure, or a Schottky diode structure, and a method of manufacturing the same.
  • FIG. 13 of the accompanying drawings Another possible method utilizes a cup grinding wheel.
  • a cup grinding wheel 31 and a semiconductor substrate 1 are positioned to face each other so that the outer circumference of the former and the rotational centre of the latter substantially coincide with each other, and a cup grinding wheel 31 is caused to cut into the semiconductor substrate 1 with the cup grinding wheel 31 and the semiconductor substrate 1 rotated in opposite directions.
  • Figure 4 is a schematic sectional view showing the state of a surface of a semiconductor substrate obtained using a known processing method in which a deep process-transformed layer 36 is produced which extends from a surface 35 of the semiconductor substrate to the region indicated by the broken line.
  • the thickness of the process-transformed layer b is limited to about 1.5 ⁇ m and there will be irregularities (undulations) having an amplitude variation "a" of at least several micrometers.
  • a grinding process can be performed which involves less possibility of generation of a process transformed layer and reduces the thickness of a process-transformed layer to 0.1 ⁇ m without increasing the size of the device and without reducing processing efficiency, and such a processing method is applied especially to a semiconductor device having a photoelectric conversion device and an MIS structure to improve the efficiency of photoelectric conversion or to enhance the capacity of a capacitor.
  • a method of processing the surface of a semiconductor substrate comprising rotating the substrate; rotating a grinding wheel about an axis which is substantially perpendicular to the axis of rotation of the substrate; and moving the axis of rotation of the wheel along an axis which is substantially perpendicular to the axis of rotation of the substrate and the axis of rotation of the wheel to grind the substrate.
  • a method of manufacturing a semiconductor device comprising processing a semiconductor substrate according to the present invention and forming a semiconductor device utilising the processed semiconductor substrate.
  • a semiconductor substrate comprising a process-transformed layer having an undulated surface, characterised in that the thickness of the layer at its minimum is in the range of 0.1 ⁇ m to 0.5 ⁇ m.
  • a semiconductor substrate having an undulated surface characterised in that the difference between the minimum and maximum surface height is in the range of 0.3 ⁇ m to 3 ⁇ m.
  • an apparatus for processing the surface of a semiconductor substrate comprising means for rotating the substrate; a grinding wheel; means for rotating the grinding wheel about an axis which is substantially perpendicular to the axis of rotation of the substrate and means for moving the axis of rotation of the wheel along an axis which is substantially perpendicular to the axis of rotation of the substrate and the axis of rotation of the wheel to grind the substrate.
  • the thickness of a process-transformed layer on the surface of a semiconductor substrate is kept within the range from 0.1 ⁇ m to 0.5 ⁇ m as a first means.
  • the amplitude of undulations of the surface of a semiconductor substrate is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • the amplitude of undulations of the surface of a substrate of a semiconductor device is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • the amplitude of undulations of the surface of a substrate of a semiconductor device having a photoelectric conversion device is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • the amplitude of undulations of the surface of a substrate of a semiconductor device having an MIS structure is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • the amplitude of undulations of the surface of a substrate of a semiconductor device having a separated-dielectric structure is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • the amplitude of undulations of the surface of a substrate of a semiconductor device having a Schottky diode structure is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • the amplitude of undulations of the surface of an SO1 semiconductor substrate is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • the amplitude of undulations of the surface of a DW semiconductor substrate is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • the amplitude of undulations of the surface of an expitaxial semiconductor substrate is kept within the range from 0.3 ⁇ m to 3 ⁇ m.
  • a rotating semiconductor substrate is ground by the circumferential end face having a flat portion of a disc-shaped grinding wheel which is rotated about a moving rotational axis.
  • wet etching is performed using a solution after the above-described grinding.
  • a semiconductor substrate of a photoelectric conversion device is processed using the above-described grinding method.
  • a semiconductor substrate of a semiconductor device having a photodiode structure is processed using the above-described grinding method.
  • a semiconductor substrate of a semiconductor device having an MIS structure is processed using the above-described grinding method.
  • a semiconductor substrate of a semiconductor device having an MIS structure especially a charge-transfer device (CTD) is processed using the above-described grinding method.
  • a semiconductor substrate of a semiconductor device having an MIS structure especially a DRAM is processed using the above-described grinding method.
  • a separated-dielectric structure is formed by processing a semiconductor substrate using the above-described grinding method.
  • a separated-dielectric structure is formed using the above-described grinding method in a semiconductor device especially a photodiode array such as an optical relay which has been subjected to dielectric separation.
  • a semiconductor substrate of a semiconductor device having a Schottky diode structure is processed using the above-described grinding method.
  • an SOI substrate is particularly processed using the above-described grinding method.
  • a semiconductor substrate is processed using the above-described grinding method in a semiconductor device having an MIS structure especially a semiconductor device having a boosting circuit.
  • a semiconductor substrate is processed using the above-described grinding method in a photoelectric conversion semiconductor device having a light-receiving device portion constituted by a semiconductor substrate of a first conductivity type and an impurity region of a second conductivity type provided on the surface of said substrate and an electrode for applying a reverse voltage to the junction of a capacitor connected to said light-receiving device portion and said light-receiving device portion.
  • a semiconductor device is manufactured using a semiconductor substrate wherein the thickness of a process-transformed layer on the surface thereof is 0.1 ⁇ m to 0.5 ⁇ m.
  • a DW substrate is particularly used in the above-described grinding method.
  • an epitaxial substrate is particularly processed using the above-described grinding method.
  • Figure 1 is a schematic perspective view showing a method of grinding a semiconductor substrate according to an embodiment of the present invention.
  • a semiconductor substrate 1 is fixed on a main spindle 3 of a machine tool by a chuck 2, and the main spindle 3 of the machine tool is rotated by a motor 4.
  • the main spindle 3 of the machine tool is provided on a head stock 5 and is moved along an X-axis by a servo motor or the like together with the head stock 5.
  • a disc-shaped grinding wheel 6 is rotated by a grinding wheel spindle 7 about a Z-axis by means of a motor, and a grinding wheel head 8 on which this grinding wheel spindle 7 is fixed is reciprocated by a servo motor or the like in the direction of a Y-axis which is orthogonal to the X-axis and Z-axis.
  • Figure 2 is a conceptual diagram illustrating the positional relationship between the semiconductor substrate 1 and the disc-shaped grinding wheel 6 wherein the semiconductor substrate 1 is brought into contact with the outer circumferential end face of the disc-shaped grinding wheel 6 as a result of the movement of the head stock 5 along the X-axis.
  • the rotation of the machine tool main spindle 3 caused by the motor 4 results in the rotation of the semiconductor substrate 1, and the rotation of the grinding wheel spindle 7 causes the disc-shaped grinding wheel 6 to rotate.
  • the semiconductor substrate 1 is ground in accordance with the movement in the direction of the X-axis.
  • the thickness of the disc-shaped grinding wheel is 15 - 20 mm which substantially corresponds to one chip (device) on a semiconductor substrate. Since grinding is performed at line contact of such a width, the processing load is smaller than that in grinding on a surface contact basis.
  • Processing efficiency is very low when the width of the disc-shaped grinding wheel is 10 mm or less while a width of 20 mm or more results in problems such as an increase in the size of the device due to an increase in the processing load.
  • the method according to the present invention suppresses the generation of cracks and the like because the contact time per one abrasive grain of the grinding wheel is short and hence chips are effectively ejected.
  • a semiconductor substrate processed according to a process of the invention was subjected to angle lapping and selective etching using a wet type chemical etchant which is a mixture of HN0 3 HF 1 and CH 3 COOH or water and was examined for the presence of micro cracks and defects using a sectional transmission electron microscope.
  • a wet type chemical etchant which is a mixture of HN0 3 HF 1 and CH 3 COOH or water
  • appropriate processing conditions allowed the thickness b of a process-transformed layer 36 (i.e. the region damaged by shaping) in the region indicated by the broken line from the surface 35 of the semiconductor substrate to be reduced to 0.1 ⁇ m and allowed an amplitude variation a of irregularities (undulations) to be reduced to 0.3 ⁇ m.
  • a process-transformed layer is a region having micro cracks and defects produced by angle lapping and selective etching as described above, it is preferable that the presence of micro cracks and defects is further observed using a sectional transmission electron microscope.
  • angle lapping and selective etching are described in American Society for Testing and Materials (ASTM) F 950 in detail and reference can be made also to Japanese Industrial Standard (JIS) H 0609.
  • TTV total thickness variation
  • a process-transformer layer up to 0.5 ⁇ m is on a level which can be easily removed by oxidation followed by etching of the oxide film.
  • the irregularities (undulations) having a long period on the surface can be maintained almost as they are, unlike polishing, and a semiconductor substrate having a process-transformed layer of 0.1 ⁇ m to 0.5 ⁇ m thickness is very useful.
  • Irregularities having a long period on the surface can be varied up to about 3 ⁇ m depending on the size of the abrasive grains and processing speed.
  • Figure 5 is a schematic section showing the state of the surface of a semiconductor substrate processed according to a method of the present invention which has been etched or oxidized and the process-transformed layer of which has been removed by etching the oxide layer. As illustrated, a semiconductor substrate having a large surface area without any process-transformed layer has been obtained.
  • a process-transformed layer can be expanded as a result of oxidation when the etching of the oxide layer is performed in an attempt to remove the process-transformed layer, it is preferable that the process-transformed layer is removed or made thinner in advance by means of wet type chemical etching.
  • Such a semiconductor substrate is very useful because a photoelectric conversion device having high conversion efficiency or a semiconductor device having a large apparent MIS (metal insulator semiconductor) capacitor per unit area can be obtained from it.
  • MIS metal insulator semiconductor
  • Figure 6 is a schematic sectional view of a PIN photodiode, which is excellent especially in linearity and response speed among photodiodes, according to a first embodiment of the present invention relating to photoelectric transfer devices.
  • a P + type impurity region 11 and an N + type impurity region 12 are formed on an N - type semiconductor substrate 10 of a low resistivity index, and an N + type impurity region 13 is formed also on the rear side.
  • the width of the depletion layer can be greatly varied depending on the reverse voltage, and the use of the N- type semiconductor substrate processed according to the method of the invention improves the conversion efficiency.
  • Figure 7 is a schematic sectional view of a solar battery which is a second embodiment of the present invention relating to photoelectric transfer devices.
  • a P + type impurity region 11 and an N + type impurity region 12 are formed on an N type semiconductor substrate 13, and the use of the N type semiconductor substrate processed according to the method of the invention improves the conversion efficiency.
  • Figure 8 is a schematic sectional view of a solid-state camera device having a MOS IC (metal-oxide-semiconductor integrated circuit) and a photodiode as a light-receiving portion and consisting of an N + type impurity region 16, a P + type impurity region 17, an X gate 18, a Y gate 19, a P + type impurity region 20, and a drain 21 provided on an N type semiconductor substrate 15.
  • MOS IC metal-oxide-semiconductor integrated circuit
  • an MIS capacitor per unit area can be improved by the use of a semiconductor substrate processed according to a method of the invention.
  • Figure 9 is a schematic sectional view of one type of charge-transfer device according to a fifth embodiment of the present invention.
  • a semiconductor substrate 25 processed according to a method of the invention is used; an oxide film 26 is formed thereon, and a polysilicon electrode 27 and a metal electrode 28 are further formed thereon.
  • the use of the semiconductor substrate processed according to a method of the invention allows the amount of accumulated electric charge to be increased.
  • Figure 10 is a schematic sectional view of an example of a DRAM according to a fifth embodiment of the present invention. It includes a metal data line 47 and a polysilicon ward line 46 provided on a P - type semiconductor substrate 40, and a capacitor is formed by a polysilicon plate electrode 43, an oxide film 44, and an inversion layer 45.
  • Figure 11 is a circuit diagram of the above-described DRAM wherein a one-transistor type cell is constituted by one MOS transistor and one MOS capacitor (electrostatic capacity). The greater the signal obtained, the larger the capacity of the capacitor. In order to allow finer configurations, the capacity per unit area of the capacitor must be increased.
  • the capacity per unit area can be increased to obtain a large signal amount.
  • MOS capacitor utilizing thermally oxidized Si0 2 having excellent characteristics is normally used as a dielectric for an MIS capacitor, it goes without saying that other substances having a high dielectric constant such as CVD Si0 2 and Si 3 N 4 or multi-layer structures such as Si0 2 -Si 3 N 4 -Si0 2 are also effective.
  • Figure 14 is a circuit diagram of an optically driven semiconductor relay (optical relay) constituted by an LED 75, a photoelectric conversion device 76, and a MOSFET 77.
  • the photoelectric conversion device has a separated-dielectric photodiode array structure.
  • Performance can be improved by forming the separation of the dielectric using a processing method according to the present invention.
  • Figure 15A-15C illustrate steps for manufacturing a separated-dielectric photodiode array structure according to a processing method of the invention.
  • a groove 52 is formed on a silicon substrate 50 having a N + type impurity region 51 formed thereon by means of anisotropic etching, RIE (reactive ion etching) or the like; an insulation film 53 is formed by means of thermal oxidation, and a polysilicon layer 54 is formed thereon using CVD.
  • RIE reactive ion etching
  • a Si0 2 layer is formed on the thermally oxidized insulation film 53 using spin-on glass or CVD; etching (etch-back) is performed thereafter to form a flattening layer 55; and a silicon substrate 57 is laminated thereon.
  • the initial silicon substrate 50 is ground using the method of the invention to form a single crystal silicon island 56 which has been subjected to dielectric separation.
  • predetermined devices for example with impurity regions 11 and 12, are formed as shown in Figure 15C.
  • Figures 17A-17C illustrate steps for manufacturing in a case wherein the grinding method according to the present invention is used for an SOI substrate.
  • an insulation film 53 is formed on a silicon substrate 57 using thermal oxidation; a silicon substrate 50 manufactured using an FZ (floating zone) process or the like is laminated thereon to fabricate an S0I substrate; and, thereafter, the laminated silicon substrate 57 is ground according to the grinding method of the invention to a predetermined thickness as shown in Figure 17B.
  • FZ floating zone
  • a LOCOS (local oxidation) oxide film 58 for separating devices is formed so that it reaches the insulation film 53, thereby performing dielectric separation to form predetermined devices having, for example, a semiconductor substrate 10 and impurity region 11.
  • Figures 18A-18C illustrate steps for manufacturing in a case in which device separation is performed on an SOI substrate using a grinding method according to the present invention.
  • a single crystal silicon island 60 is formed on an S01 substrate 59 by means of etching or the like, and an oxide film 61 is formed on the surface thereof.
  • a polysilicon layer 62 is deposited using CVD (chemical vapour deposition).
  • predetermined devices may be formed as shown in Figure 15C for example.
  • FIG 19 is a schematic sectional view showing a Schottky diode according to a seventh embodiment of the present invention, in which an N + type impurity region 71 is formed on a surface of an N - type semiconductor substrate 70 ground according to the grinding method of the invention, an N + type impurity region 72 is formed also on the opposite side, a Schottky electrode 73 of a Schottky metal such as Al, W, Pt, etc. is formed in direct contact with the N - type semiconductor substrate, an ohmic electrode 74 is formed in contact with the N + type impurity region 72, and a Schottky junction is formed by a Schottky electrode 73.
  • a Schottky electrode 73 of a Schottky metal such as Al, W, Pt, etc.
  • the use of a semiconductor substrate ground according to a grinding method of the invention increases the bonding area of the Schottky junction, thereby allowing the forward voltage V F (a forward voltage required to obtain a predetermined forward current) to be decreased.
  • Such a Schottky diode having a small forward voltage V F is quite useful as a switching device, a bi-directional gate circuit which is a combination of four Schottky diodes, a balance modulator, a double-balance modulator, or a ring modulator.
  • Figure 20 is a circuit diagram of a semiconductor device having a boosting circuit which is essentially constituted by a rectifying device 88 and a capacitor 89.
  • Figure 20 shows a diode as the rectifying device, it may be replaced by a transistor.
  • the diode may be either PN junction or Schottky junction type.
  • FIG 21 is a schematic sectional view of a semiconductor device having a boosting circuit according to an eighth embodiment of the present invention, in which a PN junction is provided as a rectifying device.
  • the PN junction as a rectifying device and a capacitor are formed on separate islands utilizing silicon islands 80 which are P type impurity regions made of silicon and which have been subjected to device-separation according to a method as shown in any of Figures 15 through 18, and a capacitor electrode 81 and a capacitor insulation film 82 are formed in the capacitor portion.
  • the structure may have been manufactured according to a method such as that shown in Figure 17, in which the structure is provided with a silicon substrate 218 and an insulator film 219 and in which device separation is achieved by the provision of a LOCOS oxide film 217.
  • the rectifying portion has P + impurity regions 211 and 213 and an N ⁇ impurity region 212
  • the capacitor has P + impurity regions 214 and 216 and a P + impurity region which isolates the P + impurity region 214 from the P + impurity region 216 (P ⁇ indicates an impurity concentration P greater than P - and less than P + ).
  • Device separation according to an inventive method such as any of those shown in Figures 15 through 18, allows the capacity to be increased, thereby increasing the boosting voltage.
  • Figure 22 is a schematic sectional view of a semiconductor device having a boosting circuit according to a ninth embodiment of the present invention and in which a PN junction and a capacitor are fabricated on a single silicon island 80 which is an N type impurity region.
  • a PN junction is formed by anode electrode 221, which contacts a P + type impurity region 224, and cathode electrode 223, which contacts an N + type impurity region 225.
  • a capacitor is formed by capacitor electrode 81, capacitor insulation film 82 and N + type impurity region 222.
  • the cathode electrode 223 is also used as a capacitor electrode for contacting the N + type impurity region 222.
  • Figure 23 is a schematic sectional view of a semiconductor device having a boosting circuit according to a tenth embodiment of the present invention and in which transistors are used as rectifying devices, P - type wells 86 are formed on an N type semiconductor substrate 85 ground according to a grinding method of the invention, the transistors are fabricated therein, and a capacitor insulation film 82 is formed on a LOCOS oxide film 87 between the wells with capacitor electrodes 81 interposed therebetween.
  • Figure 24 is a schematic sectional view of a photoelectric conversion semiconductor device mainly used for purposes such as the detection of radiation according to an eleventh embodiment of the present invention and in which a multiplicity of P + type impurity regions 92 as impurity regions of a second conductivity type in the form of strips are formed on a surface of an N - type semiconductor substrate 91 ground according to a grinding method of the invention as a semiconductor substrate of a first conductivity type, and an N + type impurity region 93 is formed on the opposite side.
  • a two-dimensional configuration can be provided by forming a multiplicity of N + type impurity regions in the form of strips like the P + type impurity regions so that they are orthogonal to the P + type impurity regions.
  • a capacitor insulation film consisting of three layers, i.e. a Si0 2 layer 94, a Si 3 N 4 layer 95, and a Si0 2 layer 96, and a capacitor electrode 97 made of polysilicon are formed to perform capacitive reading (the structure on the N + type impurity region will be the same as that on the P + type impurity regions if the N + type impurity region is provided in the form of strips).
  • an Al electrode 98 for applying a reverse voltage is formed on the P + type impurity regions. It applies the reverse voltage to expand the depletion layer through a high resistance portion 99 made of silicon, thereby allowing the efficiency of the detection of radiation and the like to be improved.
  • the capacity of a capacitor portion for reading can be increased by processing a semiconductor substrate to be used for such a semiconductor device using a grinding method of the invention.
  • a substrate processed using a grinding method of the invention has an improved heat dissipation capacity, such a substrate is advantageous when used in a bipolar transistor or diode which is a vertical device (a current is applied to the substrate surface vertically) consuming high power referred to as a power semiconductor device.
  • Such a semiconductor device utilizes a substrate having a high resistance portion formed on a low resistance portion.
  • a substrates include DW (diffusion wafer) substrates and epitaxial substrates to which the present invention can be applied.
  • Figures 25A-25B illustrate manufacturing steps in a case wherein a grinding method of the invention is used for a DW substrate.
  • a high impurity region 101 having low resistance is formed on a high resistance substrate 100.
  • the high impurity region 101 is formed on both sides, the high impurity region on one side is removed as shown in Figure 25B.
  • the use of a grinding method of the invention leaves a surface having irregularities of 0.3 ⁇ m to 1 ⁇ m formed thereon, and a power semiconductor device formed on such a DW substrate will exhibit an excellent heat dissipation capacity.
  • FIGS 26A-26B illustrate manufacturing steps in a case wherein a grinding method of the invention is used for an epitaxial substrate. As shown in Figure 26A, a high resistance epitaxial layer 106 is formed on a low resistance substrate 105 on an epitaxial growth basis.
  • a projection referred to as a hillock 107 grows on the surface of the epitaxial layer 106.
  • the epitaxial layer is ground to a predetermined thickness using a grinding method of the invention, which also results in removal of the hillock as shown in Figure 26A.
  • a power semiconductor device formed on such an epitaxial substrate will exhibit an excellent heat dissipation capacity.
  • the present invention makes it possible to provide a semiconductor substrate having a small process-transformed layer which can be used, amongst other things, to obtain a photoelectric conversion device of high conversion efficiency or a semiconductor device having a large apparent MIS capacitor per unit area and a power semiconductor device having an excellent heat dissipation capacity.
  • the invention provides a photoelectric conversion device of high conversion efficiency and a semiconductor device having a large capacitor capacity in the thickness of a process-transformed layer which is small. Further, a rotating semiconductor substrate is ground by the circumferential end face of a disc-shaped grinding wheel which is rotated about a moving rotational axis.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
EP96300388A 1995-01-20 1996-01-19 Halbleiterwafer, Halbleiteranordnung enthaltende denselben und Verfahren zur dessen Herstellung Withdrawn EP0724932A1 (de)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP7515/95 1995-01-20
JP751595 1995-01-20
JP8158995 1995-04-06
JP81589/95 1995-04-06
JP82905/95 1995-04-07
JP8290595 1995-04-07
JP31566195A JPH08335562A (ja) 1995-01-20 1995-12-04 半導体装置およびその製造方法
JP315661/95 1995-12-04

Publications (1)

Publication Number Publication Date
EP0724932A1 true EP0724932A1 (de) 1996-08-07

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JP (1) JPH08335562A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0824053A1 (de) * 1996-08-14 1998-02-18 Siemens Aktiengesellschaft Gerät zum chemisch-mechanischen Polieren von Wafern

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4878738B2 (ja) * 2004-04-30 2012-02-15 株式会社ディスコ 半導体デバイスの加工方法
CN114102407B (zh) * 2021-12-08 2022-11-08 重庆华西三利包装刀具有限责任公司 一种刀片旋转面加工用的抛光机床

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FR2505709A1 (fr) * 1981-05-14 1982-11-19 Od Polt Institut Procede de formation, sur la surface de pieces, d'un microrelief regulier compose d'evidements separes, tete porte-outil et meule pour la mise en oeuvre dudit procede, et pieces traitees conformement audit procede
JPS57194866A (en) * 1981-05-21 1982-11-30 Shin Etsu Chem Co Ltd Lapping device
EP0362516A2 (de) * 1988-10-04 1990-04-11 International Business Machines Corporation Vorrichtung zum mechanischen Planpolieren
US5083401A (en) * 1988-08-08 1992-01-28 Mitsubishi Denki Kabushiki Kaisha Method of polishing
EP0588055A2 (de) * 1992-09-18 1994-03-23 Mitsubishi Materials Corporation Verfahren zur Herstellung von Halbleiterscheiben

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3943666A (en) * 1974-07-31 1976-03-16 Dysan Corporation Method and apparatus for burnishing flexible recording material
FR2505709A1 (fr) * 1981-05-14 1982-11-19 Od Polt Institut Procede de formation, sur la surface de pieces, d'un microrelief regulier compose d'evidements separes, tete porte-outil et meule pour la mise en oeuvre dudit procede, et pieces traitees conformement audit procede
JPS57194866A (en) * 1981-05-21 1982-11-30 Shin Etsu Chem Co Ltd Lapping device
US5083401A (en) * 1988-08-08 1992-01-28 Mitsubishi Denki Kabushiki Kaisha Method of polishing
EP0362516A2 (de) * 1988-10-04 1990-04-11 International Business Machines Corporation Vorrichtung zum mechanischen Planpolieren
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0824053A1 (de) * 1996-08-14 1998-02-18 Siemens Aktiengesellschaft Gerät zum chemisch-mechanischen Polieren von Wafern
US5964652A (en) * 1996-08-14 1999-10-12 Siemens Aktiengesellschaft Apparatus for the chemical-mechanical polishing of wafers
DE19632809C2 (de) * 1996-08-14 2002-06-20 Infineon Technologies Ag Gerät zum chemisch-mechanischen Polieren von Wafern

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