EP0694886B1 - Elektronisches Frankiersystem mit einem austauschbaren Betriebsprogramm in einem Flash-Speicher - Google Patents

Elektronisches Frankiersystem mit einem austauschbaren Betriebsprogramm in einem Flash-Speicher Download PDF

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Publication number
EP0694886B1
EP0694886B1 EP19950401701 EP95401701A EP0694886B1 EP 0694886 B1 EP0694886 B1 EP 0694886B1 EP 19950401701 EP19950401701 EP 19950401701 EP 95401701 A EP95401701 A EP 95401701A EP 0694886 B1 EP0694886 B1 EP 0694886B1
Authority
EP
European Patent Office
Prior art keywords
memory
microprocessor
circuit
sector
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19950401701
Other languages
English (en)
French (fr)
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EP0694886A1 (de
Inventor
Bernard Vermesse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quadient Technologies France SA
Original Assignee
Neopost Technologies SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Neopost Technologies SA filed Critical Neopost Technologies SA
Publication of EP0694886A1 publication Critical patent/EP0694886A1/de
Application granted granted Critical
Publication of EP0694886B1 publication Critical patent/EP0694886B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00193—Constructional details of apparatus in a franking system
    • G07B2017/00258—Electronic hardware aspects, e.g. type of circuits used
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00314—Communication within apparatus, personal computer [PC] system, or server, e.g. between printhead and central unit in a franking machine
    • G07B2017/00322—Communication between components/modules/parts, e.g. printer, printhead, keyboard, conveyor or central unit
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
    • G07B2017/00395—Memory organization
    • G07B2017/00403—Memory zones protected from unauthorized reading or writing

Definitions

  • the invention relates generally to field of postage machines which are now widely used in shipping offices of corporate mail.
  • It relates more particularly to a system electronic postage including a microprocessor connected by an address bus and a bus data to a non-volatile memory circuit in which is recorded an operating program (see EP-A-0 605 313).
  • operating program is meant a program intended for the control of the microprocessor in order to obtain a desired operation of it. It can be used in particular with amount accounting information management postage. This information includes generally the amount of funds available in the system (this amount being decremented with each transaction postage) as well as the cumulative amount of postage (this amount is incremented each time franking operation). This information is maintained in the so-called top-down and bottom-up registers in non-volatile memory backed up by battery. Most franking system has two memories not battery-backed birds in which are duplicate the top and bottom registers.
  • Such a franking system is generally mounted inside a sealed enclosure.
  • the program operating system is saved in a memory of the type EPROM.
  • Such memory requires exposure to rays ultra violet to be erased then reprogrammed in order to change the operating program.
  • the circuit or EPROM memory box must be mounted in the franking system on a support so as to be removable. The presence of such a support increases the cost of the postage system. It would be possible to record the operating program in a RAM type read / write memory backed up by drums. But such a solution increases the cost even more of the franking system.
  • this arrangement would cause complications to ensure the level of program data security required by Postal administrations. In other words, it is not planned today to change, in situ in a system electronic franking, the operating program stored in a non-volatile memory circuit, i.e. without removing the memory circuit from the sealed enclosure containing the franking system.
  • the object of the invention is to propose a system electronic postage meter having a circuit of memory arranged in such a way as to allow a change in situ of the operating program recorded in the circuit of memory without penalizing the cost of the system and without affecting its security level.
  • the invention relates to a system electronic postage characterized in that the memory circuit is of the flash memory type having a memory space divided into a plurality of sectors selectively addressable from the address bus, in this that there is an address decoding circuit between the address bus and a memory circuit terminal authorizing or prohibiting writing to memory, this circuit of decoding being arranged so that the microprocessor is prevented from writing to a first memory sector in which the operating program is saved when the decoding circuit detects the presence of a signal control set to a logical first level and the microprocessor is allowed to write to said first memory sector when the decoding circuit detects the presence of the control signal set to a second level logic, and that there is a loading program saved in a second protected memory sector, by programmed configuration of the memory circuit, against all write access, this loading program being planned to control the microprocessor in such a way that he establish a dialogue with another processor in view load a new operating program, provided by this other processor, instead of the operating program already saved in said first memory sector when the control signal
  • Non-volatile memory circuit technology from flash type is starting to appear on the market and is of interest for a franking system electronic postal.
  • Such a memory circuit has space memory organized into sectors of fixed size selectively erasable by a microprocessor control. The sectors of such memory are otherwise likely to be selectively protected against write or write access erasure. This protection is done by configuring the flash memory on a programming bench. This protection can therefore be performed before mounting the memory circuit flash directly on a printed circuit board.
  • Such non-volatile memory circuit may be suitable for recording the operating program of a machine postage because it has a memory space important enough.
  • Decoding circuit prevents changes untimely operating program in memory flash, for example in the event of a malfunction of the microprocessor, and contributes to the security of the system.
  • this control signal comes from a line conductive connected to a current source by a pin removable. This way when the spindle is interposed between the decoding circuit and the current source, the control signal is set to its first logical state. When this pin is removed, the control signal changes of logical state which makes the first sector of memory containing the operating program accessible in erasing and writing by the microprocessor which can then reload a new operating program.
  • the microprocessor, the circuit memory, address decoding circuit and pin be placed inside a sealed enclosure. This way, only the manufacturer can load a new one. operating program in the first sector of the memory.
  • Figure 1 shows in schematic form a first embodiment of the franking system.
  • Figure 2 illustrates the organization into sectors of the flash memory.
  • the franking system includes a microprocessor 1 having seventeen address bits A0-A16 and eight data bits D0-D7, for example the circuit integrated known as "80C166" or the circuit integrated known under the reference "ST10". He still understands a non-volatile flash memory circuit 2, for example the integrated circuit known under the reference "29F10PL".
  • This memory has a capacity of 128 Kilo bytes divided into eight memory sectors of 16 Kilo bytes each. These eight sectors are designated by S1 to S8 in Figure 2.
  • the data inputs / outputs D0 to D7 of the memory 2 are connected to the data inputs / outputs microprocessor 1 through a bus data 10 comprising eight lines of data.
  • the entrees of addresses A0 to A16 of memory circuit 2 are connected to corresponding address outputs of microprocessor 1 to across an address bus 11 comprising seventeen lines addresses.
  • the memory circuit 2 also has an input of OE read command, WR write command input and a CE box selection input.
  • the entrance to selection of CE box permanently receives a signal 0 volt electric so the memory circuit 2 receives all read and write commands from microprocessor 1.
  • the microprocessor 1 also has an output of RD read command, a write command output WR, a reserved input of a CHPRG control signal, and a serial RXD1 input and TXD1 output port.
  • RD microprocessor read command output is connected to the RD read command input of the circuit of memory.
  • the serial RXD1 input and TXD1 output of the microprocessor are connected to a connector 5 through a control bus 12 comprising several lines of orders.
  • microprocessor input for receive the CHPRG control signal is connected through the control bus 12 and a removable pin 4 (under the shape of a jumper) to a current source delivering a 5 volts electrical signal corresponding to a level logic equal to 1.
  • the address decoder 3 includes an AND gate reverser 31 with three inputs to receive respectively the CHPRG control signal and signals from the outputs of most significant addresses A15 and A16 of microprocessor. These last two signals are taken directly on address bus 11. It also includes a reversing single door 32 which receives a control signal write from WR write command output of microprocessor 1. It includes yet another AND gate reverser 33 having a first input connected to the output of gate 31 and two other inputs connected to the output of door 32. The output of door 33 is connected to the input write command WR of memory circuit 2.
  • the microprocessor 1, the memory circuit 2, the address decoder 3 and pin 4 are enclosed in a enclosure 20 comprising a hatch 21 giving access from the outside of the enclosure on pin 4.
  • the hatch closes normally the enclosure and is sealed to prevent any unauthorized access to the interior of the enclosure by a user.
  • the connector 5 is freely accessible from outside the enclosure 20. However, it could also be locked inside of the enclosure so as to be accessible only when the hatch 21 is open.
  • the set of circuits 1,2,3,4,5 is mounted on one or printed circuit boards not shown, the terminals memory circuit 2 can be directly soldered on a printed circuit board.
  • the memory space of memory 2 is divided into a plurality of memory sectors of identical capacity, in the occurrence eight sectors S1 to S8 of 16 Kilo bytes each.
  • a loading program is saved in the sector S1.
  • the S1 sector is protected against erasing or writing, after the program load recorded there and before mounting the circuit memory 2 directly on the printed circuit board. Such protection is achieved using a device specific memory programming known per se.
  • a machine operating program postage is recorded in sectors S7 and S8 from memory. Sectors S2 to S6 are left free for the recording of other data.
  • the address decoder 3 prevents access writing the microprocessor in sectors S7 and S8 of memory of the fact that the combination of the input signals of door 31 forces the output of the address decoder to a logic level equal to 1 and that this logic level is that required to inhibit WR write command input memory circuit 2.
  • the address decoder 3 ensures that the operating program saved in the S7 and S8 memory is not affected by a malfunction microprocessor for example.
  • the microprocessor accesses the first bytes saved in sector S1 of the memory which constitute the beginning of the loading program.
  • This loading program is first designed to test during the start of its execution the logic level CHPRG signal received by the microprocessor. If this signal to a logic level equal to 1, the loading program launches execution of the operating program at the same time as stops. It is therefore the normal framework for operation of the franking system.
  • the CHPRG signal will have a logic level equal to 0.
  • the address decoder 3 lets through the control signal WR writing from the microprocessor so that authorize the microprocessor to write in the S7 sectors and S8 from memory.
  • the loading program upon signal detection CHPRG at a logic level equal to 0, command the microprocessor in such a way that it first erases the contents of sectors S7 and S8 and then that it establishes a communication with another processor connected to the ports RXD1 and TXD1 serial input / output via connector 5 to load a new one in situ operating program in sectors S7 and S8, this new operating program from the other processor.
  • the loading program can stop and block the functioning of the system postage. System power postage should be cut.
  • the spindle 4 must be replaced again so that the CHPRG signal level is equal to 1. Then the machine meter is turned back on and the program loading as indicated above will launch the execution of the new operating program.
  • the signal CHPRG can come from directly from the microprocessor which is controlled in such a way so as to change the logic level of the CHPRG signal to response to a coded message obtained from the port of entry RXD1 series.
  • the microprocessor of the franking system is connected, for example by a telephone line, at a fleet management center postage systems.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Read Only Memory (AREA)

Claims (3)

  1. Elektronisches Postfrankiersystem mit einem Mikroprozessor (1), der über einen Adressenbus (11) und einen Datenbus (10) an eine nicht-flüchtige Speicherschaltung (2) angeschlossen ist, in der ein Anwendungsprogramm gespeichert ist, dadurch gekennzeichnet, daß die Speicherschaltung vom Flash-Typ ist und einen in einer Mehrzahl von selektiv ausgehend vom Adressenbus adressierbaren Sektoren (S1 bis S8) unterteilten Speicher enthält, daß eine Adressendekodierschaltung (3) zwischen dem Adressenbus und einer Klemme (WE) der Speicherschaltung vorgesehen ist, über die das Beschreiben des Speichers zugelassen oder untersagt wird, wobei diese Dekodierschaltung so ausgebildet ist, daß der Mikroprozessor am Beschreiben eines ersten Sektors (S7, S8) gehindert wird, in dem das Anwendungsprogramm gespeichert ist, wenn die Kodierschaltung das Vorliegen eines ersten logischen Pegels eines Steuersignals (CHPRG) feststellt, während der Mikroprozessor den ersten Sektor des Speichers beschreiben kann, wenn die Dekodierschaltung das Vorliegen eines zweiten logischen Pegels des Steuersignals feststellt, und daß ein Ladeprogramm vorgesehen ist, das in einem zweiten Sektor des Speichers liegt, der durch programmierte Konfiguration der Speicherschaltung gegen jeden zugang in Schreibrichtung geschützt ist, wobei dieses Ladeprogramm ausgestaltet ist, um den Mikroprozessor so zu steuern, daß er einen Dialog mit einem anderen Prozessor in Hinblick auf das Laden eines neuen von diesem anderen Prozessor gelieferten Anwendungsprogramms anstelle des bisher im ersten Sektor des Speichers enthaltenen Anwendungsprogramms herstellt, wenn das Steuersignal auf den zweiten logischen Pegel gebracht wird.
  2. System nach Anspruch 1, in dem das Steuersignal (CHPRG) von einer Leitung kommt, die an eine Stromquelle über eine entfernbare Brücke (4) angeschlossen ist.
  3. System nach Anspruch 2, in dem der Mikroprozessor (1), die Speicherschaltung (2), die Adressendekodierschaltung (3) und die abnehmbare Brücke innerhalb eines versiegelten Gehäuses (2) untergebracht sind.
EP19950401701 1994-07-18 1995-07-18 Elektronisches Frankiersystem mit einem austauschbaren Betriebsprogramm in einem Flash-Speicher Expired - Lifetime EP0694886B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9408859 1994-07-18
FR9408859A FR2722595B1 (fr) 1994-07-18 1994-07-18 Systeme d'affranchissement postal electronique ayant un programme d'exploitation rechargeable in situ

Publications (2)

Publication Number Publication Date
EP0694886A1 EP0694886A1 (de) 1996-01-31
EP0694886B1 true EP0694886B1 (de) 1999-10-13

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Application Number Title Priority Date Filing Date
EP19950401701 Expired - Lifetime EP0694886B1 (de) 1994-07-18 1995-07-18 Elektronisches Frankiersystem mit einem austauschbaren Betriebsprogramm in einem Flash-Speicher

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Country Link
EP (1) EP0694886B1 (de)
DE (1) DE69512718T2 (de)
FR (1) FR2722595B1 (de)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547853A (en) * 1982-10-13 1985-10-15 Pitney Bowes Inc. Electronic postage meter reset circuit
DE3650330T2 (de) * 1985-10-16 1995-11-16 Pitney Bowes Inc Frankiermaschinensystem zur nichtflüchtigen Speicherung von Daten.
WO1989011134A1 (en) * 1988-05-09 1989-11-16 Ascom Hasler Ag Electronic computing and storage system for franking machines
CH683726A5 (de) * 1992-03-10 1994-04-29 Frama Ag Frankiermaschine.
FR2700043B1 (fr) * 1992-12-30 1995-02-10 Neopost Ind Machine à affranchir permettant de mémoriser un historique.

Also Published As

Publication number Publication date
DE69512718D1 (de) 1999-11-18
FR2722595B1 (fr) 1996-10-04
FR2722595A1 (fr) 1996-01-19
EP0694886A1 (de) 1996-01-31
DE69512718T2 (de) 2000-03-02

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