EP0694886A1 - Elektronisches Frankiersystem mit einem herladbaren Betriebsprogramm in situ - Google Patents

Elektronisches Frankiersystem mit einem herladbaren Betriebsprogramm in situ Download PDF

Info

Publication number
EP0694886A1
EP0694886A1 EP95401701A EP95401701A EP0694886A1 EP 0694886 A1 EP0694886 A1 EP 0694886A1 EP 95401701 A EP95401701 A EP 95401701A EP 95401701 A EP95401701 A EP 95401701A EP 0694886 A1 EP0694886 A1 EP 0694886A1
Authority
EP
European Patent Office
Prior art keywords
memory
microprocessor
circuit
control signal
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP95401701A
Other languages
English (en)
French (fr)
Other versions
EP0694886B1 (de
Inventor
Bernard Vermesse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quadient Technologies France SA
Original Assignee
Neopost Technologies SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Neopost Technologies SA filed Critical Neopost Technologies SA
Publication of EP0694886A1 publication Critical patent/EP0694886A1/de
Application granted granted Critical
Publication of EP0694886B1 publication Critical patent/EP0694886B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00193—Constructional details of apparatus in a franking system
    • G07B2017/00258—Electronic hardware aspects, e.g. type of circuits used
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00314—Communication within apparatus, personal computer [PC] system, or server, e.g. between printhead and central unit in a franking machine
    • G07B2017/00322—Communication between components/modules/parts, e.g. printer, printhead, keyboard, conveyor or central unit
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
    • G07B2017/00395—Memory organization
    • G07B2017/00403—Memory zones protected from unauthorized reading or writing

Definitions

  • the invention relates generally to the field of franking machines which are now widely used in corporate mail forwarding offices.
  • It relates more particularly to an electronic postage system comprising a microprocessor connected by an address bus and a data bus to a non-volatile memory circuit in which an operating program is recorded.
  • operating program is meant a program for controlling the microprocessor in order to obtain a desired operation of the latter. It can be used in particular to manage postage amount accounting information.
  • This information generally includes the amount of funds available in the system (this amount being decremented at each postage transaction) as well as the cumulative amount of postage (this amount being incremented at each postage transaction).
  • This information is kept in the so-called descending and ascending registers in non-volatile memory backed up by battery.
  • Most franking systems have two non-volatile battery backed memories in which the descending and ascending registers are duplicated.
  • Such a franking system is generally mounted inside a sealed enclosure.
  • the operating program is saved in a memory of the EPROM type.
  • Such a memory requires exposure to ultra violet rays to be erased and then reprogrammed in order to change the operating program.
  • the EPROM memory circuit or box must be mounted in the franking system on a support of so as to be removable. The presence of such a support increases the cost of the franking system.
  • this arrangement would cause complications to ensure the level of security of the program data required by the Postal Administrations. In other words, it is not planned today to change, in situ in an electronic franking system, the operating program recorded in a non-volatile memory circuit, that is to say without leaving the circuit memory of the sealed enclosure containing the franking system.
  • the object of the invention is to propose an electronic postage system having a memory circuit arranged in such a way as to allow an in situ change of the operating program recorded in the memory circuit without penalizing the cost price of the system. and without affecting its security level.
  • the subject of the invention is an electronic postage system characterized in that the memory circuit is of the flash memory type having a memory space divided into a plurality of sectors selectively addressable from the address bus, in that an address decoding circuit is provided between the address bus and a terminal of the memory circuit authorizing or prohibiting writing to the memory, this decoding circuit being arranged so that the microprocessor is prevented from '' write in a first sector of the memory in which the operating program is recorded when the decoding circuit detects the presence of a control signal set to a first logic level and the microprocessor is authorized to write in said first sector of the memory when the decoding circuit detects the presence of the control signal set to a second level logic, and in that there is provided a loading program recorded in a second sector of the memory protected before mounting the memory circuit in the system against any write access, this loading program being intended to control the microprocessor of such so that it establishes a dialogue with another processor in order to load a new operating program, supplied by this other processor, in place of the operating program already
  • non-volatile flash memory circuits The technology of non-volatile flash memory circuits is starting to appear on the market and is of interest for an electronic postage system.
  • a memory circuit has a memory space organized into sectors of fixed size selectively erasable by a microprocessor control. The sectors of such a memory are moreover capable of being selectively protected against any write or erase access. This protection is carried out by configuring the flash memory on a programming bench. This protection can therefore be carried out before mounting the flash memory circuit directly on a printed circuit board.
  • Such a non-volatile memory circuit may be suitable for recording the operating program of a franking machine because it has a sufficiently large memory space.
  • the decoding circuit prevents untimely modifications of the operating program in the flash memory, for example in the event of a microprocessor malfunction and contributes to system security.
  • this control signal comes from a conductive line connected to a current source by a removable pin.
  • the control signal is set to its first logic state.
  • the control signal changes logic state which makes the first sector of the memory containing the operating program accessible for erasure and writing by the microprocessor which can then reload a new operating program .
  • the microprocessor, the memory circuit, the address decoding circuit and the removable pin are placed at the inside a sealed enclosure. In this way, only the manufacturer can load a new operating program into the first memory sector.
  • Figure 1 shows in schematic form a first embodiment of the franking system.
  • Figure 2 illustrates the organization into sectors of flash memory.
  • the franking system comprises a microprocessor 1 having seventeen address bits A0-A16 and eight data bits D0-D7, for example the integrated circuit known under the reference "80C166" or the integrated circuit known under the reference "ST10". It also includes a non-volatile flash memory circuit 2, for example the integrated circuit known under the reference "29F10PL".
  • This memory has a capacity of 128 Kilo bytes divided into eight memory sectors of 16 Kilo bytes each. These eight sectors are designated by S1 to S8 in FIG. 2.
  • the data inputs / outputs D0 to D7 of the memory circuit 2 are connected to the respective data inputs / outputs of the microprocessor 1 through a data bus 10 comprising eight data lines.
  • the address inputs A0 to A16 of the memory circuit 2 are connected to the corresponding address outputs of the microprocessor 1 through an address bus 11 comprising seventeen address lines.
  • the memory circuit 2 also includes a read control input OE, a write control input WR and a box selection input CE.
  • the box selection input CE permanently receives an electrical signal of 0 volts so that the memory circuit 2 receives all the read and write commands from the microprocessor 1.
  • the microprocessor 1 also has a read control output RD, a write control output WR, a reserved input of a control signal CHPRG, and a serial input port RXD1 and output TXD1.
  • the read control output RD of the microprocessor is connected to the read control input RD of the memory circuit.
  • the serial RXD1 input and TXD1 output of the microprocessor are connected to a connector 5 through a control bus 12 comprising several control lines.
  • the input of the microprocessor for receiving the CHPRG control signal is connected through the control bus 12 and a removable pin 4 (in the form of a jumper) to a current source delivering an electrical signal from 5 volts corresponding to a logic level equal to 1.
  • An address decoder 3 is also provided, having an output connected to the write command input WE of the memory circuit 2.
  • the address decoder 3 comprises a reversing AND gate 31 with three inputs for receiving respectively the control signal CHPRG and signals coming from the outputs of most significant addresses A15 and A16 of the microprocessor. These last two signals are taken directly from the address bus 11. It also includes a single inverting gate 32 which receives a write command signal coming from the write command output WR of the microprocessor 1. It also includes a another AND reversing gate 33 having a first input connected to the output of gate 31 and two other inputs connected to the output of gate 32. The output of gate 33 is connected to the write command input WR of the circuit memory 2.
  • the microprocessor 1, the memory circuit 2, the address decoder 3 and the pin 4 are enclosed in an enclosure 20 comprising a hatch 21 giving access from outside the enclosure to the pin 4.
  • the hatch normally closes l enclosure and is sealed to prevent unauthorized access to the interior of the enclosure by a user.
  • the connector 5 is freely accessible from the outside of the enclosure 20. However, it could also be enclosed inside the enclosure so as to be accessible only when the hatch 21 is open.
  • the set of circuits 1,2,3,4,5 is mounted on one or more printed circuit boards (not shown), the terminals of the memory circuit 2 being able to be directly soldered on a printed circuit board.
  • the memory space of memory 2 is divided into a plurality of memory sectors of identical capacity, in this case eight sectors S1 to S8 of 16 kilobytes each.
  • a loading program is recorded in sector S1. Furthermore, the sector S1 is protected against erasure or writing, after the loading program is recorded there and before the mounting of the memory circuit 2 directly on the printed circuit board. Such protection is achieved using a specific memory programming device known per se.
  • An operating program for a franking machine is saved in the S7 and S8 sectors of the memory. Sectors S2 to S6 are left free for recording other data.
  • the address decoder 3 prevents write access of the microprocessor in sectors S7 and S8 of the memory since the combination of the signals at the input of gate 31 forces the output of the address decoder at a logic level equal to 1 and that this logic level is that which is necessary to inhibit the write command input WR of the memory circuit 2.
  • the address decoder 3 ensures that the operating program recorded in the sectors S7 and S8 of the memory is not altered by a malfunction of the microprocessor for example.
  • the microprocessor accesses the first bytes recorded in the sector S1 of the memory which constitute the start of the loading program.
  • This loading program is first arranged to test during the start of its execution the logic level of the signal CHPRG received by the microprocessor. If this signal at a logic level equal to 1, the loading program starts the execution of the operating program at the same time as it stops. It is therefore the normal operating framework for the franking system.
  • the CHPRG signal will have a logic level equal to 0.
  • the decoder of addresses 3 allows the write command signal WR coming from the microprocessor to pass authorize the microprocessor to write in the sectors S7 and S8 of the memory.
  • the loading program upon detection of the CHPRG signal at a logic level equal to 0, controls the microprocessor in such a way that it first erases the content of the sectors S7 and S8 and then establishes communication with another processor connected to the serial input / output ports RXD1 and TXD1 via connector 5 in order to load in situ a new operating program in the sectors S7 and S8, this new operating program coming from the other processor .
  • the loading program may stop and block the operation of the franking system. Mailing system power must be turned off. At this time, pin 4 must again be replaced so that the level of the CHPRG signal is equal to 1. Then the franking machine is switched on again and the loading program as indicated above will start the execution of the new operating program.
  • the signal CHPRG can come directly from the microprocessor which is controlled so as to change the logic level of the signal CHPRG in response to a coded message obtained from the serial input port RXD1.
  • the microprocessor of the franking system is connected, for example by a telephone line, to a management center of a fleet of franking systems.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Read Only Memory (AREA)
EP19950401701 1994-07-18 1995-07-18 Elektronisches Frankiersystem mit einem austauschbaren Betriebsprogramm in einem Flash-Speicher Expired - Lifetime EP0694886B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9408859A FR2722595B1 (fr) 1994-07-18 1994-07-18 Systeme d'affranchissement postal electronique ayant un programme d'exploitation rechargeable in situ
FR9408859 1994-07-18

Publications (2)

Publication Number Publication Date
EP0694886A1 true EP0694886A1 (de) 1996-01-31
EP0694886B1 EP0694886B1 (de) 1999-10-13

Family

ID=9465479

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19950401701 Expired - Lifetime EP0694886B1 (de) 1994-07-18 1995-07-18 Elektronisches Frankiersystem mit einem austauschbaren Betriebsprogramm in einem Flash-Speicher

Country Status (3)

Country Link
EP (1) EP0694886B1 (de)
DE (1) DE69512718T2 (de)
FR (1) FR2722595B1 (de)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106320A2 (de) * 1982-10-13 1984-04-25 Pitney Bowes Inc. Elektronische Frankiermaschine mit Rücksetzschaltkreis
WO1989011134A1 (en) * 1988-05-09 1989-11-16 Ascom Hasler Ag Electronic computing and storage system for franking machines
EP0457114A1 (de) * 1985-10-16 1991-11-21 Pitney Bowes Inc. Frankiermaschinensystem zur nichtflüchtigen Speicherung von Daten
EP0560717A2 (de) * 1992-03-10 1993-09-15 Frama Ag Frankiermaschine
EP0605313A1 (de) * 1992-12-30 1994-07-06 Neopost Industrie Frankiermaschine mit Geschichtsabspeicherung

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106320A2 (de) * 1982-10-13 1984-04-25 Pitney Bowes Inc. Elektronische Frankiermaschine mit Rücksetzschaltkreis
EP0457114A1 (de) * 1985-10-16 1991-11-21 Pitney Bowes Inc. Frankiermaschinensystem zur nichtflüchtigen Speicherung von Daten
WO1989011134A1 (en) * 1988-05-09 1989-11-16 Ascom Hasler Ag Electronic computing and storage system for franking machines
EP0560717A2 (de) * 1992-03-10 1993-09-15 Frama Ag Frankiermaschine
EP0605313A1 (de) * 1992-12-30 1994-07-06 Neopost Industrie Frankiermaschine mit Geschichtsabspeicherung

Also Published As

Publication number Publication date
FR2722595B1 (fr) 1996-10-04
EP0694886B1 (de) 1999-10-13
FR2722595A1 (fr) 1996-01-19
DE69512718T2 (de) 2000-03-02
DE69512718D1 (de) 1999-11-18

Similar Documents

Publication Publication Date Title
EP0554164B1 (de) Chipkarte mit mehreren Kommunikationsprotokollen
EP0461971B1 (de) Elektronische Verbindungsvorrichtung
EP1062633B1 (de) Vorrichtung zum maskieren von betriebsvorgängen in einer mikroprozessorkarte
EP0437386B1 (de) Sicherheitsverriegelung für integrierten Schaltkreis
EP0740268B1 (de) Speicherkarte und Vorrichtung zum Betrieb einer solchen Karte
FR2503423A1 (fr) Systeme de cartes a memoire electronique pouvant etre rechargees a des valeurs fiduciaires
FR2646942A1 (fr) Carte a circuit integre
EP0669576B1 (de) Speicherredundanzschaltung
EP0267114B1 (de) Integrierte Schaltung zur Speicherung und zur vertraulichen Verarbeitung von Informationen, die eine Antibetrugsvorrichtung enthält
EP1292889A1 (de) Gesicherter eeprom-speicher mit fehlerkorrekturschaltung
FR2693581A1 (fr) Dispositif de mémorisation à semi-conducteurs et méthode d'accès à ce dispositif.
JP2000148507A (ja) 制御装置のプログラミング方法およびプログラミング装置
EP0735489A1 (de) Verfahren zum Schützen nichtflüchtiger Speicherbereiche
FR2594984A1 (fr) Element a carte de circuits integres pour dispositif de traitement de donnees
FR2711832A1 (fr) Carte de mémoire non volatile avec indication prêt occupé et minimisation de compte de broches.
EP0694886B1 (de) Elektronisches Frankiersystem mit einem austauschbaren Betriebsprogramm in einem Flash-Speicher
FR2691832A1 (fr) Circuit de commande de mémoire pour une carte à mémoire.
FR2618926A1 (fr) Dispositif a memoire de controle de l'utilisation d'un logiciel, du type cle
EP1374249A1 (de) Vorrichtung und verfahren zur teilweisen lesebeschützung eines nichtflüchtigen speichers
FR2604554A1 (fr) Dispositif de securite pourla programmation d'une memoire non volatile programmable electriquement
EP0851359A1 (de) Speicher mit lesegeschützten Zonen
FR2788353A1 (fr) Microprocesseur avec circuits de protection pour securiser l'acces a ses registres
FR2756410A1 (fr) Dispositif de protection apres une ecriture de page d'une memoire electriquement programmable
EP0328436B1 (de) Verfahren und Anordnung zur Teildekodierung des Vorsatzes einer Kommunikationsnachricht, gesendet von einer ersten nach mindestens einer zweiten Station, insbesondere in einem Fahrzeug
WO2001082212A1 (fr) Interface de connexion entre des lecteurs de cartes à puce et système de connexion entre des lecteurs comprenant une telle interface

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19960509

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 19990112

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 69512718

Country of ref document: DE

Date of ref document: 19991118

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19991201

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20100805

Year of fee payment: 16

Ref country code: DE

Payment date: 20100723

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20100722

Year of fee payment: 16

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 69512718

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20110718

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20120330

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120201

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20110801

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 69512718

Country of ref document: DE

Effective date: 20120201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20110718